mach-stm32: Factorize MPU's region config for STM32 SoCs

MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family
and used a common MPU's region config.

Only one exception for STM32H7 which doesn't have device area
located at 0xA000 0000.

For STM32F4, configure_clocks() need to be moved from arch_cpu_init()
to board_early_init_f().

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
This commit is contained in:
Patrice Chotard 2017-11-16 08:59:21 +01:00 committed by Tom Rini
parent 014a953c4a
commit c729fb258a
8 changed files with 16 additions and 116 deletions

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@ -4,7 +4,6 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += soc.o
obj-$(CONFIG_STM32F4) += stm32f4/
obj-$(CONFIG_STM32F7) += stm32f7/
obj-$(CONFIG_STM32H7) += stm32h7/

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@ -9,11 +9,6 @@
#include <asm/io.h>
#include <asm/armv7m_mpu.h>
u32 get_cpu_rev(void)
{
return 0;
}
int arch_cpu_init(void)
{
int i;
@ -30,11 +25,11 @@ int arch_cpu_init(void)
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_4GB },
/* Code area, executable & strongly ordered */
{ 0xD0000000, REGION_1, XN_EN, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_8MB },
/* armv7m code area */
{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_512MB },
/* Device area in all H7 : Not executable */
/* Device area : Not executable */
{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
DEVICE_NON_SHARED, REGION_512MB },
@ -42,8 +37,14 @@ int arch_cpu_init(void)
* Armv7m fixed configuration: strongly ordered & not
* executable, not cacheable
*/
{ 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
{ 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_512MB },
#if !defined(CONFIG_STM32H7)
/* Device area : Not executable */
{ 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
DEVICE_NON_SHARED, REGION_512MB },
#endif
};
disable_mpu();
@ -53,7 +54,3 @@ int arch_cpu_init(void)
return 0;
}
void s_init(void)
{
}

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@ -8,4 +8,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += soc.o clock.o timer.o
obj-y += clock.o timer.o

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@ -1,41 +0,0 @@
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/armv7m_mpu.h>
#include <asm/arch/stm32.h>
u32 get_cpu_rev(void)
{
return 0;
}
int arch_cpu_init(void)
{
struct mpu_region_config stm32_region_config[] = {
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_4GB },
};
int i;
configure_clocks();
/*
* Configure the memory protection unit (MPU) to allow full access to
* the whole 4GB address space.
*/
disable_mpu();
for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
mpu_config(&stm32_region_config[i]);
enable_mpu();
return 0;
}
void s_init(void)
{
}

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@ -5,4 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += timer.o soc.o
obj-y += timer.o

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@ -1,49 +0,0 @@
/*
* (C) Copyright 2015
* Kamil Lulko, <kamil.lulko@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/armv7m_mpu.h>
#include <asm/arch/stm32.h>
u32 get_cpu_rev(void)
{
return 0;
}
int arch_cpu_init(void)
{
int i;
struct mpu_region_config stm32_region_config[] = {
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
O_I_WB_RD_WR_ALLOC, REGION_4GB },
{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_512MB },
{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
DEVICE_NON_SHARED, REGION_512MB },
{ 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
DEVICE_NON_SHARED, REGION_512MB },
{ 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
STRONG_ORDER, REGION_512MB },
};
disable_mpu();
for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
mpu_config(&stm32_region_config[i]);
enable_mpu();
return 0;
}
void s_init(void)
{
}

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@ -1,8 +0,0 @@
#
# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += soc.o

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@ -294,6 +294,8 @@ int board_early_init_f(void)
{
int res;
configure_clocks();
res = uart_setup_gpio();
if (res)
return res;