mach-stm32: Factorize MPU's region config for STM32 SoCs
MPU's region setup can be factorized between STM32F4/F7/H7 SoCs family and used a common MPU's region config. Only one exception for STM32H7 which doesn't have device area located at 0xA000 0000. For STM32F4, configure_clocks() need to be moved from arch_cpu_init() to board_early_init_f(). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
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@ -4,7 +4,6 @@
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += soc.o
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obj-$(CONFIG_STM32F4) += stm32f4/
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obj-$(CONFIG_STM32F7) += stm32f7/
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obj-$(CONFIG_STM32H7) += stm32h7/
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@ -9,11 +9,6 @@
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#include <asm/io.h>
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#include <asm/armv7m_mpu.h>
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u32 get_cpu_rev(void)
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{
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return 0;
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}
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int arch_cpu_init(void)
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{
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int i;
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@ -30,11 +25,11 @@ int arch_cpu_init(void)
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{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
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O_I_WB_RD_WR_ALLOC, REGION_4GB },
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/* Code area, executable & strongly ordered */
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{ 0xD0000000, REGION_1, XN_EN, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_8MB },
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/* armv7m code area */
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{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_512MB },
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/* Device area in all H7 : Not executable */
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/* Device area : Not executable */
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{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
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DEVICE_NON_SHARED, REGION_512MB },
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@ -42,8 +37,14 @@ int arch_cpu_init(void)
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* Armv7m fixed configuration: strongly ordered & not
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* executable, not cacheable
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*/
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{ 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
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{ 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_512MB },
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#if !defined(CONFIG_STM32H7)
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/* Device area : Not executable */
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{ 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
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DEVICE_NON_SHARED, REGION_512MB },
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#endif
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};
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disable_mpu();
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@ -53,7 +54,3 @@ int arch_cpu_init(void)
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return 0;
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}
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void s_init(void)
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{
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}
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@ -8,4 +8,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += soc.o clock.o timer.o
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obj-y += clock.o timer.o
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@ -1,41 +0,0 @@
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/*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7m_mpu.h>
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#include <asm/arch/stm32.h>
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u32 get_cpu_rev(void)
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{
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return 0;
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}
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int arch_cpu_init(void)
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{
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struct mpu_region_config stm32_region_config[] = {
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{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_4GB },
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};
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int i;
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configure_clocks();
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/*
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* Configure the memory protection unit (MPU) to allow full access to
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* the whole 4GB address space.
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*/
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disable_mpu();
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for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
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mpu_config(&stm32_region_config[i]);
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enable_mpu();
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return 0;
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}
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void s_init(void)
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{
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}
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@ -5,4 +5,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += timer.o soc.o
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obj-y += timer.o
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@ -1,49 +0,0 @@
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/*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7m_mpu.h>
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#include <asm/arch/stm32.h>
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u32 get_cpu_rev(void)
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{
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return 0;
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}
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int arch_cpu_init(void)
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{
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int i;
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struct mpu_region_config stm32_region_config[] = {
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{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
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O_I_WB_RD_WR_ALLOC, REGION_4GB },
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{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_512MB },
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{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
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DEVICE_NON_SHARED, REGION_512MB },
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{ 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
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DEVICE_NON_SHARED, REGION_512MB },
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{ 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_512MB },
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};
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disable_mpu();
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for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
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mpu_config(&stm32_region_config[i]);
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enable_mpu();
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return 0;
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}
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void s_init(void)
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{
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}
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@ -1,8 +0,0 @@
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#
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# Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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# Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += soc.o
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@ -294,6 +294,8 @@ int board_early_init_f(void)
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{
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int res;
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configure_clocks();
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res = uart_setup_gpio();
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if (res)
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return res;
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