board: phytec: imx8mp: Add PHYTEC phyCORE-i.MX8MP support
Add initial support PHYTEC phyCORE-i.MX8MP SOM.
Supported features:
- 2GB LPDDR4 RAM
- eMMC
- external SD
- debug UART2
- watchdog
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Teresa Remmet
Stefano Babic
parent
3f832699ff
commit
c661c511e9
@ -786,6 +786,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
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imx8mm-beacon-kit.dtb \
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imx8mq-phanbell.dtb \
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imx8mp-evk.dtb \
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imx8mp-phyboard-pollux-rdk.dtb \
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imx8mq-pico-pi.dtb
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dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \
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114
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
Normal file
114
arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
Normal file
@ -0,0 +1,114 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/ {
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wdt-reboot {
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compatible = "wdt-reboot";
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wdt = <&wdog1>;
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u-boot,dm-spl;
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};
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};
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&{/soc@0} {
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u-boot,dm-pre-reloc;
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u-boot,dm-spl;
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};
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&clk {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&osc_32k {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&osc_24m {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&aips1 {
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u-boot,dm-spl;
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u-boot,dm-pre-reloc;
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};
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&aips2 {
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u-boot,dm-spl;
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};
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&aips3 {
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u-boot,dm-spl;
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};
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&iomuxc {
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u-boot,dm-spl;
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};
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®_usdhc2_vmmc {
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u-boot,dm-spl;
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};
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&pinctrl_uart2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2_pins {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc2 {
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u-boot,dm-spl;
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};
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&pinctrl_usdhc3 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&uart2 {
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u-boot,dm-spl;
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};
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&i2c1 {
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u-boot,dm-spl;
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};
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&pmic {
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u-boot,dm-spl;
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};
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&usdhc2 {
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u-boot,dm-spl;
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};
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&usdhc3 {
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u-boot,dm-spl;
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};
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&wdog1 {
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u-boot,dm-spl;
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};
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161
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
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161
arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
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@ -0,0 +1,161 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/dts-v1/;
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#include <dt-bindings/leds/leds-pca9532.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx8mp-phycore-som.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Pollux i.MX8MP";
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compatible = "phytec,imx8mp-phyboard-pollux-rdk",
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"phytec,imx8mp-phycore-som", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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leds@62 {
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compatible = "nxp,pca9533";
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reg = <0x62>;
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led1 {
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type = <PCA9532_TYPE_LED>;
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};
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led2 {
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type = <PCA9532_TYPE_LED>;
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};
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led3 {
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type = <PCA9532_TYPE_LED>;
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};
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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/* debug console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* SD-Card */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
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MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
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>;
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};
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pinctrl_usdhc2_pins: usdhc2-gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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};
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293
arch/arm/dts/imx8mp-phycore-som.dtsi
Normal file
293
arch/arm/dts/imx8mp-phycore-som.dtsi
Normal file
@ -0,0 +1,293 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#include <dt-bindings/net/ti-dp83867.h>
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#include "imx8mp.dtsi"
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/ {
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model = "PHYTEC phyCORE-i.MX8MP";
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compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
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aliases {
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rtc0 = &rv3028;
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rtc1 = &snvs_rtc;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2>;
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};
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&A53_1 {
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cpu-supply = <&buck2>;
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};
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&A53_2 {
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cpu-supply = <&buck2>;
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};
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&A53_3 {
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cpu-supply = <&buck2>;
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};
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/* ethernet 1 */
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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interrupt-parent = <&gpio1>;
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interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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enet-phy-lane-no-swap;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pmic: pmic@25 {
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reg = <0x25>;
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compatible = "nxp,pca9450c";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio4>;
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interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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buck1: BUCK1 {
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regulator-compatible = "BUCK1";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-compatible = "BUCK2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck4: BUCK4 {
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regulator-compatible = "BUCK4";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5 {
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regulator-compatible = "BUCK5";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-compatible = "BUCK6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-compatible = "LDO1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2: LDO2 {
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regulator-compatible = "LDO2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3: LDO3 {
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regulator-compatible = "LDO3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-compatible = "LDO4";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-compatible = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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rv3028: rtc@52 {
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compatible = "microcrystal,rv3028";
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reg = <0x52>;
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trickle-resistor-ohms = <3000>;
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};
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};
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/* eMMC */
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&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
|
||||
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
||||
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
|
||||
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
|
||||
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicirqgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -77,6 +77,12 @@ config TARGET_PHYCORE_IMX8MM
|
||||
select IMX8MM
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
|
||||
config TARGET_PHYCORE_IMX8MP
|
||||
bool "PHYTEC PHYCORE i.MX8MP"
|
||||
select IMX8MP
|
||||
select SUPPORT_SPL
|
||||
select IMX8M_LPDDR4
|
||||
endchoice
|
||||
|
||||
source "board/freescale/imx8mq_evk/Kconfig"
|
||||
@ -88,5 +94,6 @@ source "board/technexion/pico-imx8mq/Kconfig"
|
||||
source "board/toradex/verdin-imx8mm/Kconfig"
|
||||
source "board/beacon/imx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mm/Kconfig"
|
||||
source "board/phytec/phycore_imx8mp/Kconfig"
|
||||
|
||||
endif
|
||||
|
||||
12
board/phytec/phycore_imx8mp/Kconfig
Normal file
12
board/phytec/phycore_imx8mp/Kconfig
Normal file
@ -0,0 +1,12 @@
|
||||
if TARGET_PHYCORE_IMX8MP
|
||||
|
||||
config SYS_BOARD
|
||||
default "phycore_imx8mp"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "phytec"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "phycore_imx8mp"
|
||||
|
||||
endif
|
||||
9
board/phytec/phycore_imx8mp/MAINTAINERS
Normal file
9
board/phytec/phycore_imx8mp/MAINTAINERS
Normal file
@ -0,0 +1,9 @@
|
||||
phyCORE-i.MX8M Plus
|
||||
M: Teresa Remmet <t.remmet@phytec.de>
|
||||
W: https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus/
|
||||
S: Maintained
|
||||
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk.dts
|
||||
F: arch/arm/dts/imx8mp-phyboard-pollux-rdk-u-boot.dtsi
|
||||
F: board/phytec/phycore_imx8mp/
|
||||
F: configs/phycore-imx8mp_defconfig
|
||||
F: include/configs/phycore_imx8mp.h
|
||||
11
board/phytec/phycore_imx8mp/Makefile
Normal file
11
board/phytec/phycore_imx8mp/Makefile
Normal file
@ -0,0 +1,11 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
#
|
||||
# Copyright (C) 2020 PHYTEC Messtechnik GmbH
|
||||
# Author: Teresa Remmet <t.remmet@phytec.de>
|
||||
|
||||
obj-y += phycore-imx8mp.o
|
||||
|
||||
ifdef CONFIG_SPL_BUILD
|
||||
obj-y += spl.o
|
||||
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
|
||||
endif
|
||||
1849
board/phytec/phycore_imx8mp/lpddr4_timing.c
Normal file
1849
board/phytec/phycore_imx8mp/lpddr4_timing.c
Normal file
File diff suppressed because it is too large
Load Diff
39
board/phytec/phycore_imx8mp/phycore-imx8mp.c
Normal file
39
board/phytec/phycore_imx8mp/phycore-imx8mp.c
Normal file
@ -0,0 +1,39 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
|
||||
* Author: Teresa Remmet <t.remmet@phytec.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <env.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
switch (get_boot_device()) {
|
||||
case SD2_BOOT:
|
||||
env_set_ulong("mmcdev", 1);
|
||||
break;
|
||||
case MMC3_BOOT:
|
||||
env_set_ulong("mmcdev", 2);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
129
board/phytec/phycore_imx8mp/spl.c
Normal file
129
board/phytec/phycore_imx8mp/spl.c
Normal file
@ -0,0 +1,129 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
|
||||
* Author: Teresa Remmet <t.remmet@phytec.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/ddr.h>
|
||||
#include <asm/arch/imx8mp_pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <hang.h>
|
||||
#include <init.h>
|
||||
#include <log.h>
|
||||
#include <power/pmic.h>
|
||||
#include <power/pca9450.h>
|
||||
#include <spl.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
||||
{
|
||||
return BOOT_DEVICE_BOOTROM;
|
||||
}
|
||||
|
||||
void spl_dram_init(void)
|
||||
{
|
||||
ddr_init(&dram_timing);
|
||||
}
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
struct i2c_pads_info i2c_pad_info1 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
|
||||
.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 14),
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
|
||||
.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 15),
|
||||
},
|
||||
};
|
||||
|
||||
int power_init_board(void)
|
||||
{
|
||||
struct pmic *p;
|
||||
int ret;
|
||||
|
||||
ret = power_pca9450_init(0);
|
||||
if (ret)
|
||||
printf("power init failed");
|
||||
p = pmic_get("PCA9450");
|
||||
pmic_probe(p);
|
||||
|
||||
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
||||
pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29);
|
||||
|
||||
/* increase VDD_SOC to typical value 0.95V */
|
||||
pmic_reg_write(p, PCA9450_BUCK2OUT_DVS0, 0x1C);
|
||||
|
||||
/* set WDOG_B_CFG to cold reset */
|
||||
pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
||||
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
||||
|
||||
static iomux_v3_cfg_t const uart_pads[] = {
|
||||
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static iomux_v3_cfg_t const wdog_pads[] = {
|
||||
MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
||||
};
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
||||
|
||||
set_wdog_reset(wdog);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
int ret;
|
||||
|
||||
arch_cpu_init();
|
||||
|
||||
init_uart_clk(1);
|
||||
|
||||
board_early_init_f();
|
||||
|
||||
ret = spl_early_init();
|
||||
if (ret) {
|
||||
debug("spl_early_init() failed: %d\n", ret);
|
||||
hang();
|
||||
}
|
||||
|
||||
preloader_console_init();
|
||||
|
||||
enable_tzc380();
|
||||
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
|
||||
power_init_board();
|
||||
|
||||
/* DDR initialization */
|
||||
spl_dram_init();
|
||||
}
|
||||
95
configs/phycore-imx8mp_defconfig
Normal file
95
configs/phycore-imx8mp_defconfig
Normal file
@ -0,0 +1,95 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8M=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x10000
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x3C0000
|
||||
CONFIG_SYS_I2C_MXC_I2C1=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_SPL_TEXT_BASE=0x920000
|
||||
CONFIG_TARGET_PHYCORE_IMX8MP=y
|
||||
CONFIG_SPL_MMC_SUPPORT=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx8mp-phyboard-pollux-rdk"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
|
||||
CONFIG_SPL_LOAD_FIT=y
|
||||
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
|
||||
CONFIG_OF_SYSTEM_SETUP=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg"
|
||||
CONFIG_DEFAULT_FDT_FILE="oftree"
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_SPL_BOOTROM_SUPPORT=y
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
CONFIG_SPL_SEPARATE_BSS=y
|
||||
CONFIG_SPL_I2C_SUPPORT=y
|
||||
CONFIG_SPL_POWER_SUPPORT=y
|
||||
CONFIG_SPL_WATCHDOG_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="u-boot=> "
|
||||
# CONFIG_CMD_EXPORTENV is not set
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
# CONFIG_CMD_CRC32 is not set
|
||||
CONFIG_CMD_EEPROM=y
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_FUSE=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_REGULATOR=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_SPL_OF_CONTROL=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=2
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_SPL_DM=y
|
||||
CONFIG_CLK_COMPOSITE_CCF=y
|
||||
CONFIG_CLK_IMX8MP=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MXC=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_I2C_EEPROM=y
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
|
||||
CONFIG_SYS_EEPROM_SIZE=4096
|
||||
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
|
||||
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
|
||||
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_SUPPORT_EMMC_BOOT=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_ES_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SPL_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8M=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_SYSRESET_PSCI=y
|
||||
CONFIG_SYSRESET_WATCHDOG=y
|
||||
CONFIG_DM_THERMAL=y
|
||||
CONFIG_IMX_WATCHDOG=y
|
||||
107
include/configs/phycore_imx8mp.h
Normal file
107
include/configs/phycore_imx8mp.h
Normal file
@ -0,0 +1,107 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later
|
||||
*
|
||||
* Copyright (C) 2020 PHYTEC Messtechnik GmbH
|
||||
* Author: Teresa Remmet <t.remmet@phytec.de>
|
||||
*/
|
||||
|
||||
#ifndef __PHYCORE_IMX8MP_H
|
||||
#define __PHYCORE_IMX8MP_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_SYS_BOOTM_LEN SZ_64M
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
|
||||
#define CONFIG_SYS_MONITOR_LEN SZ_512K
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
|
||||
#define CONFIG_SYS_UBOOT_BASE \
|
||||
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
|
||||
#define CONFIG_SPL_STACK 0x960000
|
||||
#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
|
||||
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
|
||||
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
|
||||
|
||||
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
|
||||
|
||||
#define CONFIG_POWER
|
||||
#define CONFIG_POWER_I2C
|
||||
#define CONFIG_POWER_PCA9450
|
||||
|
||||
#undef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"image=Image\0" \
|
||||
"console=ttymxc1,115200\0" \
|
||||
"fdt_addr=0x48000000\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=2\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi;\0 " \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi;"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x40480000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN SZ_32M
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
||||
|
||||
#define PHYS_SDRAM 0x40000000
|
||||
#define PHYS_SDRAM_SIZE 0x80000000
|
||||
|
||||
/* UART */
|
||||
#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE SZ_2K
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
/* USDHC */
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
#endif /* __PHYCORE_IMX8MP_H */
|
||||
Loading…
Reference in New Issue
Block a user