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net: designware: set the PS bit when resetting DMA bus in MII configuration

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On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block,
the DMA reset never succeeds when a MII PHY is used (no problem with a
GMII PHY). The designware_eth_init() function sets the
DMAMAC_SRST bit in the DMA_BUS_MODE register, and then
polls until this bit clears. When a MII PHY is used, with the current
driver, this bit never clears and the driver therefore doesn't work.

The reason is that the PS bit of the GMAC_CONTROL register should be
correctly configured for the DMA reset to work. When the PS bit is 0,
it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells
the MAC we have a MII PHY.

Doing a DMA reset clears all registers, so the PS bit is cleared as
well. This makes the DMA reset work fine with a GMII PHY. However,
with MII PHY, the PS bit should be set.

We have identified this issue thanks to two SPEAr600 platform:

- One equipped with a GMII PHY, with which the existing driver was
working fine.

- One equipped with a MII PHY, where the current driver fails because
the DMA reset times out.

Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Quentin Schulz 2018-06-04 12:17:33 +02:00 committed by Joe Hershberger
parent 3cb51dad0d
commit c61221948c
1 changed files with 9 additions and 0 deletions
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9
drivers/net/designware.c
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@ -280,6 +280,15 @@ int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
/*
* When a MII PHY is used, we must set the PS bit for the DMA
* reset to succeed.
*/
if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
else
writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
start = get_timer(0);
while (readl(&dma_p->busmode) & DMAMAC_SRST) {
if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {