Add initial support for Freescale mx51evk board
The patch adds initial support for the Freescale mx51evk board. Network (FEC) and SD controller (fsl_esdhc) are supported. Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>
This commit is contained in:
Stefano Babic
Tom Rix
parent
c67bee1460
commit
c5fb70c911
@ -150,6 +150,10 @@ Dave Ellis <DGE@sixnetio.com>
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SXNI855T MPC8xx
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Fred Fan <fanyefeng@gmail.com>
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mx51evk i.MX51
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Thomas Frieden <ThomasF@hyperion-entertainment.com>
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AmigaOneG3SE MPC7xx
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1
MAKEALL
1
MAKEALL
@ -633,6 +633,7 @@ LIST_ARM11=" \
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#########################################################################
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LIST_ARM_CORTEX_A8=" \
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devkit8000 \
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mx51evk \
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omap3_beagle \
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omap3_overo \
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omap3_evm \
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4
Makefile
4
Makefile
@ -3300,6 +3300,9 @@ mx31pdk_nand_config : unconfig
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fi
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@$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31
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mx51evk_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx51evk freescale mx51
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omap2420h4_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 ti omap24xx
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@ -3771,6 +3774,7 @@ clobber: clean
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$(obj)cscope.* $(obj)*.*~
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@rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL)
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@rm -f $(obj)u-boot.kwb
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@rm -f $(obj)u-boot.imx
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@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
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@rm -f $(obj)cpu/mpc824x/bedbug_603e.c
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@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
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48
board/freescale/mx51evk/Makefile
Normal file
48
board/freescale/mx51evk/Makefile
Normal file
@ -0,0 +1,48 @@
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2009 Freescale Semiconductor, Inc.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := mx51evk.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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25
board/freescale/mx51evk/config.mk
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25
board/freescale/mx51evk/config.mk
Normal file
@ -0,0 +1,25 @@
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#
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# Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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LDSCRIPT = cpu/$(CPU)/$(SOC)/u-boot.lds
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TEXT_BASE = 0x97800000
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IMX_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/imximage.cfg
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119
board/freescale/mx51evk/imximage.cfg
Normal file
119
board/freescale/mx51evk/imximage.cfg
Normal file
@ -0,0 +1,119 @@
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#
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# (C Copyright 2009
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# Stefano Babic DENX Software Engineering sbabic@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not write to the Free Software
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# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
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# MA 02110-1301 USA
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#
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# Refer docs/README.imxmage for more details about how-to configure
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# and create imximage boot image
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#
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# The syntax is taken as close as possible with the kwbimage
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# Boot Device : one of
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# spi_flash, nand, onenand, sd_card
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BOOT_FROM spi
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# Device Configuration Data (DCD)
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#
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# Each entry must have the format:
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# Addr-type Address Value
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#
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# where:
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# Addr-type register length (1,2 or 4 bytes)
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# Address absolute address of the register
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# value value to be stored in the register
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# Setting IOMUXC
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DATA 4 0x73FA88a0 0x200
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DATA 4 0x73FA850c 0x20c5
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DATA 4 0x73FA8510 0x20c5
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DATA 4 0x73FA883c 0x2
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DATA 4 0x73FA8848 0x2
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DATA 4 0x73FA84b8 0xe7
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DATA 4 0x73FA84bc 0x45
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DATA 4 0x73FA84c0 0x45
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DATA 4 0x73FA84c4 0x45
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DATA 4 0x73FA84c8 0x45
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DATA 4 0x73FA8820 0x0
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DATA 4 0x73FA84a4 0x3
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DATA 4 0x73FA84a8 0x3
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DATA 4 0x73FA84ac 0xe3
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DATA 4 0x73FA84b0 0xe3
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DATA 4 0x73FA84b4 0xe3
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DATA 4 0x73FA84cc 0xe3
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DATA 4 0x73FA84d0 0xe2
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DATA 4 0x73FA882c 0x6
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DATA 4 0x73FA88a4 0x6
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DATA 4 0x73FA88ac 0x6
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DATA 4 0x73FA88b8 0x6
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# Setting DDR for micron
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# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
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# CAS=3 BL=4
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# ESDCTL_ESDCTL0
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DATA 4 0x83FD9000 0x82a20000
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# ESDCTL_ESDCTL1
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DATA 4 0x83FD9008 0x82a20000
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# ESDCTL_ESDMISC
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DATA 4 0x83FD9010 0x000ad0d0
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# ESDCTL_ESDCFG0
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DATA 4 0x83FD9004 0x333574aa
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# ESDCTL_ESDCFG1
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DATA 4 0x83FD900C 0x333574aa
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# Init DRAM on CS0
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# ESDCTL_ESDSCR
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DATA 4 0x83FD9014 0x04008008
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DATA 4 0x83FD9014 0x0000801a
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DATA 4 0x83FD9014 0x0000801b
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DATA 4 0x83FD9014 0x00448019
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DATA 4 0x83FD9014 0x07328018
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DATA 4 0x83FD9014 0x04008008
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DATA 4 0x83FD9014 0x00008010
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DATA 4 0x83FD9014 0x00008010
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DATA 4 0x83FD9014 0x06328018
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DATA 4 0x83FD9014 0x03808019
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DATA 4 0x83FD9014 0x00408019
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DATA 4 0x83FD9014 0x00008000
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# Init DRAM on CS1
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DATA 4 0x83FD9014 0x0400800c
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DATA 4 0x83FD9014 0x0000801e
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DATA 4 0x83FD9014 0x0000801f
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DATA 4 0x83FD9014 0x0000801d
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DATA 4 0x83FD9014 0x0732801c
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DATA 4 0x83FD9014 0x0400800c
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DATA 4 0x83FD9014 0x00008014
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DATA 4 0x83FD9014 0x00008014
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DATA 4 0x83FD9014 0x0632801c
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DATA 4 0x83FD9014 0x0380801d
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DATA 4 0x83FD9014 0x0040801d
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DATA 4 0x83FD9014 0x00008004
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# Write to CTL0
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DATA 4 0x83FD9000 0xb2a20000
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# Write to CTL1
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DATA 4 0x83FD9008 0xb2a20000
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# ESDMISC
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DATA 4 0x83FD9010 0x000ad6d0
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#ESDCTL_ESDCDLYGD
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DATA 4 0x83FD9034 0x90000000
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DATA 4 0x83FD9014 0x00000000
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406
board/freescale/mx51evk/mx51evk.c
Normal file
406
board/freescale/mx51evk/mx51evk.c
Normal file
@ -0,0 +1,406 @@
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/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx51_pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include "mx51evk.h"
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DECLARE_GLOBAL_DATA_PTR;
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static u32 system_rev;
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struct io_board_ctrl *mx51_io_board;
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR, 1, 1},
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{MMC_SDHC2_BASE_ADDR, 1, 1},
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};
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#endif
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u32 get_board_rev(void)
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{
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return system_rev;
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}
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static inline void set_board_rev(int rev)
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{
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system_rev |= (rev & 0xF) << 8;
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}
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inline int is_soc_rev(int rev)
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{
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return (system_rev & 0xFF) - rev;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
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PHYS_SDRAM_1_SIZE);
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return 0;
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}
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static void setup_iomux_uart(void)
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{
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unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
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mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
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mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
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mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
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}
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static void setup_expio(void)
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{
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u32 reg;
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struct weim *pweim = (struct weim *)WEIM_BASE_ADDR;
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struct clkctl *pclkctl = (struct clkctl *)CCM_BASE_ADDR;
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/* CS5 setup */
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mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0);
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writel(0x00410089, &pweim[5].csgcr1);
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writel(0x00000002, &pweim[5].csgcr2);
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/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
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writel(0x32260000, &pweim[5].csrcr1);
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/* APR = 0 */
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writel(0x00000000, &pweim[5].csrcr2);
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/*
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* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0,
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* WCSA=0, WCSN=0
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*/
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writel(0x72080F00, &pweim[5].cswcr1);
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mx51_io_board = (struct io_board_ctrl *)(CS5_BASE_ADDR +
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IO_BOARD_OFFSET);
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if ((readw(&mx51_io_board->id1) == 0xAAAA) &&
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(readw(&mx51_io_board->id2) == 0x5555)) {
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if (is_soc_rev(CHIP_REV_2_0) < 0) {
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reg = readl(&pclkctl->cbcdr);
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reg = (reg & (~0x70000)) | 0x30000;
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writel(reg, &pclkctl->cbcdr);
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/* make sure divider effective */
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while (readl(&pclkctl->cdhipr) != 0)
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;
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writel(0x0, &pclkctl->ccdr);
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}
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} else {
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/* CS1 */
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writel(0x00410089, &pweim[1].csgcr1);
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writel(0x00000002, &pweim[1].csgcr2);
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/* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */
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writel(0x32260000, &pweim[1].csrcr1);
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/* APR=0 */
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writel(0x00000000, &pweim[1].csrcr2);
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/*
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* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0,
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* WEN=0, WCSA=0, WCSN=0
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*/
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writel(0x72080F00, &pweim[1].cswcr1);
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mx51_io_board = (struct io_board_ctrl *)(CS1_BASE_ADDR +
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IO_BOARD_OFFSET);
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}
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/* Reset interrupt status reg */
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writew(0x1F, &(mx51_io_board->int_rest));
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writew(0x00, &(mx51_io_board->int_rest));
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writew(0xFFFF, &(mx51_io_board->int_mask));
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/* Reset the XUART and Ethernet controllers */
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reg = readw(&(mx51_io_board->sw_reset));
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reg |= 0x9;
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writew(reg, &(mx51_io_board->sw_reset));
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reg &= ~0x9;
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writew(reg, &(mx51_io_board->sw_reset));
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}
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX51_PIN_EIM_EB2 , IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB2 , 0x1FD);
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/*FEC_MDC*/
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mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, 0x2004);
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/* FEC RDATA[3] */
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mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS3, 0x180);
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/* FEC RDATA[2] */
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mxc_request_iomux(MX51_PIN_EIM_CS2, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_CS2, 0x180);
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/* FEC RDATA[1] */
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mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX51_PIN_EIM_EB3, 0x180);
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/* FEC RDATA[0] */
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mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX51_PIN_NANDF_D9, 0x2180);
|
||||
|
||||
/* FEC TDATA[3] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, 0x2004);
|
||||
|
||||
/* FEC TDATA[2] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, 0x2004);
|
||||
|
||||
/* FEC TDATA[1] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, 0x2004);
|
||||
|
||||
/* FEC TDATA[0] */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D8, 0x2004);
|
||||
|
||||
/* FEC TX_EN */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS7, 0x2004);
|
||||
|
||||
/* FEC TX_ER */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, 0x2004);
|
||||
|
||||
/* FEC TX_CLK */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RDY_INT, 0x2180);
|
||||
|
||||
/* FEC TX_COL */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB2, 0x2180);
|
||||
|
||||
/* FEC RX_CLK */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT1);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, 0x2180);
|
||||
|
||||
/* FEC RX_CRS */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS5, 0x180);
|
||||
|
||||
/* FEC RX_ER */
|
||||
mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_ALT3);
|
||||
mxc_iomux_set_pad(MX51_PIN_EIM_CS4, 0x180);
|
||||
|
||||
/* FEC RX_DV */
|
||||
mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT2);
|
||||
mxc_iomux_set_pad(MX51_PIN_NANDF_D11, 0x2180);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC
|
||||
int board_mmc_getcd(u8 *cd, struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
|
||||
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
|
||||
*cd = readl(GPIO1_BASE_ADDR) & 0x01;
|
||||
else
|
||||
*cd = readl(GPIO1_BASE_ADDR) & 0x40;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
u32 index;
|
||||
s32 status = 0;
|
||||
|
||||
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
|
||||
index++) {
|
||||
switch (index) {
|
||||
case 0:
|
||||
mxc_request_iomux(MX51_PIN_SD1_CMD,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_CLK,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA0,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA1,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA2,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD1_DATA3,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_NONE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH |
|
||||
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PD |
|
||||
PAD_CTL_PUE_PULL |
|
||||
PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_0,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_0,
|
||||
PAD_CTL_HYS_ENABLE);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_1,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
|
||||
PAD_CTL_HYS_ENABLE);
|
||||
break;
|
||||
case 1:
|
||||
mxc_request_iomux(MX51_PIN_SD2_CMD,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD2_CLK,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA0,
|
||||
IOMUX_CONFIG_ALT0);
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA1,
|
||||
IOMUX_CONFIG_ALT0);
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA2,
|
||||
IOMUX_CONFIG_ALT0);
|
||||
mxc_request_iomux(MX51_PIN_SD2_DATA3,
|
||||
IOMUX_CONFIG_ALT0);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
||||
PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
||||
PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
||||
PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
||||
PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
||||
PAD_CTL_SRE_FAST);
|
||||
mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
|
||||
PAD_CTL_DRV_MAX | PAD_CTL_22K_PU |
|
||||
PAD_CTL_SRE_FAST);
|
||||
mxc_request_iomux(MX51_PIN_SD2_CMD,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_6,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_6,
|
||||
PAD_CTL_HYS_ENABLE);
|
||||
mxc_request_iomux(MX51_PIN_GPIO1_5,
|
||||
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
|
||||
mxc_iomux_set_pad(MX51_PIN_GPIO1_5,
|
||||
PAD_CTL_HYS_ENABLE);
|
||||
break;
|
||||
default:
|
||||
printf("Warning: you configured more ESDHC controller"
|
||||
"(%d) as supported by the board(2)\n",
|
||||
CONFIG_SYS_FSL_ESDHC_NUM);
|
||||
return status;
|
||||
}
|
||||
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
system_rev = get_cpu_rev();
|
||||
|
||||
gd->bd->bi_arch_number = MACH_TYPE_MX51_BABBAGE;
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
setup_iomux_uart();
|
||||
setup_expio();
|
||||
setup_iomux_fec();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX51EVK ");
|
||||
|
||||
switch (system_rev & 0xff) {
|
||||
case CHIP_REV_3_0:
|
||||
puts("3.0 [");
|
||||
break;
|
||||
case CHIP_REV_2_5:
|
||||
puts("2.5 [");
|
||||
break;
|
||||
case CHIP_REV_2_0:
|
||||
puts("2.0 [");
|
||||
break;
|
||||
case CHIP_REV_1_1:
|
||||
puts("1.1 [");
|
||||
break;
|
||||
case CHIP_REV_1_0:
|
||||
default:
|
||||
puts("1.0 [");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (__raw_readl(SRC_BASE_ADDR + 0x8)) {
|
||||
case 0x0001:
|
||||
puts("POR");
|
||||
break;
|
||||
case 0x0009:
|
||||
puts("RST");
|
||||
break;
|
||||
case 0x0010:
|
||||
case 0x0011:
|
||||
puts("WDOG");
|
||||
break;
|
||||
default:
|
||||
puts("unknown");
|
||||
}
|
||||
puts("]\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
51
board/freescale/mx51evk/mx51evk.h
Normal file
51
board/freescale/mx51evk/mx51evk.h
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_FREESCALE_MX51_EVK_H__
|
||||
#define __BOARD_FREESCALE_MX51_EVK_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct io_board_ctrl {
|
||||
u16 led_ctrl; /* 0x00 */
|
||||
u16 resv1[0x03];
|
||||
u16 sb_stat; /* 0x08 */
|
||||
u16 resv2[0x03];
|
||||
u16 int_stat; /* 0x10 */
|
||||
u16 resv3[0x07];
|
||||
u16 int_rest; /* 0x20 */
|
||||
u16 resv4[0x0B];
|
||||
u16 int_mask; /* 0x38 */
|
||||
u16 resv5[0x03];
|
||||
u16 id1; /* 0x40 */
|
||||
u16 resv6[0x03];
|
||||
u16 id2; /* 0x48 */
|
||||
u16 resv7[0x03];
|
||||
u16 version; /* 0x50 */
|
||||
u16 resv8[0x03];
|
||||
u16 id3; /* 0x58 */
|
||||
u16 resv9[0x03];
|
||||
u16 sw_reset; /* 0x60 */
|
||||
};
|
||||
#endif
|
||||
|
||||
#define IO_BOARD_OFFSET (0x20000)
|
||||
#endif
|
||||
172
include/configs/mx51evk.h
Normal file
172
include/configs/mx51evk.h
Normal file
@ -0,0 +1,172 @@
|
||||
/*
|
||||
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
*
|
||||
* (C) Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the MX51EVK Board
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
#define CONFIG_MX51 /* in a mx51 */
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */
|
||||
#define CONFIG_MX51_CLK32 32768
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
|
||||
#define CONFIG_L2_OFF
|
||||
|
||||
/*
|
||||
* Disabled for now due to build problems under Debian and a significant
|
||||
* increase in the final file size: 144260 vs. 109536 Bytes.
|
||||
*/
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_REVISION_TAG 1
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_SYS_MX51_UART1
|
||||
|
||||
/*
|
||||
* MMC Configs
|
||||
* */
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 2
|
||||
|
||||
#define CONFIG_MMC
|
||||
|
||||
#define CONFIG_CMD_MMC
|
||||
#define CONFIG_GENERIC_MMC
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/*
|
||||
* Eth Configs
|
||||
*/
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_DISCOVER_PHY
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE FEC_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1F
|
||||
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
/***********************************************************
|
||||
* Command definition
|
||||
***********************************************************/
|
||||
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#define CONFIG_PRIME "FEC0"
|
||||
|
||||
#define CONFIG_LOADADDR 0x90800000 /* loadaddr env var */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot_addr=0xa0000000\0" \
|
||||
"uboot=u-boot.bin\0" \
|
||||
"loadaddr=0x90800000\0" \
|
||||
"bootargs_base=setenv bootargs console=tty "\
|
||||
"console=ttymxc0,${baudrate}\0"\
|
||||
"bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\
|
||||
"bootcmd=run bootcmd_net\0" \
|
||||
"bootcmd_net=run bootargs_base bootargs_nfs; " \
|
||||
"tftpboot ${loadaddr} ${kernel}; bootm\0"
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "MX51EVK U-Boot > "
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x90000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x10000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
#define CONFIG_ENV_IS_NOWHERE
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user