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ARM: dts: rk3288: Remove unused LCDC clock assigned

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The LCDC assigned rate is 0, it will make boot error,
error log:"pll_para_config: the frequency can not be
 0 Hz". Remove them, and the lcdc driver will do the
correct clock rate setting.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
David Wu 2018-01-13 14:06:16 +08:00 committed by Philipp Tomsich
parent a50e5c9e33
commit c513e9e1e6
1 changed files with 2 additions and 5 deletions
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7
arch/arm/dts/rk3288.dtsi
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@ -604,19 +604,16 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru PLL_NPLL>, <&cru ACLK_CPU>,
<&cru HCLK_CPU>, <&cru PCLK_CPU>,
<&cru ACLK_PERI>, <&cru HCLK_PERI>,
<&cru PCLK_PERI>;
assigned-clock-rates = <0>, <0>,
<594000000>, <400000000>,
assigned-clock-rates = <594000000>, <400000000>,
<500000000>, <300000000>,
<150000000>, <75000000>,
<300000000>, <150000000>,
<75000000>;
assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
};
grf: syscon@ff770000 {