Revert "riscv: Clear pending interrupts before enabling IPIs"
Clearing MIP.MSIP is not guaranteed to do anything by the spec. In
addition, most existing RISC-V hardware does nothing when this bit is set.
The following commits "riscv: Use a valid bit to ignore already-pending
IPIs" and "riscv: Clear pending IPIs on initialization" should implement
the original intent of the reverted commit in a more robust manner.
This reverts commit 9472630337
.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
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@ -65,8 +65,6 @@ _start:
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#else
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li t0, SIE_SSIE
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#endif
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/* Clear any pending IPIs */
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csrc MODE_PREFIX(ip), t0
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csrs MODE_PREFIX(ie), t0
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#endif
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