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tegra2: Rename PIN_ to PINGRP_

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The pin groupings are better named PINGRP, since on Tegra2 they refer to
multiple pins.

Sorry about this, but better to get it right now when there is only a small
amount of code affected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass 2011-09-21 12:40:05 +00:00 committed by Albert ARIBAUD
parent 4ed59e70e4
commit c3cf49d247
3 changed files with 138 additions and 138 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/cpu/armv7/tegra2/pinmux.c
View File

@ -27,7 +27,7 @@
#include <common.h> #include <common.h>
void pinmux_set_tristate(enum pmux_pin pin, int enable) void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
{ {
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE; struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)]; u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
@ -41,12 +41,12 @@ void pinmux_set_tristate(enum pmux_pin pin, int enable)
writel(reg, tri); writel(reg, tri);
} }
void pinmux_tristate_enable(enum pmux_pin pin) void pinmux_tristate_enable(enum pmux_pingrp pin)
{ {
pinmux_set_tristate(pin, 1); pinmux_set_tristate(pin, 1);
} }
void pinmux_tristate_disable(enum pmux_pin pin) void pinmux_tristate_disable(enum pmux_pingrp pin)
{ {
pinmux_set_tristate(pin, 0); pinmux_set_tristate(pin, 0);
} }

252
arch/arm/include/asm/arch-tegra2/pinmux.h
View File

@ -24,137 +24,137 @@
#ifndef _PINMUX_H_ #ifndef _PINMUX_H_
#define _PINMUX_H_ #define _PINMUX_H_
/* Pins which we can set to tristate or normal */ /* Pin groups which we can set to tristate or normal */
enum pmux_pin { enum pmux_pingrp {
/* APB_MISC_PP_TRISTATE_REG_A_0 */ /* APB_MISC_PP_TRISTATE_REG_A_0 */
PIN_ATA, PINGRP_ATA,
PIN_ATB, PINGRP_ATB,
PIN_ATC, PINGRP_ATC,
PIN_ATD, PINGRP_ATD,
PIN_CDEV1, PINGRP_CDEV1,
PIN_CDEV2, PINGRP_CDEV2,
PIN_CSUS, PINGRP_CSUS,
PIN_DAP1, PINGRP_DAP1,
PIN_DAP2, PINGRP_DAP2,
PIN_DAP3, PINGRP_DAP3,
PIN_DAP4, PINGRP_DAP4,
PIN_DTA, PINGRP_DTA,
PIN_DTB, PINGRP_DTB,
PIN_DTC, PINGRP_DTC,
PIN_DTD, PINGRP_DTD,
PIN_DTE, PINGRP_DTE,
PIN_GPU, PINGRP_GPU,
PIN_GPV, PINGRP_GPV,
PIN_I2CP, PINGRP_I2CP,
PIN_IRTX, PINGRP_IRTX,
PIN_IRRX, PINGRP_IRRX,
PIN_KBCB, PINGRP_KBCB,
PIN_KBCA, PINGRP_KBCA,
PIN_PMC, PINGRP_PMC,
PIN_PTA, PINGRP_PTA,
PIN_RM, PINGRP_RM,
PIN_KBCE, PINGRP_KBCE,
PIN_KBCF, PINGRP_KBCF,
PIN_GMA, PINGRP_GMA,
PIN_GMC, PINGRP_GMC,
PIN_SDMMC1, PINGRP_SDMMC1,
PIN_OWC, PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */ /* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
PIN_GME, PINGRP_GME,
PIN_SDC, PINGRP_SDC,
PIN_SDD, PINGRP_SDD,
PIN_RESERVED0, PINGRP_RESERVED0,
PIN_SLXA, PINGRP_SLXA,
PIN_SLXC, PINGRP_SLXC,
PIN_SLXD, PINGRP_SLXD,
PIN_SLXK, PINGRP_SLXK,
PIN_SPDI, PINGRP_SPDI,
PIN_SPDO, PINGRP_SPDO,
PIN_SPIA, PINGRP_SPIA,
PIN_SPIB, PINGRP_SPIB,
PIN_SPIC, PINGRP_SPIC,
PIN_SPID, PINGRP_SPID,
PIN_SPIE, PINGRP_SPIE,
PIN_SPIF, PINGRP_SPIF,
PIN_SPIG, PINGRP_SPIG,
PIN_SPIH, PINGRP_SPIH,
PIN_UAA, PINGRP_UAA,
PIN_UAB, PINGRP_UAB,
PIN_UAC, PINGRP_UAC,
PIN_UAD, PINGRP_UAD,
PIN_UCA, PINGRP_UCA,
PIN_UCB, PINGRP_UCB,
PIN_RESERVED1, PINGRP_RESERVED1,
PIN_ATE, PINGRP_ATE,
PIN_KBCC, PINGRP_KBCC,
PIN_RESERVED2, PINGRP_RESERVED2,
PIN_RESERVED3, PINGRP_RESERVED3,
PIN_GMB, PINGRP_GMB,
PIN_GMD, PINGRP_GMD,
PIN_DDC, PINGRP_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */ /* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
PIN_LD0, PINGRP_LD0,
PIN_LD1, PINGRP_LD1,
PIN_LD2, PINGRP_LD2,
PIN_LD3, PINGRP_LD3,
PIN_LD4, PINGRP_LD4,
PIN_LD5, PINGRP_LD5,
PIN_LD6, PINGRP_LD6,
PIN_LD7, PINGRP_LD7,
PIN_LD8, PINGRP_LD8,
PIN_LD9, PINGRP_LD9,
PIN_LD10, PINGRP_LD10,
PIN_LD11, PINGRP_LD11,
PIN_LD12, PINGRP_LD12,
PIN_LD13, PINGRP_LD13,
PIN_LD14, PINGRP_LD14,
PIN_LD15, PINGRP_LD15,
PIN_LD16, PINGRP_LD16,
PIN_LD17, PINGRP_LD17,
PIN_LHP0, PINGRP_LHP0,
PIN_LHP1, PINGRP_LHP1,
PIN_LHP2, PINGRP_LHP2,
PIN_LVP0, PINGRP_LVP0,
PIN_LVP1, PINGRP_LVP1,
PIN_HDINT, PINGRP_HDINT,
PIN_LM0, PINGRP_LM0,
PIN_LM1, PINGRP_LM1,
PIN_LVS, PINGRP_LVS,
PIN_LSC0, PINGRP_LSC0,
PIN_LSC1, PINGRP_LSC1,
PIN_LSCK, PINGRP_LSCK,
PIN_LDC, PINGRP_LDC,
PIN_LCSN, PINGRP_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */ /* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
PIN_LSPI, PINGRP_LSPI,
PIN_LSDA, PINGRP_LSDA,
PIN_LSDI, PINGRP_LSDI,
PIN_LPW0, PINGRP_LPW0,
PIN_LPW1, PINGRP_LPW1,
PIN_LPW2, PINGRP_LPW2,
PIN_LDI, PINGRP_LDI,
PIN_LHS, PINGRP_LHS,
PIN_LPP, PINGRP_LPP,
PIN_RESERVED4, PINGRP_RESERVED4,
PIN_KBCD, PINGRP_KBCD,
PIN_GPU7, PINGRP_GPU7,
PIN_DTF, PINGRP_DTF,
PIN_UDA, PINGRP_UDA,
PIN_CRTP, PINGRP_CRTP,
PIN_SDB, PINGRP_SDB,
}; };
@ -172,25 +172,25 @@ struct pmux_tri_ctlr {
uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */ uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
uint pmt_ctl_a; /* _PIN_MUX_CTL_A_0, offset 80 */ uint pmt_ctl_a; /* _PINGRP_MUX_CTL_A_0, offset 80 */
uint pmt_ctl_b; /* _PIN_MUX_CTL_B_0, offset 84 */ uint pmt_ctl_b; /* _PINGRP_MUX_CTL_B_0, offset 84 */
uint pmt_ctl_c; /* _PIN_MUX_CTL_C_0, offset 88 */ uint pmt_ctl_c; /* _PINGRP_MUX_CTL_C_0, offset 88 */
uint pmt_ctl_d; /* _PIN_MUX_CTL_D_0, offset 8C */ uint pmt_ctl_d; /* _PINGRP_MUX_CTL_D_0, offset 8C */
uint pmt_ctl_e; /* _PIN_MUX_CTL_E_0, offset 90 */ uint pmt_ctl_e; /* _PINGRP_MUX_CTL_E_0, offset 90 */
uint pmt_ctl_f; /* _PIN_MUX_CTL_F_0, offset 94 */ uint pmt_ctl_f; /* _PINGRP_MUX_CTL_F_0, offset 94 */
uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */ uint pmt_ctl_g; /* _PINGRP_MUX_CTL_G_0, offset 98 */
}; };
/* Converts a pin number to a tristate register: 0=A, 1=B, 2=C, 3=D */ /* Converts a pin group to a tristate register: 0=A, 1=B, 2=C, 3=D */
#define TRISTATE_REG(id) ((id) >> 5) #define TRISTATE_REG(id) ((id) >> 5)
/* Mask value for a tristate (within TRISTATE_REG(id)) */ /* Mask value for a tristate (within TRISTATE_REG(id)) */
#define TRISTATE_MASK(id) (1 << ((id) & 0x1f)) #define TRISTATE_MASK(id) (1 << ((id) & 0x1f))
/* Set a pin to tristate */ /* Set a pin group to tristate */
void pinmux_tristate_enable(enum pmux_pin pin); void pinmux_tristate_enable(enum pmux_pingrp pin);
/* Set a pin to normal (non tristate) */ /* Set a pin group to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pin pin); void pinmux_tristate_disable(enum pmux_pingrp pin);
#endif /* PINMUX_H */ #endif /* PINMUX_H */

18
board/nvidia/common/board.c
View File

@ -94,15 +94,15 @@ static void pin_mux_uart(void)
reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */ reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
writel(reg, &pmt->pmt_ctl_c); writel(reg, &pmt->pmt_ctl_c);
pinmux_tristate_disable(PIN_IRRX); pinmux_tristate_disable(PINGRP_IRRX);
pinmux_tristate_disable(PIN_IRTX); pinmux_tristate_disable(PINGRP_IRTX);
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #endif /* CONFIG_TEGRA2_ENABLE_UARTA */
#if defined(CONFIG_TEGRA2_ENABLE_UARTD) #if defined(CONFIG_TEGRA2_ENABLE_UARTD)
reg = readl(&pmt->pmt_ctl_b); reg = readl(&pmt->pmt_ctl_b);
reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */ reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
writel(reg, &pmt->pmt_ctl_b); writel(reg, &pmt->pmt_ctl_b);
pinmux_tristate_disable(PIN_GMC); pinmux_tristate_disable(PINGRP_GMC);
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */ #endif /* CONFIG_TEGRA2_ENABLE_UARTD */
} }
@ -138,9 +138,9 @@ static void pin_mux_mmc(void)
reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */ reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
writel(reg, &pmt->pmt_ctl_d); writel(reg, &pmt->pmt_ctl_d);
pinmux_tristate_disable(PIN_ATB); pinmux_tristate_disable(PINGRP_ATB);
pinmux_tristate_disable(PIN_GMA); pinmux_tristate_disable(PINGRP_GMA);
pinmux_tristate_disable(PIN_GME); pinmux_tristate_disable(PINGRP_GME);
/* SDMMC3 */ /* SDMMC3 */
/* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
@ -151,9 +151,9 @@ static void pin_mux_mmc(void)
reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */ reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
writel(reg, &pmt->pmt_ctl_d); writel(reg, &pmt->pmt_ctl_d);
pinmux_tristate_disable(PIN_SDC); pinmux_tristate_disable(PINGRP_SDC);
pinmux_tristate_disable(PIN_SDD); pinmux_tristate_disable(PINGRP_SDD);
pinmux_tristate_disable(PIN_SDB); pinmux_tristate_disable(PINGRP_SDB);
} }
#endif #endif