tegra2: Rename PIN_ to PINGRP_
The pin groupings are better named PINGRP, since on Tegra2 they refer to multiple pins. Sorry about this, but better to get it right now when there is only a small amount of code affected. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass
Albert ARIBAUD
parent
4ed59e70e4
commit
c3cf49d247
@ -27,7 +27,7 @@
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#include <common.h>
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void pinmux_set_tristate(enum pmux_pin pin, int enable)
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void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
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{
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struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
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u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
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@ -41,12 +41,12 @@ void pinmux_set_tristate(enum pmux_pin pin, int enable)
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writel(reg, tri);
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}
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void pinmux_tristate_enable(enum pmux_pin pin)
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void pinmux_tristate_enable(enum pmux_pingrp pin)
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{
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pinmux_set_tristate(pin, 1);
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}
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void pinmux_tristate_disable(enum pmux_pin pin)
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void pinmux_tristate_disable(enum pmux_pingrp pin)
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{
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pinmux_set_tristate(pin, 0);
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}
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@ -24,137 +24,137 @@
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#ifndef _PINMUX_H_
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#define _PINMUX_H_
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/* Pins which we can set to tristate or normal */
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enum pmux_pin {
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/* Pin groups which we can set to tristate or normal */
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enum pmux_pingrp {
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/* APB_MISC_PP_TRISTATE_REG_A_0 */
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PIN_ATA,
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PIN_ATB,
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PIN_ATC,
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PIN_ATD,
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PIN_CDEV1,
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PIN_CDEV2,
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PIN_CSUS,
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PIN_DAP1,
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PINGRP_ATA,
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PINGRP_ATB,
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PINGRP_ATC,
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PINGRP_ATD,
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PINGRP_CDEV1,
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PINGRP_CDEV2,
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PINGRP_CSUS,
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PINGRP_DAP1,
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PIN_DAP2,
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PIN_DAP3,
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PIN_DAP4,
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PIN_DTA,
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PIN_DTB,
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PIN_DTC,
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PIN_DTD,
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PIN_DTE,
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PINGRP_DAP2,
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PINGRP_DAP3,
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PINGRP_DAP4,
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PINGRP_DTA,
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PINGRP_DTB,
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PINGRP_DTC,
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PINGRP_DTD,
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PINGRP_DTE,
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PIN_GPU,
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PIN_GPV,
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PIN_I2CP,
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PIN_IRTX,
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PIN_IRRX,
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PIN_KBCB,
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PIN_KBCA,
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PIN_PMC,
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PINGRP_GPU,
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PINGRP_GPV,
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PINGRP_I2CP,
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PINGRP_IRTX,
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PINGRP_IRRX,
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PINGRP_KBCB,
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PINGRP_KBCA,
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PINGRP_PMC,
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PIN_PTA,
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PIN_RM,
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PIN_KBCE,
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PIN_KBCF,
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PIN_GMA,
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PIN_GMC,
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PIN_SDMMC1,
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PIN_OWC,
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PINGRP_PTA,
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PINGRP_RM,
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PINGRP_KBCE,
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PINGRP_KBCF,
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PINGRP_GMA,
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PINGRP_GMC,
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PINGRP_SDMMC1,
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PINGRP_OWC,
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/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
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PIN_GME,
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PIN_SDC,
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PIN_SDD,
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PIN_RESERVED0,
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PIN_SLXA,
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PIN_SLXC,
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PIN_SLXD,
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PIN_SLXK,
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PINGRP_GME,
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PINGRP_SDC,
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PINGRP_SDD,
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PINGRP_RESERVED0,
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PINGRP_SLXA,
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PINGRP_SLXC,
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PINGRP_SLXD,
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PINGRP_SLXK,
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PIN_SPDI,
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PIN_SPDO,
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PIN_SPIA,
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PIN_SPIB,
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PIN_SPIC,
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PIN_SPID,
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PIN_SPIE,
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PIN_SPIF,
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PINGRP_SPDI,
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PINGRP_SPDO,
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PINGRP_SPIA,
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PINGRP_SPIB,
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PINGRP_SPIC,
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PINGRP_SPID,
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PINGRP_SPIE,
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PINGRP_SPIF,
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PIN_SPIG,
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PIN_SPIH,
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PIN_UAA,
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PIN_UAB,
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PIN_UAC,
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PIN_UAD,
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PIN_UCA,
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PIN_UCB,
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PINGRP_SPIG,
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PINGRP_SPIH,
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PINGRP_UAA,
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PINGRP_UAB,
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PINGRP_UAC,
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PINGRP_UAD,
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PINGRP_UCA,
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PINGRP_UCB,
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PIN_RESERVED1,
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PIN_ATE,
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PIN_KBCC,
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PIN_RESERVED2,
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PIN_RESERVED3,
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PIN_GMB,
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PIN_GMD,
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PIN_DDC,
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PINGRP_RESERVED1,
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PINGRP_ATE,
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PINGRP_KBCC,
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PINGRP_RESERVED2,
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PINGRP_RESERVED3,
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PINGRP_GMB,
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PINGRP_GMD,
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PINGRP_DDC,
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/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
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PIN_LD0,
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PIN_LD1,
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PIN_LD2,
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PIN_LD3,
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PIN_LD4,
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PIN_LD5,
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PIN_LD6,
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PIN_LD7,
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PINGRP_LD0,
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PINGRP_LD1,
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PINGRP_LD2,
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PINGRP_LD3,
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PINGRP_LD4,
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PINGRP_LD5,
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PINGRP_LD6,
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PINGRP_LD7,
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PIN_LD8,
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PIN_LD9,
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PIN_LD10,
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PIN_LD11,
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PIN_LD12,
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PIN_LD13,
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PIN_LD14,
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PIN_LD15,
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PINGRP_LD8,
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PINGRP_LD9,
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PINGRP_LD10,
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PINGRP_LD11,
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PINGRP_LD12,
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PINGRP_LD13,
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PINGRP_LD14,
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PINGRP_LD15,
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PIN_LD16,
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PIN_LD17,
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PIN_LHP0,
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PIN_LHP1,
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PIN_LHP2,
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PIN_LVP0,
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PIN_LVP1,
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PIN_HDINT,
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PINGRP_LD16,
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PINGRP_LD17,
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PINGRP_LHP0,
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PINGRP_LHP1,
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PINGRP_LHP2,
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PINGRP_LVP0,
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PINGRP_LVP1,
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PINGRP_HDINT,
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PIN_LM0,
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PIN_LM1,
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PIN_LVS,
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PIN_LSC0,
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PIN_LSC1,
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PIN_LSCK,
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PIN_LDC,
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PIN_LCSN,
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PINGRP_LM0,
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PINGRP_LM1,
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PINGRP_LVS,
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PINGRP_LSC0,
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PINGRP_LSC1,
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PINGRP_LSCK,
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PINGRP_LDC,
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PINGRP_LCSN,
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/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
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PIN_LSPI,
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PIN_LSDA,
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PIN_LSDI,
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PIN_LPW0,
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PIN_LPW1,
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PIN_LPW2,
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PIN_LDI,
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PIN_LHS,
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PINGRP_LSPI,
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PINGRP_LSDA,
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PINGRP_LSDI,
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PINGRP_LPW0,
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PINGRP_LPW1,
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PINGRP_LPW2,
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PINGRP_LDI,
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PINGRP_LHS,
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PIN_LPP,
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PIN_RESERVED4,
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PIN_KBCD,
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PIN_GPU7,
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PIN_DTF,
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PIN_UDA,
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PIN_CRTP,
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PIN_SDB,
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PINGRP_LPP,
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PINGRP_RESERVED4,
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PINGRP_KBCD,
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PINGRP_GPU7,
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PINGRP_DTF,
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PINGRP_UDA,
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PINGRP_CRTP,
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PINGRP_SDB,
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};
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@ -172,25 +172,25 @@ struct pmux_tri_ctlr {
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uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
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uint pmt_ctl_a; /* _PIN_MUX_CTL_A_0, offset 80 */
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uint pmt_ctl_b; /* _PIN_MUX_CTL_B_0, offset 84 */
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uint pmt_ctl_c; /* _PIN_MUX_CTL_C_0, offset 88 */
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uint pmt_ctl_d; /* _PIN_MUX_CTL_D_0, offset 8C */
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uint pmt_ctl_e; /* _PIN_MUX_CTL_E_0, offset 90 */
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uint pmt_ctl_f; /* _PIN_MUX_CTL_F_0, offset 94 */
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uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */
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uint pmt_ctl_a; /* _PINGRP_MUX_CTL_A_0, offset 80 */
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uint pmt_ctl_b; /* _PINGRP_MUX_CTL_B_0, offset 84 */
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uint pmt_ctl_c; /* _PINGRP_MUX_CTL_C_0, offset 88 */
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uint pmt_ctl_d; /* _PINGRP_MUX_CTL_D_0, offset 8C */
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uint pmt_ctl_e; /* _PINGRP_MUX_CTL_E_0, offset 90 */
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uint pmt_ctl_f; /* _PINGRP_MUX_CTL_F_0, offset 94 */
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uint pmt_ctl_g; /* _PINGRP_MUX_CTL_G_0, offset 98 */
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};
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/* Converts a pin number to a tristate register: 0=A, 1=B, 2=C, 3=D */
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/* Converts a pin group to a tristate register: 0=A, 1=B, 2=C, 3=D */
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#define TRISTATE_REG(id) ((id) >> 5)
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/* Mask value for a tristate (within TRISTATE_REG(id)) */
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#define TRISTATE_MASK(id) (1 << ((id) & 0x1f))
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/* Set a pin to tristate */
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void pinmux_tristate_enable(enum pmux_pin pin);
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/* Set a pin group to tristate */
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void pinmux_tristate_enable(enum pmux_pingrp pin);
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/* Set a pin to normal (non tristate) */
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void pinmux_tristate_disable(enum pmux_pin pin);
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/* Set a pin group to normal (non tristate) */
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void pinmux_tristate_disable(enum pmux_pingrp pin);
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#endif /* PINMUX_H */
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@ -94,15 +94,15 @@ static void pin_mux_uart(void)
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reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
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writel(reg, &pmt->pmt_ctl_c);
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pinmux_tristate_disable(PIN_IRRX);
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pinmux_tristate_disable(PIN_IRTX);
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pinmux_tristate_disable(PINGRP_IRRX);
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pinmux_tristate_disable(PINGRP_IRTX);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
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#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
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reg = readl(&pmt->pmt_ctl_b);
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reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */
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writel(reg, &pmt->pmt_ctl_b);
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pinmux_tristate_disable(PIN_GMC);
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pinmux_tristate_disable(PINGRP_GMC);
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#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
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}
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@ -138,9 +138,9 @@ static void pin_mux_mmc(void)
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reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */
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writel(reg, &pmt->pmt_ctl_d);
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pinmux_tristate_disable(PIN_ATB);
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pinmux_tristate_disable(PIN_GMA);
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pinmux_tristate_disable(PIN_GME);
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pinmux_tristate_disable(PINGRP_ATB);
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pinmux_tristate_disable(PINGRP_GMA);
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pinmux_tristate_disable(PINGRP_GME);
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/* SDMMC3 */
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/* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */
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@ -151,9 +151,9 @@ static void pin_mux_mmc(void)
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reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */
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writel(reg, &pmt->pmt_ctl_d);
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pinmux_tristate_disable(PIN_SDC);
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pinmux_tristate_disable(PIN_SDD);
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pinmux_tristate_disable(PIN_SDB);
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pinmux_tristate_disable(PINGRP_SDC);
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pinmux_tristate_disable(PINGRP_SDD);
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pinmux_tristate_disable(PINGRP_SDB);
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}
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#endif
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