mmc: dwmmc: socfpga: Convert to DM
Convert the SoCFPGA shim for registering the DWMMC driver to DM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
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@ -5,24 +5,29 @@
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*/
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#include <common.h>
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#include <malloc.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/system_manager.h>
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#include <dm.h>
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#include <dwmmc.h>
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#include <errno.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/system_manager.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <linux/err.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_clock_manager *clock_manager_base =
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(void *)SOCFPGA_CLKMGR_ADDRESS;
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static const struct socfpga_system_manager *system_manager_base =
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(void *)SOCFPGA_SYSMGR_ADDRESS;
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/* socfpga implmentation specific drver private data */
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/* socfpga implmentation specific driver private data */
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struct dwmci_socfpga_priv_data {
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unsigned int drvsel;
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unsigned int smplsel;
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struct dwmci_host host;
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unsigned int drvsel;
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unsigned int smplsel;
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};
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static void socfpga_dwmci_clksel(struct dwmci_host *host)
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@ -46,98 +51,77 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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}
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static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
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static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
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{
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/* FIXME: probe from DT eventually too/ */
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const unsigned long clk = cm_get_mmc_controller_clk_hz();
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struct dwmci_host *host;
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struct dwmci_socfpga_priv_data *priv;
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fdt_addr_t reg_base;
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int bus_width, fifo_depth;
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struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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int fifo_depth;
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if (clk == 0) {
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printf("DWMMC%d: MMC clock is zero!", idx);
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printf("DWMMC: MMC clock is zero!");
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return -EINVAL;
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}
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/* Get the register address from the device node */
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reg_base = fdtdec_get_addr(blob, node, "reg");
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if (!reg_base) {
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printf("DWMMC%d: Can't get base address\n", idx);
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return -EINVAL;
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}
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/* Get the bus width from the device node */
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bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
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if (bus_width <= 0) {
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printf("DWMMC%d: Can't get bus-width\n", idx);
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return -EINVAL;
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}
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fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
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fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"fifo-depth", 0);
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if (fifo_depth < 0) {
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printf("DWMMC%d: Can't get FIFO depth\n", idx);
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printf("DWMMC: Can't get FIFO depth\n");
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return -EINVAL;
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}
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/* Allocate the host */
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host = calloc(1, sizeof(*host));
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if (!host)
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return -ENOMEM;
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/* Allocate the priv */
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priv = calloc(1, sizeof(*priv));
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if (!priv) {
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free(host);
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return -ENOMEM;
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}
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host->name = "SOCFPGA DWMMC";
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host->ioaddr = (void *)reg_base;
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host->buswidth = bus_width;
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host->name = dev->name;
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host->ioaddr = (void *)dev_get_addr(dev);
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host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
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"bus-width", 4);
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host->clksel = socfpga_dwmci_clksel;
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host->dev_index = idx;
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/*
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* TODO(sjg@chromium.org): Remove the need for this hack.
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* We only have one dwmmc block on gen5 SoCFPGA.
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*/
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host->dev_index = 0;
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/* Fixed clock divide by 4 which due to the SDMMC wrapper */
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host->bus_hz = clk;
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host->fifoth_val = MSIZE(0x2) |
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RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
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priv->drvsel = fdtdec_get_uint(blob, node, "drvsel", 3);
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priv->smplsel = fdtdec_get_uint(blob, node, "smplsel", 0);
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priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
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"drvsel", 3);
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priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev->of_offset,
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"smplsel", 0);
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host->priv = priv;
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return add_dwmci(host, host->bus_hz, 400000);
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}
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static int socfpga_dwmci_process_node(const void *blob, int nodes[],
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int count)
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{
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int i, node, ret;
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for (i = 0; i < count; i++) {
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node = nodes[i];
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if (node <= 0)
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continue;
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ret = socfpga_dwmci_of_probe(blob, node, i);
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if (ret) {
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printf("%s: failed to decode dev %d\n", __func__, i);
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return ret;
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}
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}
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return 0;
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}
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int socfpga_dwmmc_init(const void *blob)
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static int socfpga_dwmmc_probe(struct udevice *dev)
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{
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int nodes[2]; /* Max. two controllers. */
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int ret, count;
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
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struct dwmci_host *host = &priv->host;
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int ret;
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count = fdtdec_find_aliases_for_id(blob, "mmc",
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COMPAT_ALTERA_SOCFPGA_DWMMC,
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nodes, ARRAY_SIZE(nodes));
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ret = add_dwmci(host, host->bus_hz, 400000);
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if (ret)
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return ret;
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ret = socfpga_dwmci_process_node(blob, nodes, count);
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upriv->mmc = host->mmc;
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return ret;
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return 0;
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}
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static const struct udevice_id socfpga_dwmmc_ids[] = {
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{ .compatible = "altr,socfpga-dw-mshc" },
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{ }
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};
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U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
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.name = "socfpga_dwmmc",
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.id = UCLASS_MMC,
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.of_match = socfpga_dwmmc_ids,
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.ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
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.probe = socfpga_dwmmc_probe,
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.priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
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};
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