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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-12-06 14:26:51 +01:00
commit c35cf8dc9f
53 changed files with 1745 additions and 261 deletions
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7
arch/arm/cpu/armv7/am33xx/ddr.c
View File

@ -89,15 +89,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr)
void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
{
writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
}
@ -121,10 +118,6 @@ void config_ddr_data(const struct ddr_data *data, int nr)
&(ddr_data_reg[nr]+i)->dt0fwsratio0);
writel(data->datawrsratio0,
&(ddr_data_reg[nr]+i)->dt0wrsratio0);
writel(data->datauserank0delay,
&(ddr_data_reg[nr]+i)->dt0rdelays0);
writel(data->datadldiff0,
&(ddr_data_reg[nr]+i)->dt0dldiff0);
}
}

5
arch/arm/cpu/armv7/omap-common/Makefile
View File

@ -17,6 +17,11 @@ obj-y += vc.o
obj-y += abb.o
endif
ifneq ($(CONFIG_OMAP54XX),)
COBJS += pipe3-phy.o
obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
obj-y += lowlevel_init.o

142
arch/arm/cpu/armv7/omap-common/emif-common.c
View File

@ -206,7 +206,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs)
}
}
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
@ -217,47 +217,86 @@ static void ddr3_leveling(u32 base, const struct emif_regs *regs)
/*
* Set invert_clkout (if activated)--DDR_PHYCTRL_1
* Invert clock adds an additional half cycle delay on the command
* interface. The additional half cycle, is usually meant to enable
* leveling in the situation that DQS is later than CK on the board.It
* also helps provide some additional margin for leveling.
* Invert clock adds an additional half cycle delay on the
* command interface. The additional half cycle, is usually
* meant to enable leveling in the situation that DQS is later
* than CK on the board.It also helps provide some additional
* margin for leveling.
*/
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
writel(regs->emif_ddr_phy_ctlr_1,
&emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1,
&emif->emif_ddr_phy_ctrl_1_shdw);
__udelay(130);
writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
__udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
/* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
/*
* Launch 8 incremental WR_LVL- to compensate for
* PHY limitation.
*/
writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Launch Incremental leveling */
writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
__udelay(130);
__udelay(130);
}
static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
u32 fifo_reg;
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_1);
fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
writel(fifo_reg | 0x00000100,
&emif->emif_ddr_fifo_misaligned_clear_2);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
__udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
writel(regs->sdram_config, &emif->emif_sdram_config);
/*
* Disable leveling. This is because if leveling is kept
* enabled, then PHY triggers a false leveling during
* EMIF-idle scenario which results in wrong delay
* values getting updated. After this the EMIF becomes
* unaccessible. So disable it after the first time
*/
writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
}
static void ddr3_leveling(u32 base, const struct emif_regs *regs)
{
if (is_omap54xx())
omap5_ddr3_leveling(base, regs);
else
dra7_ddr3_leveling(base, regs);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
@ -270,9 +309,6 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
/* Update timing registers */
@ -283,15 +319,24 @@ static void ddr3_init(u32 base, const struct emif_regs *regs)
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
do_ext_phy_settings(base, regs);
/*
* The same sequence should work on OMAP5432 as well. But strange that
* it is not working
*/
if (omap_revision() == DRA752_ES1_0) {
do_ext_phy_settings(base, regs);
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
} else {
writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
writel(regs->sdram_config_init, &emif->emif_sdram_config);
do_ext_phy_settings(base, regs);
}
/* enable leveling */
writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
if (omap_revision() == DRA752_ES1_0)
ddr3_sw_leveling(base, regs);
else
ddr3_leveling(base, regs);
ddr3_leveling(base, regs);
}
#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@ -1079,10 +1124,7 @@ static void do_sdram_init(u32 base)
if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
set_lpmode_selfrefresh(base);
emif_reset_phy(base);
if (omap_revision() == DRA752_ES1_0)
ddr3_sw_leveling(base, regs);
else
ddr3_leveling(base, regs);
ddr3_leveling(base, regs);
}
/* Write to the shadow registers */
@ -1244,6 +1286,42 @@ void dmm_init(u32 base)
}
static void do_bug0039_workaround(u32 base)
{
u32 val, i, clkctrl;
struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
const struct read_write_regs *bug_00339_regs;
u32 iterations;
u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
if (is_dra7xx())
phy_status_base++;
bug_00339_regs = get_bug_regs(&iterations);
/* Put EMIF in to idle */
clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
__raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
/* Copy the phy status registers in to phy ctrl shadow registers */
for (i = 0; i < iterations; i++) {
val = __raw_readl(phy_status_base +
bug_00339_regs[i].read_reg - 1);
__raw_writel(val, phy_ctrl_base +
((bug_00339_regs[i].write_reg - 1) << 1));
__raw_writel(val, phy_ctrl_base +
(bug_00339_regs[i].write_reg << 1) - 1);
}
/* Disable leveling */
writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
__raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
}
/*
* SDRAM initialization:
* SDRAM initialization has two parts:
@ -1319,5 +1397,11 @@ void sdram_init(void)
debug("get_ram_size() successful");
}
if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
(!in_sdram && !warm_reset())) {
do_bug0039_workaround(EMIF1_BASE);
do_bug0039_workaround(EMIF2_BASE);
}
debug("<<sdram_init()\n");
}

231
arch/arm/cpu/armv7/omap-common/pipe3-phy.c Normal file
View File

@ -0,0 +1,231 @@
/*
* TI PIPE3 PHY
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <sata.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <asm/errno.h>
#include "pipe3-phy.h"
/* PLLCTRL Registers */
#define PLL_STATUS 0x00000004
#define PLL_GO 0x00000008
#define PLL_CONFIGURATION1 0x0000000C
#define PLL_CONFIGURATION2 0x00000010
#define PLL_CONFIGURATION3 0x00000014
#define PLL_CONFIGURATION4 0x00000020
#define PLL_REGM_MASK 0x001FFE00
#define PLL_REGM_SHIFT 9
#define PLL_REGM_F_MASK 0x0003FFFF
#define PLL_REGM_F_SHIFT 0
#define PLL_REGN_MASK 0x000001FE
#define PLL_REGN_SHIFT 1
#define PLL_SELFREQDCO_MASK 0x0000000E
#define PLL_SELFREQDCO_SHIFT 1
#define PLL_SD_MASK 0x0003FC00
#define PLL_SD_SHIFT 10
#define SET_PLL_GO 0x1
#define PLL_TICOPWDN BIT(16)
#define PLL_LDOPWDN BIT(15)
#define PLL_LOCK 0x2
#define PLL_IDLE 0x1
/* PHY POWER CONTROL Register */
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000
#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16
#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3
#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0
#define PLL_IDLE_TIME 100 /* in milliseconds */
#define PLL_LOCK_TIME 100 /* in milliseconds */
static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
{
return __raw_readl(addr + offset);
}
static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
u32 data)
{
__raw_writel(data, addr + offset);
}
static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
*pipe3)
{
u32 rate;
struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
rate = get_sys_clk_freq();
for (; dpll_map->rate; dpll_map++) {
if (rate == dpll_map->rate)
return &dpll_map->params;
}
printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
__func__, rate);
return NULL;
}
static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
{
u32 val;
int timeout = PLL_LOCK_TIME;
do {
mdelay(1);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
if (val & PLL_LOCK)
break;
} while (--timeout);
if (!(val & PLL_LOCK)) {
printf("%s: DPLL failed to lock\n", __func__);
return -EBUSY;
}
return 0;
}
static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
{
u32 val;
struct pipe3_dpll_params *dpll_params;
dpll_params = omap_pipe3_get_dpll_params(phy);
if (!dpll_params) {
printf("%s: Invalid DPLL parameters\n", __func__);
return -EINVAL;
}
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
val &= ~PLL_REGN_MASK;
val |= dpll_params->n << PLL_REGN_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
val &= ~PLL_SELFREQDCO_MASK;
val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
val &= ~PLL_REGM_MASK;
val |= dpll_params->m << PLL_REGM_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
val &= ~PLL_REGM_F_MASK;
val |= dpll_params->mf << PLL_REGM_F_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
val &= ~PLL_SD_MASK;
val |= dpll_params->sd << PLL_SD_SHIFT;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
return omap_pipe3_wait_lock(phy);
}
static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
{
u32 val, rate;
val = readl(phy->power_reg);
rate = get_sys_clk_freq();
rate = rate/1000000;
if (on) {
val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
val |= rate <<
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
} else {
val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
}
writel(val, phy->power_reg);
}
int phy_pipe3_power_on(struct omap_pipe3 *phy)
{
int ret;
u32 val;
/* Program the DPLL only if not locked */
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
if (!(val & PLL_LOCK)) {
ret = omap_pipe3_dpll_program(phy);
if (ret)
return ret;
} else {
/* else just bring it out of IDLE mode */
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
if (val & PLL_IDLE) {
val &= ~PLL_IDLE;
omap_pipe3_writel(phy->pll_ctrl_base,
PLL_CONFIGURATION2, val);
ret = omap_pipe3_wait_lock(phy);
if (ret)
return ret;
}
}
/* Power up the PHY */
omap_control_phy_power(phy, 1);
return 0;
}
int phy_pipe3_power_off(struct omap_pipe3 *phy)
{
u32 val;
int timeout = PLL_IDLE_TIME;
/* Power down the PHY */
omap_control_phy_power(phy, 0);
/* Put DPLL in IDLE mode */
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
val |= PLL_IDLE;
omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
/* wait for LDO and Oscillator to power down */
do {
mdelay(1);
val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
break;
} while (--timeout);
if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
__func__, val);
return -EBUSY;
}
return 0;
}

36
arch/arm/cpu/armv7/omap-common/pipe3-phy.h Normal file
View File

@ -0,0 +1,36 @@
/*
* TI PIPE3 PHY
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __OMAP_PIPE3_PHY_H
#define __OMAP_PIPE3_PHY_H
struct pipe3_dpll_params {
u16 m;
u8 n;
u8 freq:3;
u8 sd;
u32 mf;
};
struct pipe3_dpll_map {
unsigned long rate;
struct pipe3_dpll_params params;
};
struct omap_pipe3 {
void __iomem *pll_ctrl_base;
void __iomem *power_reg;
struct pipe3_dpll_map *dpll_map;
};
int phy_pipe3_power_on(struct omap_pipe3 *phy);
int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
#endif /* __OMAP_PIPE3_PHY_H */

75
arch/arm/cpu/armv7/omap-common/sata.c Normal file
View File

@ -0,0 +1,75 @@
/*
* TI SATA platform driver
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/clock.h>
#include <asm/arch/sata.h>
#include <asm/io.h>
#include "pipe3-phy.h"
static struct pipe3_dpll_map dpll_map_sata[] = {
{12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
{16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
{19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
{20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
{26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
{38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
{ }, /* Terminator */
};
struct omap_pipe3 sata_phy = {
.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
/* .power_reg is updated at runtime */
.dpll_map = dpll_map_sata,
};
int omap_sata_init(void)
{
int ret;
u32 val;
u32 const clk_domains_sata[] = {
0
};
u32 const clk_modules_hw_auto_sata[] = {
(*prcm)->cm_l3init_ocp2scp3_clkctrl,
0
};
u32 const clk_modules_explicit_en_sata[] = {
(*prcm)->cm_l3init_sata_clkctrl,
0
};
do_enable_clocks(clk_domains_sata,
clk_modules_hw_auto_sata,
clk_modules_explicit_en_sata,
0);
/* Enable optional functional clock for SATA */
setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
SATA_CLKCTRL_OPTFCLKEN_MASK);
sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
/* Power up the PHY */
phy_pipe3_power_on(&sata_phy);
/* Enable SATA module, No Idle, No Standby */
val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
ret = ahci_init(DWC_AHSATA_BASE);
scsi_scan(1);
return ret;
}

2
arch/arm/cpu/armv7/omap3/clock.c
View File

@ -730,8 +730,6 @@ void per_clocks_enable(void)
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
}
sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
sdelay(1000);
}

12
arch/arm/cpu/armv7/omap4/hw_data.c
View File

@ -288,17 +288,21 @@ struct vcores_data omap4460_volts = {
.mm.pmic = &twl6030,
};
/*
* Take closest integer part of the mV value corresponding to a TWL6032 SMPS
* voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
*/
struct vcores_data omap4470_volts = {
.mpu.value = 1200,
.mpu.value = 1202,
.mpu.addr = SMPS_REG_ADDR_SMPS1,
.mpu.pmic = &twl6030,
.core.value = 1126,
.core.addr = SMPS_REG_ADDR_SMPS1,
.core.addr = SMPS_REG_ADDR_SMPS2,
.core.pmic = &twl6030,
.mm.value = 1137,
.mm.addr = SMPS_REG_ADDR_SMPS1,
.mm.value = 1139,
.mm.addr = SMPS_REG_ADDR_SMPS5,
.mm.pmic = &twl6030,
};

9
arch/arm/cpu/armv7/omap4/sdram_elpida.c
View File

@ -32,7 +32,7 @@
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
.sdram_config_init = 0x80000eb9,
.sdram_config = 0x80001ab9,
.ref_ctrl = 0x0000030c,
@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
.emif_ddr_phy_ctlr_1 = 0x049ff808
};
static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
.sdram_config_init = 0x80000eb1,
.sdram_config = 0x80001ab1,
.ref_ctrl = 0x000005cd,
@ -321,3 +321,8 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
{
*regs = &mr_regs;
}
__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
{
return 0;
}

9
arch/arm/cpu/armv7/omap5/hw_data.c
View File

@ -600,6 +600,7 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = {
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_omap5432_es2 = {
@ -610,16 +611,18 @@ const struct ctrl_ioregs ioregs_omap5432_es2 = {
.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
};
const struct ctrl_ioregs ioregs_dra7xx_es1 = {
.ctrl_ddrch = 0x40404040,
.ctrl_lpddr2ch = 0x40404040,
.ctrl_ddr3ch = 0x80808080,
.ctrl_ddrio_0 = 0xbae8c631,
.ctrl_ddrio_1 = 0xb46318d8,
.ctrl_ddrio_0 = 0xA2084210,
.ctrl_ddrio_1 = 0x84210840,
.ctrl_ddrio_2 = 0x84210000,
.ctrl_emif_sdram_config_ext = 0xb2c00000,
.ctrl_emif_sdram_config_ext = 0x0001C1A7,
.ctrl_emif_sdram_config_ext_final = 0x000101A7,
.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
};

18
arch/arm/cpu/armv7/omap5/hwinit.c
View File

@ -168,12 +168,6 @@ void do_io_settings(void)
io_settings_lpddr2();
else
io_settings_ddr3();
/* Efuse settings */
writel(EFUSE_1, (*ctrl)->control_efuse_1);
writel(EFUSE_2, (*ctrl)->control_efuse_2);
writel(EFUSE_3, (*ctrl)->control_efuse_3);
writel(EFUSE_4, (*ctrl)->control_efuse_4);
}
static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
@ -297,13 +291,17 @@ void srcomp_enable(void)
void config_data_eye_leveling_samples(u32 emif_base)
{
const struct ctrl_ioregs *ioregs;
get_ioregs(&ioregs);
/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
if (emif_base == EMIF1_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
(*ctrl)->control_emif1_sdram_config_ext);
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif1_sdram_config_ext);
else if (emif_base == EMIF2_BASE)
writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
(*ctrl)->control_emif2_sdram_config_ext);
writel(ioregs->ctrl_emif_sdram_config_ext_final,
(*ctrl)->control_emif2_sdram_config_ext);
}
void init_omap_revision(void)

7
arch/arm/cpu/armv7/omap5/prcm-regs.c
View File

@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
.cm_l3init_p1500_clkctrl = 0x4a009378,
.cm_l3init_sata_clkctrl = 0x4a009388,
.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009400,
@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
.control_status = 0x4A002134,
.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
.control_phy_power_usb = 0x4A002370,
.control_phy_power_sata = 0x4A002374,
.control_padconf_core_base = 0x4A002800,
.control_paconf_global = 0x4A002DA0,
.control_paconf_mode = 0x4A002DA4,
@ -373,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_status = 0x4A002134,
.control_phy_power_sata = 0x4A002374,
.control_core_mac_id_0_lo = 0x4A002514,
.control_core_mac_id_0_hi = 0x4A002518,
.control_core_mac_id_1_lo = 0x4A00251C,
@ -698,6 +702,7 @@ struct prcm_regs const omap5_es2_prcm = {
.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
.cm_l3init_p1500_clkctrl = 0x4a009678,
.cm_l3init_sata_clkctrl = 0x4a009688,
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
@ -891,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = {
.cm_l3init_hsusbhost_clkctrl = 0x4a009340,
.cm_l3init_hsusbotg_clkctrl = 0x4a009348,
.cm_l3init_hsusbtll_clkctrl = 0x4a009350,
.cm_l3init_sata_clkctrl = 0x4a009388,
.cm_gmac_clkstctrl = 0x4a0093c0,
.cm_gmac_gmac_clkctrl = 0x4a0093d0,
.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
/* cm2.l4per */
.cm_l4per_clkstctrl = 0x4a009700,

214
arch/arm/cpu/armv7/omap5/sdram.c
View File

@ -148,13 +148,13 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0E20400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_3 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_4 = 0x009E009E,
.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@ -172,13 +172,13 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0020400A,
.emif_ddr_phy_ctlr_1 = 0x0E24400A,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_3 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_4 = 0x009D009D,
.emif_ddr_ext_phy_ctrl_5 = 0x009D009D,
.emif_ddr_phy_ctlr_1_init = 0x0024400A,
.emif_ddr_phy_ctlr_1 = 0x0024400A,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_3 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_4 = 0x00B000B0,
.emif_ddr_ext_phy_ctrl_5 = 0x00B000B0,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
@ -306,7 +306,7 @@ void emif_get_device_details(u32 emif_nr,
#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
const u32 ext_phy_ctrl_const_base[] = {
0x01004010,
0x00001004,
0x04010040,
@ -329,7 +329,7 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
0x01004010,
0x00001004,
0x04010040,
@ -352,7 +352,7 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x0
};
const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
0x50D4350D,
0x00000D43,
0x04010040,
@ -376,51 +376,61 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
};
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x009E009E,
0x002E002E,
0x002E002E,
0x002E002E,
0x002E002E,
0x002E002E,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x004D004D,
0x0,
0x600020,
dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
0x00B000B0,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00800080,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00800080,
0x00800080,
0x40010080,
0x8102040
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0
};
const u32
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
0x009D009D,
0x002D002D,
0x002D002D,
0x002D002D,
0x002D002D,
0x002D002D,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
0x00570057,
dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
0x00BB00BB,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x00440044,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x00600060,
0x0,
0x600020,
0x00600020,
0x40010080,
0x8102040
0x08102040,
0x0,
0x0,
0x0,
0x0,
0x0
};
const struct lpddr2_mr_regs mr_regs = {
@ -431,27 +441,38 @@ const struct lpddr2_mr_regs mr_regs = {
.mr16 = MR16_REF_FULL_ARRAY
};
static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
const u32 **regs,
u32 *size)
{
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
*regs = ext_phy_ctrl_const_base;
*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
break;
case OMAP5432_ES1_0:
*regs = ddr3_ext_phy_ctrl_const_base_es1;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
break;
case OMAP5432_ES2_0:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
break;
case DRA752_ES1_0:
if (emif_nr == 1)
if (emif_nr == 1) {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
else
*size =
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
} else {
*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
*size =
ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
}
break;
default:
*regs = ddr3_ext_phy_ctrl_const_base_es2;
*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
}
}
@ -468,6 +489,7 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
u32 emif_nr;
const u32 *ext_phy_ctrl_const_regs;
u32 i = 0;
u32 size;
emif_nr = (base == EMIF1_BASE) ? 1 : 2;
@ -487,8 +509,10 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
* external phy 6-24 registers do not change with
* ddr frequency
*/
emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
emif_get_ext_phy_ctrl_const_regs(emif_nr,
&ext_phy_ctrl_const_regs, &size);
for (i = 0; i < size; i++) {
writel(ext_phy_ctrl_const_regs[i],
emif_ext_phy_ctrl_base++);
/* Update shadow registers */
@ -545,6 +569,74 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = {
.min_tck = &min_tck,
};
/*
* List of status registers to be controlled back to control registers
* after initial leveling
* readreg, writereg
*/
const struct read_write_regs omap5_bug_00339_regs[] = {
{ 8, 5 },
{ 9, 6 },
{ 10, 7 },
{ 14, 8 },
{ 15, 9 },
{ 16, 10 },
{ 11, 2 },
{ 12, 3 },
{ 13, 4 },
{ 17, 11 },
{ 18, 12 },
{ 19, 13 },
};
const struct read_write_regs dra_bug_00339_regs[] = {
{ 7, 7 },
{ 8, 8 },
{ 9, 9 },
{ 10, 10 },
{ 11, 11 },
{ 12, 2 },
{ 13, 3 },
{ 14, 4 },
{ 15, 5 },
{ 16, 6 },
{ 17, 12 },
{ 18, 13 },
{ 19, 14 },
{ 20, 15 },
{ 21, 16 },
{ 22, 17 },
{ 23, 18 },
{ 24, 19 },
{ 25, 20 },
{ 26, 21}
};
const struct read_write_regs *get_bug_regs(u32 *iterations)
{
const struct read_write_regs *bug_00339_regs_ptr = NULL;
switch (omap_revision()) {
case OMAP5430_ES1_0:
case OMAP5430_ES2_0:
case OMAP5432_ES1_0:
case OMAP5432_ES2_0:
bug_00339_regs_ptr = omap5_bug_00339_regs;
*iterations = sizeof(omap5_bug_00339_regs)/
sizeof(omap5_bug_00339_regs[0]);
break;
case DRA752_ES1_0:
bug_00339_regs_ptr = dra_bug_00339_regs;
*iterations = sizeof(dra_bug_00339_regs)/
sizeof(dra_bug_00339_regs[0]);
break;
default:
printf("\n Error: UnKnown SOC");
}
return bug_00339_regs_ptr;
}
void emif_get_device_timings_sdp(u32 emif_nr,
const struct lpddr2_device_timings **cs0_device_timings,
const struct lpddr2_device_timings **cs1_device_timings)

37
arch/arm/include/asm/arch-am33xx/ddr_defs.h
View File

@ -18,7 +18,6 @@
#define VTP_CTRL_READY (0x1 << 5)
#define VTP_CTRL_ENABLE (0x1 << 6)
#define VTP_CTRL_START_EN (0x1)
#define PHY_DLL_LOCK_DIFF 0x0
#define DDR_CKE_CTRL_NORMAL 0x1
#define PHY_EN_DYN_PWRDN (0x1 << 20)
@ -29,7 +28,6 @@
#define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0
#define MT47H128M16RT25E_RATIO 0x80
#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
@ -38,7 +36,6 @@
#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
@ -49,7 +46,6 @@
#define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
#define MT41J128MJT125_EMIF_SDREF 0x0000093B
#define MT41J128MJT125_ZQ_CFG 0x50074BE4
#define MT41J128MJT125_DLL_LOCK_DIFF 0x1
#define MT41J128MJT125_RATIO 0x40
#define MT41J128MJT125_INVERT_CLKOUT 0x1
#define MT41J128MJT125_RD_DQS 0x3B
@ -58,6 +54,12 @@
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
/* Micron MT41J64M16JT-125 */
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
/* Micron MT41J256M16JT-125 */
#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
/* Micron MT41J256M8HX-15E */
#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
@ -66,7 +68,6 @@
#define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
#define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
#define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1
#define MT41J256M8HX15E_RATIO 0x40
#define MT41J256M8HX15E_INVERT_CLKOUT 0x1
#define MT41J256M8HX15E_RD_DQS 0x3B
@ -83,7 +84,6 @@
#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
#define MT41K256M16HA125E_EMIF_SDREF 0xC30
#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1
#define MT41K256M16HA125E_RATIO 0x80
#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
#define MT41K256M16HA125E_RD_DQS 0x38
@ -100,7 +100,6 @@
#define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
#define MT41J512M8RH125_EMIF_SDREF 0x0000093B
#define MT41J512M8RH125_ZQ_CFG 0x50074BE4
#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1
#define MT41J512M8RH125_RATIO 0x80
#define MT41J512M8RH125_INVERT_CLKOUT 0x0
#define MT41J512M8RH125_RD_DQS 0x3B
@ -117,7 +116,6 @@
#define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
#define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
#define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1
#define K4B2G1646EBIH9_RATIO 0x80
#define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
#define K4B2G1646EBIH9_RD_DQS 0x35
@ -149,18 +147,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr);
struct ddr_cmd_regs {
unsigned int resv0[7];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int resv1[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int resv1[3];
unsigned int cm0iclkout; /* offset 0x02C */
unsigned int resv2[8];
unsigned int cm1csratio; /* offset 0x050 */
unsigned int resv3[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int resv3[3];
unsigned int cm1iclkout; /* offset 0x060 */
unsigned int resv4[8];
unsigned int cm2csratio; /* offset 0x084 */
unsigned int resv5[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int resv5[3];
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv6[3];
};
@ -197,24 +192,21 @@ struct ddr_regs {
unsigned int cm0configclk; /* offset 0x010 */
unsigned int resv1[2];
unsigned int cm0csratio; /* offset 0x01C */
unsigned int resv2[2];
unsigned int cm0dldiff; /* offset 0x028 */
unsigned int resv2[3];
unsigned int cm0iclkout; /* offset 0x02C */
unsigned int resv3[4];
unsigned int cm1config; /* offset 0x040 */
unsigned int cm1configclk; /* offset 0x044 */
unsigned int resv4[2];
unsigned int cm1csratio; /* offset 0x050 */
unsigned int resv5[2];
unsigned int cm1dldiff; /* offset 0x05C */
unsigned int resv5[3];
unsigned int cm1iclkout; /* offset 0x060 */
unsigned int resv6[4];
unsigned int cm2config; /* offset 0x074 */
unsigned int cm2configclk; /* offset 0x078 */
unsigned int resv7[2];
unsigned int cm2csratio; /* offset 0x084 */
unsigned int resv8[2];
unsigned int cm2dldiff; /* offset 0x090 */
unsigned int resv8[3];
unsigned int cm2iclkout; /* offset 0x094 */
unsigned int resv9[12];
unsigned int dt0rdsratio0; /* offset 0x0C8 */
@ -243,17 +235,14 @@ struct cmd_control {
unsigned long cmd0csratio;
unsigned long cmd0csforce;
unsigned long cmd0csdelay;
unsigned long cmd0dldiff;
unsigned long cmd0iclkout;
unsigned long cmd1csratio;
unsigned long cmd1csforce;
unsigned long cmd1csdelay;
unsigned long cmd1dldiff;
unsigned long cmd1iclkout;
unsigned long cmd2csratio;
unsigned long cmd2csforce;
unsigned long cmd2csdelay;
unsigned long cmd2dldiff;
unsigned long cmd2iclkout;
};
@ -267,8 +256,6 @@ struct ddr_data {
unsigned long datagiratio0;
unsigned long datafwsratio0;
unsigned long datawrsratio0;
unsigned long datauserank0delay;
unsigned long datadldiff0;
};
/**

3
arch/arm/include/asm/arch-davinci/hardware.h
View File

@ -478,8 +478,9 @@ struct davinci_syscfg_regs {
dv_reg rsvd[13];
dv_reg kick0;
dv_reg kick1;
dv_reg rsvd1[53];
dv_reg rsvd1[52];
dv_reg mstpri[3];
dv_reg rsvd2;
dv_reg pinmux[20];
dv_reg suspsrc;
dv_reg chipsig;

2
arch/arm/include/asm/arch-omap3/clock.h
View File

@ -27,8 +27,6 @@
#define ICK_DSS_ON 0x00000001
#define FCK_CAM_ON 0x00000001
#define ICK_CAM_ON 0x00000001
#define FCK_PER_ON 0x0003ffff
#define ICK_PER_ON 0x0003ffff
/* Used to index into DPLL parameter tables */
typedef struct {

1
arch/arm/include/asm/arch-omap3/omap3.h
View File

@ -55,6 +55,7 @@ struct control_prog_io {
#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000)
#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000)
#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000)
#define OMAP34XX_UART4 (OMAP34XX_L4_PER + 0x42000)
/* General Purpose Timers */
#define OMAP34XX_GPT1 0x48318000

4
arch/arm/include/asm/arch-omap4/sys_proto.h
View File

@ -16,6 +16,10 @@
DECLARE_GLOBAL_DATA_PTR;
extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
struct omap_sysinfo {
char *board_string;
};

3
arch/arm/include/asm/arch-omap5/clock.h
View File

@ -137,6 +137,9 @@
#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
/* CM_L3INIT_SATA_CLKCTRL */
#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
/* CM_WKUP_GPTIMER1_CLKCTRL */
#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)

4
arch/arm/include/asm/arch-omap5/omap.h
View File

@ -64,6 +64,9 @@
/* QSPI */
#define QSPI_BASE 0x4B300000
/* SATA */
#define DWC_AHSATA_BASE 0x4A140000
/*
* Hardware Register Details
*/
@ -239,6 +242,7 @@ struct ctrl_ioregs {
u32 ctrl_ddrio_1;
u32 ctrl_ddrio_2;
u32 ctrl_emif_sdram_config_ext;
u32 ctrl_emif_sdram_config_ext_final;
u32 ctrl_ddr_ctrl_ext_0;
};

48
arch/arm/include/asm/arch-omap5/sata.h Normal file
View File

@ -0,0 +1,48 @@
/*
* SATA Wrapper Register map
*
* (C) Copyright 2013
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TI_SATA_H
#define _TI_SATA_H
/* SATA Wrapper module */
#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100)
/* SATA PHY Module */
#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800)
/* SATA Wrapper register offsets */
#define TI_SATA_SYSCONFIG 0x00
#define TI_SATA_CDRLOCK 0x04
/* Register Set */
#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16)
#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4)
#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2)
/* Standby modes */
#define TI_SATA_STANDBY_FORCE 0x0
#define TI_SATA_STANDBY_NO (0x1 << 4)
#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4)
#define TI_SATA_STANDBY_SMART (0x2 << 4)
/* Idle modes */
#define TI_SATA_IDLE_FORCE 0x0
#define TI_SATA_IDLE_NO (0x1 << 2)
#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2)
#define TI_SATA_IDLE_SMART (0x2 << 2)
#ifdef CONFIG_SCSI_AHCI_PLAT
int omap_sata_init(void);
#else
static inline int omap_sata_init(void)
{
return 0;
}
#endif /* CONFIG_SCSI_AHCI_PLAT */
#endif /* _TI_SATA_H */

14
arch/arm/include/asm/emif.h
View File

@ -581,7 +581,6 @@
(0xFF << EMIF_SYS_ADDR_SHIFT))
#define EMIF_EXT_PHY_CTRL_TIMING_REG 0x5
#define EMIF_EXT_PHY_CTRL_CONST_REG 0x14
/* Reg mapping structure */
struct emif_reg_struct {
@ -641,7 +640,9 @@ struct emif_reg_struct {
u32 emif_ddr_phy_ctrl_2;
u32 padding7[12];
u32 emif_rd_wr_exec_thresh;
u32 padding8[55];
u32 padding8[7];
u32 emif_ddr_phy_status[21];
u32 padding9[27];
u32 emif_ddr_ext_phy_ctrl_1;
u32 emif_ddr_ext_phy_ctrl_1_shdw;
u32 emif_ddr_ext_phy_ctrl_2;
@ -690,6 +691,9 @@ struct emif_reg_struct {
u32 emif_ddr_ext_phy_ctrl_23_shdw;
u32 emif_ddr_ext_phy_ctrl_24;
u32 emif_ddr_ext_phy_ctrl_24_shdw;
u32 padding[22];
u32 emif_ddr_fifo_misaligned_clear_1;
u32 emif_ddr_fifo_misaligned_clear_2;
};
struct dmm_lisa_map_regs {
@ -1139,6 +1143,11 @@ struct lpddr2_mr_regs {
s8 mr16;
};
struct read_write_regs {
u32 read_reg;
u32 write_reg;
};
/* assert macros */
#if defined(DEBUG)
#define emif_assert(c) ({ if (!(c)) for (;;); })
@ -1167,4 +1176,5 @@ extern u32 *const T_den;
void config_data_eye_leveling_samples(u32 emif_base);
u32 emif_sdram_type(void);
const struct read_write_regs *get_bug_regs(u32 *iterations);
#endif

10
arch/arm/include/asm/omap_common.h
View File

@ -226,6 +226,7 @@ struct prcm_regs {
u32 cm_l3init_hsusbotg_clkctrl;
u32 cm_l3init_hsusbtll_clkctrl;
u32 cm_l3init_p1500_clkctrl;
u32 cm_l3init_sata_clkctrl;
u32 cm_l3init_fsusb_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
@ -366,6 +367,7 @@ struct omap_sys_ctrl_regs {
u32 control_ldosram_mpu_voltage_ctrl;
u32 control_ldosram_core_voltage_ctrl;
u32 control_usbotghs_ctrl;
u32 control_phy_power_sata;
u32 control_padconf_core_base;
u32 control_paconf_global;
u32 control_paconf_mode;
@ -605,6 +607,14 @@ static inline u8 is_omap54xx(void)
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
}
#define DRA7XX 0x07000000
static inline u8 is_dra7xx(void)
{
extern u32 *const omap_si_rev;
return ((*omap_si_rev & 0xFF000000) == DRA7XX);
}
#endif
/*

10
board/compulab/cm_t335/Makefile Normal file
View File

@ -0,0 +1,10 @@
#
# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
#
# Author: Ilya Ledvich <ilya@compulab.co.il>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += $(BOARD).o
obj-$(CONFIG_SPL_BUILD) += mux.o spl.o

162
board/compulab/cm_t335/cm_t335.c Normal file
View File

@ -0,0 +1,162 @@
/*
* Board functions for Compulab CM-T335 board
*
* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
*
* Author: Ilya Ledvich <ilya@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <miiphy.h>
#include <cpsw.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware_am33xx.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
#endif
return 0;
}
#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slave = {
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = &cpsw_slave,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
/* PHY reset GPIO */
#define GPIO_PHY_RST GPIO_PIN(3, 7)
static void board_phy_init(void)
{
gpio_request(GPIO_PHY_RST, "phy_rst");
gpio_direction_output(GPIO_PHY_RST, 0);
mdelay(2);
gpio_set_value(GPIO_PHY_RST, 1);
mdelay(2);
}
static void get_efuse_mac_addr(uchar *enetaddr)
{
uint32_t mac_hi, mac_lo;
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
enetaddr[0] = mac_hi & 0xFF;
enetaddr[1] = (mac_hi & 0xFF00) >> 8;
enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
enetaddr[4] = mac_lo & 0xFF;
enetaddr[5] = (mac_lo & 0xFF00) >> 8;
}
/*
* Routine: handle_mac_address
* Description: prepare MAC address for on-board Ethernet.
*/
static int handle_mac_address(void)
{
uchar enetaddr[6];
int rv;
rv = eth_getenv_enetaddr("ethaddr", enetaddr);
if (rv)
return 0;
rv = cl_eeprom_read_mac_addr(enetaddr);
if (rv)
get_efuse_mac_addr(enetaddr);
if (!is_valid_ether_addr(enetaddr))
return -1;
return eth_setenv_enetaddr("ethaddr", enetaddr);
}
#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
#define AR8051_PHY_DEBUG_DATA_REG 0x1e
#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
#define AR8051_RGMII_TX_CLK_DLY 0x100
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
const char *devname;
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
rv = handle_mac_address();
if (rv)
printf("No MAC address found!\n");
writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
board_phy_init();
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
/*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the AR8051 PHY. Since we only support a single ethernet
* device, we only do this for the first instance.
*/
devname = miiphy_get_current_dev();
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
AR8051_DEBUG_RGMII_CLK_DLY_REG);
miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
AR8051_RGMII_TX_CLK_DLY);
return n;
}
#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */

117
board/compulab/cm_t335/mux.c Normal file
View File

@ -0,0 +1,117 @@
/*
* Pinmux configuration for Compulab CM-T335 board
*
* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
*
* Author: Ilya Ledvich <ilya@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux uart1_pin_mux[] = {
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
{OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
{-1},
};
static struct module_pin_mux i2c1_pin_mux[] = {
/* I2C_DATA */
{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
/* I2C_SCLK */
{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
{-1},
};
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
static struct module_pin_mux eth_phy_rst_pin_mux[] = {
{OFFSET(emu0), (MODE(7) | PULLUDDIS)}, /* GPIO3_7 */
{-1},
};
static struct module_pin_mux status_led_pin_mux[] = {
{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)}, /* GPIO2_0 */
{-1},
};
void set_uart_mux_conf(void)
{
configure_module_pin_mux(uart0_pin_mux);
configure_module_pin_mux(uart1_pin_mux);
}
void set_mux_conf_regs(void)
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(i2c1_pin_mux);
configure_module_pin_mux(rgmii1_pin_mux);
configure_module_pin_mux(eth_phy_rst_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(nand_pin_mux);
configure_module_pin_mux(status_led_pin_mux);
}

106
board/compulab/cm_t335/spl.c Normal file
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@ -0,0 +1,106 @@
/*
* SPL specific code for Compulab CM-T335 board
*
* Board functions for Compulab CM-T335 board
*
* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
*
* Author: Ilya Ledvich <ilya@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware_am33xx.h>
#include <asm/sizes.h>
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J128MJT125_RD_DQS,
.datawdsratio0 = MT41J128MJT125_WR_DQS,
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd1csratio = MT41J128MJT125_RATIO,
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd2csratio = MT41J128MJT125_RATIO,
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41J128MJT125_EMIF_SDCFG,
.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
.zq_config = MT41J128MJT125_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
const struct dpll_params dpll_ddr = {
/* M N M2 M3 M4 M5 M6 */
303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
return &dpll_ddr;
}
static void probe_sdram_size(long size)
{
switch (size) {
case SZ_512M:
ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
break;
case SZ_256M:
ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
break;
case SZ_128M:
ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
break;
default:
puts("Failed configuring DRAM, resetting...\n\n");
reset_cpu(0);
}
debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
void sdram_init(void)
{
long size = SZ_1G;
do {
size = size / 2;
probe_sdram_size(size);
} while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
return;
}

101
board/compulab/cm_t335/u-boot.lds Normal file
View File

@ -0,0 +1,101 @@
/*
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
board/compulab/cm_t335/libcm_t335.o (.text*)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data*)
}
. = ALIGN(4);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.image_copy_end :
{
*(.__image_copy_end)
}
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
.rel.dyn : {
*(.rel*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
}
_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_limit = .;
}
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

4
board/isee/igep0033/board.c
View File

@ -35,20 +35,16 @@ static const struct ddr_data ddr3_data = {
.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = K4B2G1646EBIH9_RATIO,
.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
.cmd1csratio = K4B2G1646EBIH9_RATIO,
.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
.cmd2csratio = K4B2G1646EBIH9_RATIO,
.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
};

53
board/phytec/pcm051/board.c
View File

@ -49,25 +49,22 @@ const struct dpll_params *get_dpll_ddr_params(void)
return &dpll_ddr;
}
#ifdef CONFIG_REV1
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41J256M8HX15E_RD_DQS,
.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J256M8HX15E_RATIO,
.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
.cmd1csratio = MT41J256M8HX15E_RATIO,
.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
.cmd2csratio = MT41J256M8HX15E_RATIO,
.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
};
@ -82,6 +79,48 @@ static struct emif_regs ddr3_emif_reg_data = {
PHY_EN_DYN_PWRDN,
};
void sdram_init(void)
{
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#else
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
void sdram_init(void)
{
config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
@ -95,12 +134,6 @@ void set_mux_conf_regs(void)
enable_board_pin_mux();
}
void sdram_init(void)
{
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif
/*

4
board/siemens/dxr2/board.c
View File

@ -140,13 +140,9 @@ struct emif_regs dxr2_ddr3_emif_reg_data = {
};
struct ddr_data dxr2_ddr3_data = {
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
.cmd0dldiff = 0,
.cmd1dldiff = 0,
.cmd2dldiff = 0,
};
/* pass values from eeprom */
dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;

5
board/siemens/pxm2/board.c
View File

@ -58,19 +58,14 @@ struct ddr_data pxm2_ddr3_data = {
.datawdsratio0 = 0,
.datafwsratio0 = 0x8020080,
.datawrsratio0 = 0x4010040,
.datauserank0delay = 1,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
.cmd0csratio = 0x80,
.cmd0dldiff = 0,
.cmd0iclkout = 0,
.cmd1csratio = 0x80,
.cmd1dldiff = 0,
.cmd1iclkout = 0,
.cmd2csratio = 0x80,
.cmd2dldiff = 0,
.cmd2iclkout = 0,
};

5
board/siemens/rut/board.c
View File

@ -63,19 +63,14 @@ struct ddr_data rut_ddr3_data = {
.datawdsratio0 = 0x85,
.datafwsratio0 = 0x100,
.datawrsratio0 = 0xc1,
.datauserank0delay = 1,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
struct cmd_control rut_ddr3_cmd_ctrl_data = {
.cmd0csratio = 0x40,
.cmd0dldiff = 0,
.cmd0iclkout = 1,
.cmd1csratio = 0x40,
.cmd1dldiff = 0,
.cmd1iclkout = 1,
.cmd2csratio = 0x40,
.cmd2dldiff = 0,
.cmd2iclkout = 1,
};

17
board/ti/am335x/board.c
View File

@ -107,21 +107,16 @@ static const struct ddr_data ddr2_data = {
(MT47H128M16RT25E_PHY_WR_DATA<<20) |
(MT47H128M16RT25E_PHY_WR_DATA<<10) |
(MT47H128M16RT25E_PHY_WR_DATA<<0)),
.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
.cmd2csratio = MT47H128M16RT25E_RATIO,
.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
};
@ -139,7 +134,6 @@ static const struct ddr_data ddr3_data = {
.datawdsratio0 = MT41J128MJT125_WR_DQS,
.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_beagleblack_data = {
@ -147,7 +141,6 @@ static const struct ddr_data ddr3_beagleblack_data = {
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct ddr_data ddr3_evm_data = {
@ -155,48 +148,38 @@ static const struct ddr_data ddr3_evm_data = {
.datawdsratio0 = MT41J512M8RH125_WR_DQS,
.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41J128MJT125_RATIO,
.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd1csratio = MT41J128MJT125_RATIO,
.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
.cmd2csratio = MT41J128MJT125_RATIO,
.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
.cmd0csratio = MT41J512M8RH125_RATIO,
.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
.cmd1csratio = MT41J512M8RH125_RATIO,
.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
.cmd2csratio = MT41J512M8RH125_RATIO,
.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
};

7
board/ti/dra7xx/evm.c
View File

@ -14,6 +14,7 @@
#include <palmas.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sata.h>
#include "mux_data.h"
@ -77,6 +78,12 @@ int board_init(void)
return 0;
}
int board_late_init(void)
{
omap_sata_init();
return 0;
}
/**
* @brief misc_init_r - Configure EVM board specific configurations
* such as power configurations, ethernet initialization as phase2 of

7
board/ti/omap5_uevm/evm.c
View File

@ -20,6 +20,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include <asm/arch/sata.h>
#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
#define DIE_ID_REG_OFFSET 0x200
@ -67,6 +68,12 @@ int board_init(void)
return 0;
}
int board_late_init(void)
{
omap_sata_init();
return 0;
}
int board_eth_init(bd_t *bis)
{
return 0;

60
board/ti/panda/panda.c
View File

@ -122,6 +122,66 @@ int get_board_revision(void)
return board_id;
}
/**
* is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
*
*
* Detect if we are running on B3 version of ES panda board,
* This can be done by reading the level of GPIO 171 and checking the
* processor revisions.
* GPIO171: 1 => Panda ES Rev B3
*
* Return : return 1 if Panda ES Rev B3 , else return 0
*/
u8 is_panda_es_rev_b3(void)
{
int processor_rev = omap_revision();
int ret = 0;
if ((processor_rev >= OMAP4460_ES1_0 &&
processor_rev <= OMAP4460_ES1_1)) {
/* Setup the mux for the common board ID pins (gpio 171) */
writew((IEN | M3),
(*ctrl)->control_padconf_core_base + UNIPRO_TX0);
/* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
}
return ret;
}
#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
/*
* emif_get_reg_dump() - emif_get_reg_dump strong function
*
* @emif_nr - emif base
* @regs - reg dump of timing values
*
* Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
*/
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
u32 omap4_rev = omap_revision();
/* Same devices and geometry on both EMIFs */
if (omap4_rev == OMAP4430_ES1_0)
*regs = &emif_regs_elpida_380_mhz_1cs;
else if (omap4_rev == OMAP4430_ES2_0)
*regs = &emif_regs_elpida_200_mhz_2cs;
else if (omap4_rev == OMAP4430_ES2_3)
*regs = &emif_regs_elpida_400_mhz_1cs;
else if (omap4_rev < OMAP4470_ES1_0) {
if(is_panda_es_rev_b3())
*regs = &emif_regs_elpida_400_mhz_1cs;
else
*regs = &emif_regs_elpida_400_mhz_2cs;
}
else
*regs = &emif_regs_elpida_400_mhz_1cs;
}
#endif
/**
* @brief misc_init_r - Configure Panda board specific configurations
* such as power configurations, ethernet initialization as phase2 of

5
board/ti/ti814x/evm.c
View File

@ -33,15 +33,12 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifdef CONFIG_SPL_BUILD
static const struct cmd_control evm_ddr2_cctrl_data = {
.cmd0csratio = 0x80,
.cmd0dldiff = 0x04,
.cmd0iclkout = 0x00,
.cmd1csratio = 0x80,
.cmd1dldiff = 0x04,
.cmd1iclkout = 0x00,
.cmd2csratio = 0x80,
.cmd2dldiff = 0x04,
.cmd2iclkout = 0x00,
};
@ -77,8 +74,6 @@ static const struct ddr_data evm_ddr2_data = {
.datagiratio0 = ((0<<10) | (0<<0)),
.datafwsratio0 = ((0x90<<10) | (0x90<<0)),
.datawrsratio0 = ((0x50<<10) | (0x50<<0)),
.datauserank0delay = 1,
.datadldiff0 = 0x4,
};
void set_uart_mux_conf(void)

17
board/ti/ti816x/evm.c
View File

@ -59,21 +59,16 @@ static struct ddr_data ddr2_data = {
.datagiratio0 = ((0x0<<10) | (0x0<<0)),
.datafwsratio0 = ((0x13A<<10) | (0x13A<<0)),
.datawrsratio0 = ((0x8A<<10) | (0x8A<<0)),
.datauserank0delay = 0x1,
.datadldiff0 = 0x0, /* depend on cpu rev, set later */
};
static struct cmd_control ddr2_ctrl = {
.cmd0csratio = 0x80,
.cmd0dldiff = 0x04, /* reset value is 0x4 */
.cmd0iclkout = 0x00,
.cmd1csratio = 0x80,
.cmd1dldiff = 0x04, /* reset value is 0x4 */
.cmd1iclkout = 0x00,
.cmd2csratio = 0x80,
.cmd2dldiff = 0x04, /* reset value is 0x4 */
.cmd2iclkout = 0x00,
};
@ -150,21 +145,16 @@ static struct ddr_data ddr3_data = {
.datagiratio0 = ((0x20<<10) | 0x20<<0),
.datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
.datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
.datauserank0delay = 0x1,
.datadldiff0 = 0x0, /* depend on cpu rev, set later */
};
static const struct cmd_control ddr3_ctrl = {
.cmd0csratio = 0x100,
.cmd0dldiff = 0x004, /* reset value is 0x4 */
.cmd0iclkout = 0x001,
.cmd1csratio = 0x100,
.cmd1dldiff = 0x004, /* reset value is 0x4 */
.cmd1iclkout = 0x001,
.cmd2csratio = 0x100,
.cmd2dldiff = 0x004, /* reset value is 0x4 */
.cmd2iclkout = 0x001,
};
@ -198,11 +188,6 @@ void sdram_init(void)
config_dmm(&evm_lisa_map_regs);
#ifdef CONFIG_TI816X_EVM_DDR2
ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
if (CONFIG_TI816X_USE_EMIF0) {
ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
@ -217,8 +202,6 @@ void sdram_init(void)
#endif
#ifdef CONFIG_TI816X_EVM_DDR3
ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
if (CONFIG_TI816X_USE_EMIF0)
config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);

4
boards.cfg
View File

@ -244,8 +244,10 @@ Active arm arm946es - armltd integrator
Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
Active arm armv7 am33xx compulab cm_t335 cm_t335 cm_t335 Igor Grinberg <grinberg@compulab.co.il>
Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>

18
drivers/block/ahci.c
View File

@ -379,6 +379,11 @@ static int ahci_init_one(pci_dev_t pdev)
int rc;
probe_ent = malloc(sizeof(struct ahci_probe_ent));
if (!probe_ent) {
printf("%s: No memory for probe_ent\n", __func__);
return -ENOMEM;
}
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->dev = pdev;
@ -503,7 +508,7 @@ static int ahci_port_start(u8 port)
mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
if (!mem) {
free(pp);
printf("No mem for table!\n");
printf("%s: No mem for table!\n", __func__);
return -ENOMEM;
}
@ -618,7 +623,7 @@ static int ata_scsiop_inquiry(ccb *pccb)
95 - 4,
};
u8 fis[20];
u16 *tmpid;
ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
u8 port;
/* Clean ccb data buffer */
@ -637,14 +642,10 @@ static int ata_scsiop_inquiry(ccb *pccb)
/* Read id from sata */
port = pccb->target;
tmpid = malloc(ATA_ID_WORDS * 2);
if (!tmpid)
return -ENOMEM;
if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
ATA_ID_WORDS * 2, 0)) {
debug("scsi_ahci: SCSI inquiry command failure.\n");
free(tmpid);
return -EIO;
}
@ -889,6 +890,11 @@ int ahci_init(u32 base)
u32 linkmap;
probe_ent = malloc(sizeof(struct ahci_probe_ent));
if (!probe_ent) {
printf("%s: No memory for probe_ent\n", __func__);
return -ENOMEM;
}
memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
probe_ent->host_flags = ATA_FLAG_SATA

2
drivers/net/cpsw.c
View File

@ -914,7 +914,7 @@ static int cpsw_recv(struct eth_device *dev)
void *buffer;
int len;
cpsw_update_link(priv);
cpsw_check_link(priv);
while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
invalidate_dcache_range((unsigned long)buffer,

77
drivers/power/twl6030.c
View File

@ -9,6 +9,26 @@
#include <twl6030.h>
static struct twl6030_data *twl;
static struct twl6030_data twl6030_info = {
.chip_type = chip_TWL6030,
.adc_rbase = GPCH0_LSB,
.adc_ctrl = CTRL_P2,
.adc_enable = CTRL_P2_SP2,
.vbat_mult = TWL6030_VBAT_MULT,
.vbat_shift = TWL6030_VBAT_SHIFT,
};
static struct twl6030_data twl6032_info = {
.chip_type = chip_TWL6032,
.adc_rbase = TWL6032_GPCH0_LSB,
.adc_ctrl = TWL6032_CTRL_P1,
.adc_enable = CTRL_P1_SP1,
.vbat_mult = TWL6032_VBAT_MULT,
.vbat_shift = TWL6032_VBAT_SHIFT,
};
static int twl6030_gpadc_read_channel(u8 channel_no)
{
u8 lsb = 0;
@ -16,12 +36,12 @@ static int twl6030_gpadc_read_channel(u8 channel_no)
int ret = 0;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
GPCH0_LSB + channel_no * 2, &lsb);
twl->adc_rbase + channel_no * 2, &lsb);
if (ret)
return ret;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
GPCH0_MSB + channel_no * 2, &msb);
twl->adc_rbase + 1 + channel_no * 2, &msb);
if (ret)
return ret;
@ -33,7 +53,8 @@ static int twl6030_gpadc_sw2_trigger(void)
u8 val;
int ret = 0;
ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2);
ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
twl->adc_ctrl, twl->adc_enable);
if (ret)
return ret;
@ -41,7 +62,8 @@ static int twl6030_gpadc_sw2_trigger(void)
val = CTRL_P2_BUSY;
while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val);
ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
twl->adc_ctrl, &val);
if (ret)
return ret;
udelay(1000);
@ -102,6 +124,18 @@ int twl6030_get_battery_voltage(void)
{
int battery_volt = 0;
int ret = 0;
u8 vbatch;
if (twl->chip_type == chip_TWL6030) {
vbatch = TWL6030_GPADC_VBAT_CHNL;
} else {
ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
TWL6032_GPSELECT_ISB,
TWL6032_GPADC_VBAT_CHNL);
if (ret)
return ret;
vbatch = 0;
}
/* Start GPADC SW conversion */
ret = twl6030_gpadc_sw2_trigger();
@ -111,12 +145,12 @@ int twl6030_get_battery_voltage(void)
}
/* measure Vbat voltage */
battery_volt = twl6030_gpadc_read_channel(7);
battery_volt = twl6030_gpadc_read_channel(vbatch);
if (battery_volt < 0) {
printf("Failed to read battery voltage\n");
return ret;
}
battery_volt = (battery_volt * 25 * 1000) >> (10 + 2);
battery_volt = (battery_volt * twl->vbat_mult) >> twl->vbat_shift;
printf("Battery Voltage: %d mV\n", battery_volt);
return battery_volt;
@ -124,12 +158,35 @@ int twl6030_get_battery_voltage(void)
void twl6030_init_battery_charging(void)
{
u8 stat1 = 0;
u8 val = 0;
int battery_volt = 0;
int ret = 0;
ret = twl6030_i2c_read_u8(TWL6030_CHIP_USB, USB_PRODUCT_ID_LSB, &val);
if (ret) {
puts("twl6030_init_battery_charging(): could not determine chip!\n");
return;
}
if (val == 0x30) {
twl = &twl6030_info;
} else if (val == 0x32) {
twl = &twl6032_info;
} else {
puts("twl6030_init_battery_charging(): unsupported chip type\n");
return;
}
/* Enable VBAT measurement */
twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
if (twl->chip_type == chip_TWL6030) {
twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
TWL6030_GPADC_CTRL,
GPADC_CTRL_SCALER_DIV4);
} else {
twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
TWL6032_GPADC_CTRL2,
GPADC_CTRL2_CH18_SCALER_EN);
}
/* Enable GPADC module */
ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS);
@ -146,10 +203,10 @@ void twl6030_init_battery_charging(void)
printf("Main battery voltage too low!\n");
/* Check for the presence of USB charger */
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1);
twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &val);
/* check for battery presence indirectly via Fuel gauge */
if ((stat1 & VBUS_DET) && (battery_volt < 3300))
if ((val & VBUS_DET) && (battery_volt < 3300))
twl6030_start_usb_charging();
return;

57
drivers/usb/host/ehci-omap.c
View File

@ -28,21 +28,48 @@ static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
static int omap_uhh_reset(void)
{
/*
* Soft resetting the UHH module causes instability issues on
* all OMAPs so we just avoid it.
*
* See OMAP36xx Errata
* i571: USB host EHCI may stall when entering smart-standby mode
* i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
*
* On OMAP4/5, soft-resetting the UHH module will put it into
* Smart-Idle mode and lead to a deadlock.
*
* On OMAP3, this doesn't seem to be the case but still instabilities
* are observed on beagle (3530 ES1.0) if soft-reset is used.
* e.g. NFS root failures with Linux kernel.
*/
int timeout = 0;
u32 rev;
rev = readl(&uhh->rev);
/* Soft RESET */
writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
switch (rev) {
case OMAP_USBHS_REV1:
/* Wait for soft RESET to complete */
while (!(readl(&uhh->syss) & 0x1)) {
if (timeout > 100) {
printf("%s: RESET timeout\n", __func__);
return -1;
}
udelay(10);
timeout++;
}
/* Set No-Idle, No-Standby */
writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
break;
default: /* Rev. 2 onwards */
udelay(2); /* Need to wait before accessing SYSCONFIG back */
/* Wait for soft RESET to complete */
while ((readl(&uhh->sysc) & 0x1)) {
if (timeout > 100) {
printf("%s: RESET timeout\n", __func__);
return -1;
}
udelay(10);
timeout++;
}
writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
break;
}
return 0;
}

9
include/configs/am335x_evm.h
View File

@ -42,12 +42,11 @@
"dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandsrcaddr=0x280000\0" \
"nandboot=echo Booting from nand ...; " \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
"bootz ${loadaddr}\0" \
"nandimgsize=0x500000\0"
"nand read ${fdtaddr} u-boot-spl-os; " \
"nand read ${loadaddr} kernel; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
#else
#define NANDARGS ""
#endif

14
include/configs/am3517_evm.h
View File

@ -141,8 +141,18 @@
#define CONFIG_SYS_I2C_SLAVE 1
#define CONFIG_DRIVER_OMAP34XX_I2C 1
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
* Ethernet
*/
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
/*
* Board NAND Info.
*/

182
include/configs/cm_t335.h Normal file
View File

@ -0,0 +1,182 @@
/*
* Config file for Compulab CM-T335 board
*
* Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
*
* Author: Ilya Ledvich <ilya@compulab.co.il>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_CM_T335_H
#define __CONFIG_CM_T335_H
#define CONFIG_CM_T335
#define CONFIG_NAND
#include <configs/ti_am335x_common.h>
#undef CONFIG_BOARD_LATE_INIT
#undef CONFIG_SPI
#undef CONFIG_OMAP3_SPI
#undef CONFIG_CMD_SPI
#undef CONFIG_SPL_OS_BOOT
#undef CONFIG_BOOTCOUNT_LIMIT
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#undef CONFIG_MAX_RAM_BANK_SIZE
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT "CM-T335 # "
#define CONFIG_OMAP_COMMON
#define MACH_TYPE_CM_T335 4586 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335
/* Clock Defines */
#define V_OSCK 25000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
#ifndef CONFIG_SPL_BUILD
#define MMCARGS \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
"mmcrootfstype=ext4\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0"
#define NANDARGS \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"nandroot=ubi0:rootfs rw\0" \
"nandrootfstype=ubifs\0" \
"nandargs=setenv bootargs console=${console} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype} " \
"ubi.mtd=${rootfs_name}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nboot ${loadaddr} nand0 900000; " \
"bootm ${loadaddr}\0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=82000000\0" \
"console=ttyO0,115200n8\0" \
"rootfs_name=rootfs\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
MMCARGS \
NANDARGS
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
#endif /* CONFIG_SPL_BUILD */
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD "no"
/* Serial console configuration */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SERIAL1 1 /* UART0 */
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_BAUDRATE 115200
/* I2C Configuration */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
/* SPL */
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_ATHEROS
/* NAND support */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#undef CONFIG_SYS_NAND_U_BOOT_OFFS
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
#define CONFIG_CMD_NAND
#define GPMC_NAND_ECC_LP_x8_LAYOUT
#define MTDIDS_DEFAULT "nand0=nand"
#define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
"1m(u-boot),1m(u-boot-env)," \
"1m(dtb),4m(splash)," \
"6m(kernel),-(rootfs)"
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* GPIO pin + bank to pin ID mapping */
#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin)
/* Status LED */
#define CONFIG_STATUS_LED
#define CONFIG_GPIO_LED
#define CONFIG_BOARD_SPECIFIC_LED
#define STATUS_LED_BIT GPIO_PIN(2, 0)
/* Status LED polarity is inversed, so init it in the "off" state */
#define STATUS_LED_STATE STATUS_LED_OFF
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
#define STATUS_LED_BOOT 0
#ifndef CONFIG_SPL_BUILD
/*
* Enable PCA9555 at I2C0-0x26.
* First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
*/
#define CONFIG_PCA953X
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} }
#endif /* CONFIG_SPL_BUILD */
#endif /* __CONFIG_CM_T335_H */

11
include/configs/dra7xx_evm.h
View File

@ -83,4 +83,15 @@
#define CONFIG_OMAP_USB_PHY
#define CONFIG_OMAP_USB2PHY2_HOST
/* SATA */
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_CMD_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#endif /* __CONFIG_DRA7XX_EVM_H */

3
include/configs/omap3_beagle.h
View File

@ -118,9 +118,6 @@
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_SMSC95XX

3
include/configs/omap4_panda.h
View File

@ -36,9 +36,6 @@
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
#include <configs/omap4_common.h>
#define CONFIG_CMD_NET

10
include/configs/omap5_uevm.h
View File

@ -69,4 +69,14 @@
/* Max time to hold reset on this board, see doc/README.omap-reset-time */
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_CMD_SCSI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#endif /* __CONFIG_OMAP5_EVM_H */

5
include/configs/siemens-am33x-common.h
View File

@ -487,4 +487,9 @@
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_ENV
/* Enable Device-Tree (FDT) support */
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_FDT
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */

38
include/twl6030.h
View File

@ -110,9 +110,47 @@
#define CTRL_P2_EOCP2 (1 << 1)
#define CTRL_P2_BUSY (1 << 0)
#define TWL6032_CTRL_P1 0x36
#define CTRL_P1_SP1 (1 << 3)
#define GPCH0_LSB 0x57
#define GPCH0_MSB 0x58
#define TWL6032_GPCH0_LSB 0x3b
#define TWL6032_GPSELECT_ISB 0x35
#define USB_PRODUCT_ID_LSB 0x02
#define TWL6030_GPADC_VBAT_CHNL 0x07
#define TWL6032_GPADC_VBAT_CHNL 0x12
#define TWL6030_GPADC_CTRL 0x2e
#define TWL6032_GPADC_CTRL2 0x2f
#define GPADC_CTRL2_CH18_SCALER_EN (1 << 2)
#define GPADC_CTRL_SCALER_DIV4 (1 << 3)
#define TWL6030_VBAT_MULT 40 * 1000
#define TWL6032_VBAT_MULT 25 * 1000
#define TWL6030_VBAT_SHIFT (10 + 3)
#define TWL6032_VBAT_SHIFT (12 + 2)
enum twl603x_chip_type{
chip_TWL6030,
chip_TWL6032,
chip_TWL603X_cnt
};
struct twl6030_data{
u8 chip_type;
u8 adc_rbase;
u8 adc_ctrl;
u8 adc_enable;
int vbat_mult;
int vbat_shift;
};
/* Functions to read and write from TWL6030 */
static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
{