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MIPS: mips32/cache.S: save return address in t9 register

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Synchronize the code with mips64/cache.S, in order to
allow further unifications.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
This commit is contained in:
Gabor Juhos 2013-06-13 12:59:34 +02:00 committed by Tom Rini
parent d707e5b713
commit c325916563
1 changed files with 1 additions and 1 deletions
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2
arch/mips/cpu/mips32/cache.S
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@ -18,7 +18,7 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
#define RA t8
#define RA t9
/*
* 16kB is the maximum size of instruction and data caches on MIPS 4K,