OMAP3: mt_ventoux: updated timing for FPGA
Fix chipselect timing for FPGA Signed-off-by: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
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@ -31,12 +31,11 @@ const omap3_sysinfo sysinfo = {
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/* FPGA CS1 configuration */
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#define FPGA_GPMC_CONFIG1 0x00001200
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#define FPGA_GPMC_CONFIG2 0x00111a00
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#define FPGA_GPMC_CONFIG3 0x00010100
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#define FPGA_GPMC_CONFIG4 0x06041a04
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#define FPGA_GPMC_CONFIG5 0x0019101a
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#define FPGA_GPMC_CONFIG6 0x890503c0
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#define FPGA_GPMC_CONFIG7 0x00000860
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#define FPGA_GPMC_CONFIG2 0x00161f00
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#define FPGA_GPMC_CONFIG3 0x00040400
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#define FPGA_GPMC_CONFIG4 0x120c1f08
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#define FPGA_GPMC_CONFIG5 0x001e161f
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#define FPGA_GPMC_CONFIG6 0x96080fcf
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#define FPGA_BASE_ADDR 0x20000000
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