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86xx: Convert all fsl_pci_init users to new APIs

Browse Source 
Converted MPC8610HCPD, MPC8641HPCN, and SBC8641D to use
fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup().

With these changes the board code is a bit smaller and we get dma-ranges
set in the device tree for these boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Acked-by: Jon Loeliger <jdl@freescale.com>
This commit is contained in:
Kumar Gala 2008-10-22 14:38:55 -05:00 committed by Andrew Fleming-AFLEMING
parent 2dba0dea98
commit c2083e0e11
6 changed files with 59 additions and 142 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

78
board/freescale/mpc8610hpcd/mpc8610hpcd.c
View File

@ -240,6 +240,9 @@ static struct pci_controller pcie2_hose;
int first_free_busno = 0;
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
@ -256,11 +259,11 @@ void pci_init_board(void)
#ifdef CONFIG_PCIE1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie1_hose;
int pcie_configured = (io_sel == 1) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
(host_agent == 5);
struct pci_region *r = hose->regions;
if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
@ -270,27 +273,23 @@ void pci_init_board(void)
pci->pme_msg_det = 0xffffffff;
/* inbound */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(hose->regions + 1,
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
@ -313,8 +312,8 @@ void pci_init_board(void)
#ifdef CONFIG_PCIE2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pcie2_hose;
struct pci_region *r = hose->regions;
int pcie_configured = (io_sel == 0) || (io_sel == 4);
int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
@ -329,27 +328,23 @@ void pci_init_board(void)
pci->pme_msg_det = 0xffffffff;
/* inbound */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(hose->regions + 1,
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int)&pci->cfg_addr,
@ -371,9 +366,9 @@ void pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
int pci_agent = (host_agent >= 4) && (host_agent <= 6);
struct pci_region *r = hose->regions;
if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
printf(" PCI connected to PCI slots as %s" \
@ -382,27 +377,23 @@ void pci_init_board(void)
(uint)pci);
/* inbound */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(hose->regions + 1,
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr,
@ -422,12 +413,12 @@ void pci_init_board(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose);
void
ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", bd->bi_busfreq / 4, 1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@ -442,36 +433,15 @@ ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI1
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCIE1
path = fdt_getprop(blob, node, "pci1", NULL);
if (path) {
tmp[1] = pcie1_hose.last_busno
- pcie1_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
#ifdef CONFIG_PCIE2
path = fdt_getprop(blob, node, "pci2", NULL);
if (path) {
tmp[1] = pcie2_hose.last_busno
- pcie2_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
#endif
}
}
#endif

53
board/freescale/mpc8641hpcn/mpc8641hpcn.c
View File

@ -161,6 +161,8 @@ static struct pci_controller pci2_hose;
int first_free_busno = 0;
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);
void pci_init_board(void)
{
@ -173,8 +175,9 @@ void pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_region *r = hose->regions;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
@ -193,27 +196,23 @@ void pci_init_board(void)
debug("\n");
/* inbound */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(hose->regions + 1,
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@ -242,32 +241,27 @@ void pci_init_board(void)
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
struct pci_region *r = hose->regions;
/* inbound */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(hose->regions + 1,
pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@ -286,33 +280,20 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose);
void
ft_board_setup(void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
ft_cpu_setup(blob, bd);
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI1
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
path = fdt_getprop(blob, node, "pci1", NULL);
if (path) {
tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
}
}
#endif

55
board/sbc8641d/sbc8641d.c
View File

@ -220,6 +220,9 @@ static struct pci_controller pci2_hose;
int first_free_busno = 0;
extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
extern void fsl_pci_init(struct pci_controller *hose);
void pci_init_board(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
@ -231,8 +234,8 @@ void pci_init_board(void)
#ifdef CONFIG_PCI1
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci1_hose;
struct pci_region *r = hose->regions;
#ifdef DEBUG
uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA)
>> MPC8641_PORBMSR_HA_SHIFT;
@ -251,27 +254,23 @@ void pci_init_board(void)
debug("\n");
/* inbound */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(hose->regions + 1,
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@ -293,32 +292,28 @@ void pci_init_board(void)
#ifdef CONFIG_PCI2
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
extern void fsl_pci_init(struct pci_controller *hose);
struct pci_controller *hose = &pci2_hose;
struct pci_region *r = hose->regions;
/* inbound */
pci_set_region(hose->regions + 0,
CONFIG_SYS_PCI_MEMORY_BUS,
CONFIG_SYS_PCI_MEMORY_PHYS,
CONFIG_SYS_PCI_MEMORY_SIZE,
PCI_REGION_MEM | PCI_REGION_MEMORY);
r += fsl_pci_setup_inbound_windows(r);
/* outbound memory */
pci_set_region(hose->regions + 1,
pci_set_region(r++,
CONFIG_SYS_PCI2_MEM_BASE,
CONFIG_SYS_PCI2_MEM_PHYS,
CONFIG_SYS_PCI2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(hose->regions + 2,
pci_set_region(r++,
CONFIG_SYS_PCI2_IO_BASE,
CONFIG_SYS_PCI2_IO_PHYS,
CONFIG_SYS_PCI2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = 3;
hose->region_count = r - hose->regions;
hose->first_busno=first_free_busno;
pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
@ -337,33 +332,19 @@ void pci_init_board(void)
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
struct pci_controller *hose);
void
ft_board_setup (void *blob, bd_t *bd)
void ft_board_setup (void *blob, bd_t *bd)
{
int node, tmp[2];
const char *path;
ft_cpu_setup(blob, bd);
node = fdt_path_offset(blob, "/aliases");
tmp[0] = 0;
if (node >= 0) {
#ifdef CONFIG_PCI1
path = fdt_getprop(blob, node, "pci0", NULL);
if (path) {
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
#endif
#ifdef CONFIG_PCI2
path = fdt_getprop(blob, node, "pci1", NULL);
if (path) {
tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
}
ft_fsl_pci_setup(blob, "pci1", &pci2_hose);
#endif
}
}
#endif

5
include/configs/MPC8610HPCD.h
View File

@ -279,11 +279,6 @@
#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
/* PCI view of System Memory */
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
#define _IO_BASE 0x00000000

5
include/configs/MPC8641HPCN.h
View File

@ -305,11 +305,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
/* PCI view of System Memory */
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
/* For RTL8139 */
#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
#define _IO_BASE 0x00000000

5
include/configs/sbc8641d.h
View File

@ -308,11 +308,6 @@
#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
/* PCI view of System Memory */
#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */