arm: kirkwood: Dockstar : Add DM Ethernet

The Dockstar board has the network chip Marvell 88E1116R. Convert to
Ethernet driver model, and use uclass mvgbe and the compatible driver
M88E1118R to bring up Ethernet.

- Add CONFIG_DM_ETH and associated configs.
- Add board_eth_init() to use uclass mvgbe to bring up the network.
And remove ad-hoc code.
- Add CONFIG_PHY_MARVELL to properly configure the network.
- Currently, CONFIG_RESET_PHY_R symbol is used in
arch/arm/mach-kirkwood/include/mach/config.h for all Kirkwood
boards with mv8831116 PHY, with each board defines the function
reset_phy(). Undefine it for this board.
- Miscellaneous changes: Move constants to .c file and remove
header file board/Seagate/dockstar/dockstar.h, use
CONFIG_SYS_THUMB_BUILD to keep u-boot image
under 512K, add CONFIG_HUSH_PARSER, use BIT macro, and cleanup comments.

- Note: This patch is a RESEND for a previous patch:
https://patchwork.ozlabs.org/project/uboot/patch/20210812051854.1340-2-mibodhi@gmail.com/

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tony Dinh 2022-02-03 14:32:29 -08:00 committed by Stefan Roese
parent ba4e6f8a5e
commit c153576d8d
4 changed files with 30 additions and 84 deletions

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@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.c originally written by
@ -11,18 +12,22 @@
#include <common.h>
#include <bootstage.h>
#include <init.h>
#include <miiphy.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/arch/cpu.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include "dockstar.h"
#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
#define DOCKSTAR_OE_LOW (~(0))
#define DOCKSTAR_OE_HIGH (~(0))
#define DOCKSTAR_OE_VAL_LOW BIT(29) /* USB_PWEN low */
#define DOCKSTAR_OE_VAL_HIGH BIT(17) /* LED pin high */
int board_early_init_f(void)
{
/*
@ -92,6 +97,11 @@ int board_early_init_f(void)
return 0;
}
int board_eth_init(struct bd_info *bis)
{
return cpu_eth_init(bis);
}
int board_init(void)
{
/*
@ -105,53 +115,21 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
u16 reg;
u16 devadr;
char *name = "egiga0";
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
printf("Err..%s could not read PHY dev address\n",
__FUNCTION__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */
#if CONFIG_IS_ENABLED(BOOTSTAGE)
#define GREEN_LED (1 << 14)
#define ORANGE_LED (1 << 15)
#define GREEN_LED BIT(14)
#define ORANGE_LED BIT(15)
#define BOTH_LEDS (GREEN_LED | ORANGE_LED)
#define NEITHER_LED 0
static void set_leds(u32 leds, u32 blinking)
{
struct kwgpio_registers *r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
u32 oe = readl(&r->oe) | BOTH_LEDS;
u32 oe;
u32 bl;
oe = readl(&r->oe) | BOTH_LEDS;
writel(oe & ~leds, &r->oe); /* active low */
u32 bl = readl(&r->blink_en) & ~BOTH_LEDS;
bl = readl(&r->blink_en) & ~BOTH_LEDS;
writel(bl | blinking, &r->blink_en);
}

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@ -1,27 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.h originally written by
* Prafulla Wadaskar <prafulla@marvell.com>
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
*/
#ifndef __DOCKSTAR_H
#define __DOCKSTAR_H
#define DOCKSTAR_OE_LOW (~(0))
#define DOCKSTAR_OE_HIGH (~(0))
#define DOCKSTAR_OE_VAL_LOW (1 << 29) /* USB_PWEN low */
#define DOCKSTAR_OE_VAL_HIGH (1 << 17) /* LED pin high */
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
#endif /* __DOCKSTAR_H */

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@ -2,6 +2,7 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_KIRKWOOD=y
CONFIG_SYS_KWD_CONFIG="board/Seagate/dockstar/kwbimage.cfg"
CONFIG_SYS_TEXT_BASE=0x600000
@ -18,6 +19,7 @@ CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs ${console} ${mtdparts} ${bootargs_root}; ubi part root; ubifsmount ubi:root; ubifsload 0x800000 ${kernel}; ubifsload 0x1100000 ${initrd}; bootm 0x800000 0x1100000"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="DockStar> "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
@ -36,11 +38,14 @@ CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_MVGBE=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y

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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2022 Tony Dinh <mibodhi@gmail.com>
* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
*
* Based on sheevaplug.h originally written by
@ -17,14 +18,6 @@
*/
#include "mv-common.h"
/*
* Environment variables configurations
*/
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
/*
* Default environment variables
*/
@ -32,7 +25,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=console=ttyS0,115200\0" \
"mtdids=nand0=orion_nand\0" \
"mtdparts="CONFIG_MTDPARTS_DEFAULT \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT \
"kernel=/boot/uImage\0" \
"initrd=/boot/uInitrd\0" \
"bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0"
@ -40,13 +33,10 @@
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
#define CONFIG_PHY_BASE_ADR 0
#endif /* CONFIG_CMD_NET */
/*
* File system
*/
#ifdef CONFIG_RESET_PHY_R
#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */
#endif
#endif /* _CONFIG_DOCKSTAR_H */