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board: ti: am654: select SYS_DISABLE_DCACHE_OPS for arm64 build

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AM654 SoC is IO coherent wrt A53 cores, therefore enable
SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53
SPL/U-Boot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Vignesh Raghavendra 2019-04-22 21:43:33 +05:30 committed by Tom Rini
parent add4967124
commit c14f3c3111
1 changed files with 1 additions and 0 deletions
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board/ti/am65x/Kconfig
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@ -11,6 +11,7 @@ config TARGET_AM654_A53_EVM
bool "TI K3 based AM654 EVM running on A53"
select ARM64
select SOC_K3_AM6
select SYS_DISABLE_DCACHE_OPS
config TARGET_AM654_R5_EVM
bool "TI K3 based AM654 EVM running on R5"