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sh: Add support Renesas Solutions R7780MP

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Renesas Solutions R7780MP is a reference board on SH7780.
This board has serial, 10/100 base Ethernet deivice, CF slot
and VGA devices. This board can set extension board.
Extension board has 10/100/1000 base Ethernet device, PCI slot,
S-ATA, iDVR slot.

Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Yusuke Goda 2008-03-11 12:55:12 +09:00 committed by Nobuhiro Iwamatsu
parent 1a2334a4eb
commit c133c1fb0b
10 changed files with 959 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAKEALL
View File

@ -700,6 +700,7 @@ LIST_sh4=" \
ms7750se \
ms7722se \
Migo-R \
r7780mp \
"
LIST_sh3=" \

5
Makefile
View File

@ -2857,6 +2857,11 @@ MigoR_config : unconfig
@echo "#define CONFIG_MIGO_R 1" >> include/config.h
@./mkconfig -a $(@:_config=) sh sh4 MigoR
r7780mp_config: unconfig
@ >include/config.h
@echo "#define CONFIG_R7780MP 1" >> include/config.h
@./mkconfig -a $(@:_config=) sh sh4 r7780mp
#########################################################################
#########################################################################
#########################################################################

44
board/r7780mp/Makefile Normal file
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@ -0,0 +1,44 @@
#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
#
# board/r7780mp/Makefile
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := r7780mp.o
SOBJS := lowlevel_init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

27
board/r7780mp/config.mk Normal file
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@ -0,0 +1,27 @@
#
# Copyright (C) 2007,2008 Nobuhiro Iwamatsu
#
# board/r77870mp/config.mk
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# TEXT_BASE refers to image _after_ relocation.
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
TEXT_BASE = 0x0FFC0000

428
board/r7780mp/lowlevel_init.S Normal file
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@ -0,0 +1,428 @@
/*
* Copyright (C) 2007,2008 Nobuhiro Iwamatsu
*
* u-boot/board/r7780mp/lowlevel_init.S
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/processor.h>
/*
* Board specific low level init code, called _very_ early in the
* startup sequence. Relocation to SDRAM has not happened yet, no
* stack is available, bss section has not been initialised, etc.
*
* (Note: As no stack is available, no subroutines can be called...).
*/
.global lowlevel_init
.text
.align 2
lowlevel_init:
mov.l CCR_A, r1 /* Address of Cache Control Register */
mov.l CCR_D, r0 /* Instruction Cache Invalidate */
mov.l r0, @r1
mov.l FRQCR_A, r1 /* Frequency control register */
mov.l FRQCR_D, r0
mov.l r0, @r1
/* pin_multi_setting */
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR1,r0
mov.l r0,@r1
mov.l BBG_PMSR1_A,r1
mov.l BBG_PMSR1_D,r0
mov.l r0,@r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR2,r0
mov.l r0,@r1
mov.l BBG_PMSR2_A,r1
mov.l BBG_PMSR2_D,r0
mov.l r0,@r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR3,r0
mov.l r0,@r1
mov.l BBG_PMSR3_A,r1
mov.l BBG_PMSR3_D,r0
mov.l r0,@r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSR4,r0
mov.l r0,@r1
mov.l BBG_PMSR4_A,r1
mov.l BBG_PMSR4_D,r0
mov.l r0,@r1
mov.l BBG_PMMR_A,r1
mov.l BBG_PMMR_D_PMSRG,r0
mov.l r0,@r1
mov.l BBG_PMSRG_A,r1
mov.l BBG_PMSRG_D,r0
mov.l r0,@r1
/* cpg_setting */
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.l r0,@r1
mov.l DLLCSR_A,r1
mov.l DLLCSR_D,r0
mov.l r0,@r1
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
/* wait 200us */
mov.l REPEAT0_R3,r3
mov #0,r2
repeat0:
add #1,r2
cmp/hs r3,r2
bf repeat0
nop
/* bsc_setting */
mov.l MMSELR_A,r1
mov.l MMSELR_D,r0
mov.l r0,@r1
mov.l BCR_A,r1
mov.l BCR_D,r0
mov.l r0,@r1
mov.l CS0BCR_A,r1
mov.l CS0BCR_D,r0
mov.l r0,@r1
mov.l CS1BCR_A,r1
mov.l CS1BCR_D,r0
mov.l r0,@r1
mov.l CS2BCR_A,r1
mov.l CS2BCR_D,r0
mov.l r0,@r1
mov.l CS4BCR_A,r1
mov.l CS4BCR_D,r0
mov.l r0,@r1
mov.l CS5BCR_A,r1
mov.l CS5BCR_D,r0
mov.l r0,@r1
mov.l CS6BCR_A,r1
mov.l CS6BCR_D,r0
mov.l r0,@r1
mov.l CS0WCR_A,r1
mov.l CS0WCR_D,r0
mov.l r0,@r1
mov.l CS1WCR_A,r1
mov.l CS1WCR_D,r0
mov.l r0,@r1
mov.l CS2WCR_A,r1
mov.l CS2WCR_D,r0
mov.l r0,@r1
mov.l CS4WCR_A,r1
mov.l CS4WCR_D,r0
mov.l r0,@r1
mov.l CS5WCR_A,r1
mov.l CS5WCR_D,r0
mov.l r0,@r1
mov.l CS6WCR_A,r1
mov.l CS6WCR_D,r0
mov.l r0,@r1
mov.l CS5PCR_A,r1
mov.l CS5PCR_D,r0
mov.l r0,@r1
mov.l CS6PCR_A,r1
mov.l CS6PCR_D,r0
mov.l r0,@r1
/* ddr_setting */
/* wait 200us */
mov.l REPEAT0_R3,r3
mov #0,r2
repeat1:
add #1,r2
cmp/hs r3,r2
bf repeat1
nop
mov.l MIM_U_A,r0
mov.l MIM_U_D,r1
synco
mov.l r1,@r0
synco
mov.l MIM_L_A,r0
mov.l MIM_L_D0,r1
synco
mov.l r1,@r0
synco
mov.l STR_L_A,r0
mov.l STR_L_D,r1
synco
mov.l r1,@r0
synco
mov.l SDR_L_A,r0
mov.l SDR_L_D,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D0,r1
synco
mov.l r1,@r0
synco
mov.l SCR_L_A,r0
mov.l SCR_L_D1,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
mov.l EMRS_A,r0
mov.l EMRS_D,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
mov.l MRS1_A,r0
mov.l MRS1_D,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D2,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D3,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D4,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
mov.l MRS2_A,r0
mov.l MRS2_D,r1
synco
mov.l r1,@r0
synco
nop
nop
nop
mov.l SCR_L_A,r0
mov.l SCR_L_D5,r1
synco
mov.l r1,@r0
synco
/* wait 200us */
mov.l REPEAT0_R1,r3
mov #0,r2
repeat2:
add #1,r2
cmp/hs r3,r2
bf repeat2
synco
mov.l MIM_L_A,r0
mov.l MIM_L_D1,r1
synco
mov.l r1,@r0
synco
rts
nop
.align 4
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA507
RWTCNT_D: .word 0x5A00
BBG_PMMR_A: .long 0xFF800010
BBG_PMSR1_A: .long 0xFF800014
BBG_PMSR2_A: .long 0xFF800018
BBG_PMSR3_A: .long 0xFF80001C
BBG_PMSR4_A: .long 0xFF800020
BBG_PMSRG_A: .long 0xFF800024
BBG_PMMR_D_PMSR1: .long 0xffffbffd
BBG_PMSR1_D: .long 0x00004002
BBG_PMMR_D_PMSR2: .long 0xfc21a7ff
BBG_PMSR2_D: .long 0x03de5800
BBG_PMMR_D_PMSR3: .long 0xfffffff8
BBG_PMSR3_D: .long 0x00000007
BBG_PMMR_D_PMSR4: .long 0xdffdfff9
BBG_PMSR4_D: .long 0x20020006
BBG_PMMR_D_PMSRG: .long 0xffffffff
BBG_PMSRG_D: .long 0x00000000
FRQCR_A: .long FRQCR
DLLCSR_A: .long 0xffc40010
FRQCR_D: .long 0x40233035
DLLCSR_D: .long 0x00000000
/* for DDR-SDRAM */
MIM_U_A: .long MIM_1
MIM_L_A: .long MIM_2
SCR_U_A: .long SCR_1
SCR_L_A: .long SCR_2
STR_U_A: .long STR_1
STR_L_A: .long STR_2
SDR_U_A: .long SDR_1
SDR_L_A: .long SDR_2
EMRS_A: .long 0xFEC02000
MRS1_A: .long 0xFEC00B08
MRS2_A: .long 0xFEC00308
MIM_U_D: .long 0x00004000
MIM_L_D0: .long 0x03e80009
MIM_L_D1: .long 0x03e80209
SCR_L_D0: .long 0x3
SCR_L_D1: .long 0x2
SCR_L_D2: .long 0x2
SCR_L_D3: .long 0x4
SCR_L_D4: .long 0x4
SCR_L_D5: .long 0x0
STR_L_D: .long 0x000f0000
SDR_L_D: .long 0x00000400
EMRS_D: .long 0x0
MRS1_D: .long 0x0
MRS2_D: .long 0x0
/* Cache Controller */
CCR_A: .long CCR
MMUCR_A: .long MMUCR
RWTCNT_A: .long WTCNT
CCR_D: .long 0x0000090b
CCR_D_2: .long 0x00000103
MMUCR_D: .long 0x00000004
MSTPCR0_D: .long 0x00001001
MSTPCR2_D: .long 0xffffffff
/* local Bus State Controller */
MMSELR_A: .long MMSELR
BCR_A: .long BCR
CS0BCR_A: .long CS0BCR
CS1BCR_A: .long CS1BCR
CS2BCR_A: .long CS2BCR
CS4BCR_A: .long CS4BCR
CS5BCR_A: .long CS5BCR
CS6BCR_A: .long CS6BCR
CS0WCR_A: .long CS0WCR
CS1WCR_A: .long CS1WCR
CS2WCR_A: .long CS2WCR
CS4WCR_A: .long CS4WCR
CS5WCR_A: .long CS5WCR
CS6WCR_A: .long CS6WCR
CS5PCR_A: .long CS5PCR
CS6PCR_A: .long CS6PCR
MMSELR_D: .long 0xA5A50003
BCR_D: .long 0x00000000
CS0BCR_D: .long 0x77777770
CS1BCR_D: .long 0x77777670
CS2BCR_D: .long 0x77777770
CS4BCR_D: .long 0x77777770
CS5BCR_D: .long 0x77777670
CS6BCR_D: .long 0x77777770
CS0WCR_D: .long 0x00020006
CS1WCR_D: .long 0x00232304
CS2WCR_D: .long 0x7777770F
CS4WCR_D: .long 0x7777770F
CS5WCR_D: .long 0x00101006
CS6WCR_D: .long 0x77777703
CS5PCR_D: .long 0x77000000
CS6PCR_D: .long 0x77000000
REPEAT0_R3: .long 0x00002000
REPEAT0_R1: .long 0x0000200

84
board/r7780mp/r7780mp.c Normal file
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@ -0,0 +1,84 @@
/*
* Copyright (C) 2007 Nobuhiro Iwamatsu
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ide.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/pci.h>
#include "r7780mp.h"
int checkboard(void)
{
#if defined(CONFIG_R7780MP)
puts("BOARD: Renesas Solutions R7780MP\n");
#else
puts("BOARD: Renesas Solutions R7780RP\n");
#endif
return 0;
}
int board_init(void)
{
/* SCIF Enable */
*(vu_short*)PHCR = 0x0000;
/* Disable Control-C */
disable_ctrlc(1);
return 0;
}
int dram_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_memstart = CFG_SDRAM_BASE;
gd->bd->bi_memsize = CFG_SDRAM_SIZE;
printf("DRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
return 0;
}
void led_set_state (unsigned short value)
{
}
void ide_set_reset (int idereset)
{
/* if reset = 1 IDE reset will be asserted */
if (idereset){
(*(vu_short *)FPGA_CFCTL) = 0x432;
#if defined(CONFIG_R7780MP)
(*(vu_short *)FPGA_CFPOW) |= 0x01;
#else
(*(vu_short *)FPGA_CFPOW) |= 0x02;
#endif
(*(vu_short *)FPGA_CFCDINTCLR) = 0x01;
}
}
#if defined(CONFIG_PCI)
static struct pci_controller hose;
void pci_init_board(void)
{
pci_sh7780_init( &hose );
}
#endif

54
board/r7780mp/r7780mp.h Normal file
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@ -0,0 +1,54 @@
/*
* Copyright (C) 2007 Nobuhiro Iwamatsu
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* u-boot/board/r7780mp/r7780mp.h
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _BOARD_R7780MP_R7780MP_H_
#define _BOARD_R7780MP_R7780MP_H_
/* R7780MP's FPGA register map */
#define FPGA_BASE 0xa4000000
#define FPGA_IRLMSK (FPGA_BASE + 0x00)
#define FPGA_IRLMON (FPGA_BASE + 0x02)
#define FPGA_IRLPRI1 (FPGA_BASE + 0x04)
#define FPGA_IRLPRI2 (FPGA_BASE + 0x06)
#define FPGA_IRLPRI3 (FPGA_BASE + 0x08)
#define FPGA_IRLPRI4 (FPGA_BASE + 0x0A)
#define FPGA_RSTCTL (FPGA_BASE + 0x0C)
#define FPGA_PCIBD (FPGA_BASE + 0x0E)
#define FPGA_PCICD (FPGA_BASE + 0x10)
#define FPGA_EXTGIO (FPGA_BASE + 0x16)
#define FPGA_IVDRMON (FPGA_BASE + 0x18)
#define FPGA_IVDRCR (FPGA_BASE + 0x1A)
#define FPGA_OBLED (FPGA_BASE + 0x1C)
#define FPGA_OBSW (FPGA_BASE + 0x1E)
#define FPGA_TPCTL (FPGA_BASE + 0x100)
#define FPGA_TPDCKCTL (FPGA_BASE + 0x102)
#define FPGA_TPCLR (FPGA_BASE + 0x104)
#define FPGA_TPXPOS (FPGA_BASE + 0x106)
#define FPGA_TPYPOS (FPGA_BASE + 0x108)
#define FPGA_DBSW (FPGA_BASE + 0x200)
#define FPGA_VERSION (FPGA_BASE + 0x700)
#define FPGA_CFCTL (FPGA_BASE + 0x300)
#define FPGA_CFPOW (FPGA_BASE + 0x302)
#define FPGA_CFCDINTCLR (FPGA_BASE + 0x304)
#define FPGA_PMR (FPGA_BASE + 0x900)
#endif /* _BOARD_R7780RP_R7780RP_H_ */

105
board/r7780mp/u-boot.lds Normal file
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@ -0,0 +1,105 @@
/*
* Copyrigth (c) 2007,2008
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
/*
Base address of internal SDRAM is 0x0C000000.
Although size of SDRAM can be either 16 or 32 MBytes,
we assume 16 MBytes (ie ignore upper half if the full
32 MBytes is present).
NOTE: This address must match with the definition of
TEXT_BASE in config.mk (in this directory).
*/
. = 0x08000000 + (128*1024*1024) - (256*1024);
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
cpu/sh4/start.o (.text)
. = ALIGN(8192);
common/environment.o (.ppcenv)
. = ALIGN(8192);
common/environment.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(.rodata)
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}

51
doc/README.sh
View File

@ -1,6 +1,6 @@
U-Boot for Renesas SuperH
Last update 08/10/2007 by Nobuhiro Iwamatsu
Last update 01/18/2008 by Nobuhiro Iwamatsu
================================================================================
0. What's this?
@ -18,7 +18,19 @@ U-Boot for Renesas SuperH
2. Supported CPUs
2.1. Renesas SH7750/SH7750R
This CPU has the SH4 core.
2.2. Renesas SH7722
This CPU has the SH4AL-DSP core.
2.3. Renesas SH7720
This CPU has the SH3 core.
2.4. Renesas SH7710/SH7712
This CPU has the SH3-DSP core and Ethernet controller.
2.5. Renesas SH7780
This CPU has the SH4A core.
================================================================================
3. Supported Boards
@ -26,10 +38,42 @@ U-Boot for Renesas SuperH
3.1. Hitachi UL MS7750SE01/MS7750RSE01
Board specific code is in board/ms7750se
To use this board, type "make ms7750se_config".
Support devices are :
- SCIF
- SDRAM
- NOR Flash
- Marubun PCMCIA
3.2. Hitachi UL MS7722SE01
Board specific code is in board/ms7722se
To use this board, type "make ms7722se_config".
Support devices are :
- SCIF
- SDRAM
- NOR Flash
- Marubun PCMCIA
- SMC91x ethernet
3.2. Hitachi UL MS7720ERP01
Board specific code is in board/ms7720se
To use this board, type "make ms7720se_config".
Support devices are :
- SCIF
- SDRAM
- NOR Flash
- Marubun PCMCIA
3.3. Renesas R7780MP
Board specific code is in board/r7780mp
To use this board, type "make r7780mp_config".
Support devices are :
- SCIF
- DDR-SDRAM
- NOR Flash
- Compact Flash
- ASIX ethernet
- SH7780 PCI bridge
- RTL8110 ethernet
** README **
In SuperH, S-record and binary of made u-boot work on the memory.
@ -49,13 +93,12 @@ U-Boot for Renesas SuperH
5. Future
I plan to support the following CPUs and boards.
5.1. CPUs
- SH7710/SH7712 (SH3)
- SH7780(SH4)
- SH7751R(SH4)
- SH7785(SH4)
5.2. Boards
- Many boards ;-)
================================================================================
Copyright (c) 2007
Copyright (c) 2007,2008
Nobuhiro Iwamatsu <iwamatsu@nigaur.org>

164
include/configs/r7780mp.h Normal file
View File

@ -0,0 +1,164 @@
/*
* Configuation settings for the Renesas R7780MP board
*
* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyright (C) 2008 Yusuke Goda <goda.yusuke@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __R7780RP_H
#define __R7780RP_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4A 1
#define CONFIG_CPU_SH7780 1
#define CONFIG_R7780MP 1
#define __LITTLE_ENDIAN 1
/*
* Command line configuration.
*/
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_ENV
#define CONFIG_CMD_NFS
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION
#define CFG_SCIF_CONSOLE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_CONS_SCIF0 1
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTARGS "console=ttySC0,115200"
#define CONFIG_ENV_OVERWRITE 1
/* check for keypress on bootdelay==0 */
/*#define CONFIG_ZERO_BOOTDELAY_CHECK*/
/* Network setting */
#define CONFIG_NETMASK 255.0.0.0
#define CONFIG_IPADDR 10.0.192.82
#define CONFIG_SERVERIP 10.0.0.1
#define CONFIG_GATEWAYIP 10.0.0.1
#define CFG_SDRAM_BASE (0x08000000)
#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
#define CFG_LONGHELP
#define CFG_PROMPT "=> "
#define CFG_CBSIZE 256
#define CFG_PBSIZE 256
#define CFG_MAXARGS 16
#define CFG_BARGSIZE 512
/* List of legal baudrate settings for this board */
#define CFG_BAUDRATE_TABLE { 115200, 57600, 38400, 19200, 9600 }
#define CFG_MEMTEST_START (CFG_SDRAM_BASE)
#define CFG_MEMTEST_END (TEXT_BASE - 0x100000)
/* NOR Flash (S29PL127J60TFI130) */
#define CFG_FLASH_BASE (0xA0000000)
#define CFG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
#define CFG_MAX_FLASH_BANKS (2)
#define CFG_MAX_FLASH_SECT 270
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE,\
CFG_FLASH_BASE + 0x100000,\
CFG_FLASH_BASE + 0x400000,\
CFG_FLASH_BASE + 0x700000, }
#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 4 * 1024 * 1024)
/* Address of u-boot image in Flash */
#define CFG_MONITOR_BASE (CFG_FLASH_BASE)
#define CFG_MONITOR_LEN (112 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CFG_MALLOC_LEN (256 * 1024)
/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_SIZE (256)
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
#define CFG_RX_ETH_BUFFER (8)
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_DRIVER
#undef CFG_FLASH_CFI_BROKEN_TABLE
#undef CFG_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_EMPTY_INFO
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE (16 * 1024)
#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_FLASH_ERASE_TOUT 120000
#define CFG_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define TMU_CLK_DIVIDER 4
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
/* PCI Controller */
#if defined(CONFIG_CMD_PCI)
#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1
#define __io
#define __mem_pci
#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
#endif /* CONFIG_CMD_PCI */
#if defined(CONFIG_CMD_NET)
/* #define CONFIG_NET_MULTI
#define CONFIG_RTL8169 */
/* AX88696L Support(NE2000 base chip) */
#define CONFIG_DRIVER_NE2000
#define CONFIG_DRIVER_AX88796L
#define CONFIG_DRIVER_NE2000_BASE 0xA4100000
#endif
/* Compact flash Support */
#if defined(CONFIG_CMD_IDE)
#define CONFIG_IDE_RESET 1
#define CFG_PIO_MODE 1
#define CFG_IDE_MAXBUS 1 /* IDE bus */
#define CFG_IDE_MAXDEVICE 1
#define CFG_ATA_BASE_ADDR 0xb4000000
#define CFG_ATA_STRIDE 2 /* 1bit shift */
#define CFG_ATA_DATA_OFFSET 0x1000 /* data reg offset */
#define CFG_ATA_REG_OFFSET 0x1000 /* reg offset */
#define CFG_ATA_ALT_OFFSET 0x800 /* alternate register offset */
#endif /* CONFIG_CMD_IDE */
#endif /* __R7780RP_H */