Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
c08ba67722
@ -39,15 +39,8 @@
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tlbtab:
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tlbtab_start
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/*
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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#ifndef CONFIG_NAND_SPL
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tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
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#else
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tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
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#endif
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/* vxWorks needs this as first entry for the Machine Check interrupt */
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tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
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/* TLB-entry for DDR SDRAM (Up to 2GB) */
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#ifdef CONFIG_4xx_DCACHE
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@ -56,6 +49,18 @@ tlbtab:
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tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
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#endif
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/* TLB-entry for EBC */
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tlbentry( CFG_BCSR_BASE, SZ_256M, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
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/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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#ifndef CONFIG_NAND_SPL
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tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
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#else
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tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
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#endif
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#ifdef CFG_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
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@ -67,9 +72,6 @@ tlbtab:
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tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
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tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
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/* TLB-entry for EBC */
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tlbentry( CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
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/* TLB-entry for NAND */
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tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
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@ -106,5 +106,12 @@ long int initdram (int board_type)
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denali_core_search_data_eye();
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#endif
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/*
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* Clear possible errors resulting from data-eye-search.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return (CFG_MBYTES_SDRAM << 20);
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}
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@ -104,5 +104,12 @@ long int initdram (int board_type)
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denali_core_search_data_eye();
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#endif
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/*
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* Clear possible errors resulting from data-eye-search.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return (CFG_MBYTES_SDRAM << 20);
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}
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@ -233,78 +233,6 @@ int misc_init_r(void)
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reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
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mtdcr(plb4_acr, reg);
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/*
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* Reset Lime controller
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*/
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gpio_write_bit(CFG_GPIO_LIME_S, 1);
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udelay(500);
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gpio_write_bit(CFG_GPIO_LIME_RST, 1);
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/* Lime memory clock adjusted to 100MHz */
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out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
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/* Wait untill time expired. Because of requirements in lime manual */
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udelay(300);
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/* Write lime controller memory parameters */
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out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
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/*
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* Init display controller
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*/
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/* Setup dot clock (internal PLL, division rate 1/16) */
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out_be32((void *)0xc1fd0100, 0x00000f00);
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/* Lime L0 init (16 bpp, 640x480) */
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out_be32((void *)0xc1fd0020, 0x801401df);
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out_be32((void *)0xc1fd0024, 0x0);
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out_be32((void *)0xc1fd0028, 0x0);
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out_be32((void *)0xc1fd002c, 0x0);
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out_be32((void *)0xc1fd0110, 0x0);
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out_be32((void *)0xc1fd0114, 0x0);
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out_be32((void *)0xc1fd0118, 0x01df0280);
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/* Display timing init */
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out_be32((void *)0xc1fd0004, 0x031f0000);
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out_be32((void *)0xc1fd0008, 0x027f027f);
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out_be32((void *)0xc1fd000c, 0x015f028f);
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out_be32((void *)0xc1fd0010, 0x020c0000);
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out_be32((void *)0xc1fd0014, 0x01df01ea);
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out_be32((void *)0xc1fd0018, 0x0);
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out_be32((void *)0xc1fd001c, 0x01e00280);
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#if 1
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/*
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* Clear framebuffer using Lime's drawing engine
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* (draw blue rect. with white border around it)
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*/
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/* Setup mode and fbbase, xres, fg, bg */
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out_be32((void *)0xc1ff0420, 0x8300);
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out_be32((void *)0xc1ff0440, 0x0000);
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out_be32((void *)0xc1ff0444, 0x0280);
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out_be32((void *)0xc1ff0480, 0x7fff);
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out_be32((void *)0xc1ff0484, 0x0000);
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/* Reset clipping rectangle */
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out_be32((void *)0xc1ff0454, 0x0000);
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out_be32((void *)0xc1ff0458, 0x0280);
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out_be32((void *)0xc1ff045c, 0x0000);
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out_be32((void *)0xc1ff0460, 0x01e0);
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/* Draw white rect. */
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out_be32((void *)0xc1ff04a0, 0x09410000);
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out_be32((void *)0xc1ff04a0, 0x00000000);
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out_be32((void *)0xc1ff04a0, 0x01e00280);
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udelay(2000);
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/* Draw blue rect. */
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out_be32((void *)0xc1ff0480, 0x001f);
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out_be32((void *)0xc1ff04a0, 0x09410000);
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out_be32((void *)0xc1ff04a0, 0x00010001);
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out_be32((void *)0xc1ff04a0, 0x01de027e);
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#endif
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/* Display enable, L0 layer */
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out_be32((void *)0xc1fd0100, 0x80010f00);
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/* TFT-LCD enable - PWM duty, lamp on */
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out_be32((void *)0xc4000024, 0x64);
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out_be32((void *)0xc4000020, 0x701);
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/*
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* Init matrix keyboard
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*/
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@ -562,3 +490,88 @@ U_BOOT_CMD(
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"eepromwp- eeprom write protect off/on\n",
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"<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n"
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);
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#if defined(CONFIG_VIDEO)
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#include <video_fb.h>
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#include <mb862xx.h>
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extern GraphicDevice mb862xx;
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static const gdc_regs init_regs [] =
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{
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{0x0100, 0x00000f00},
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{0x0020, 0x801401df},
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{0x0024, 0x00000000},
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{0x0028, 0x00000000},
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{0x002c, 0x00000000},
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{0x0110, 0x00000000},
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{0x0114, 0x00000000},
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{0x0118, 0x01df0280},
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{0x0004, 0x031f0000},
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{0x0008, 0x027f027f},
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{0x000c, 0x015f028f},
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{0x0010, 0x020c0000},
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{0x0014, 0x01df01ea},
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{0x0018, 0x00000000},
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{0x001c, 0x01e00280},
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{0x0100, 0x80010f00},
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{0x0, 0x0}
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};
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const gdc_regs *board_get_regs (void)
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{
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return init_regs;
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}
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/* Returns Lime base address */
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unsigned int board_video_init (void)
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{
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/*
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* Reset Lime controller
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*/
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gpio_write_bit(CFG_GPIO_LIME_S, 1);
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udelay(500);
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gpio_write_bit(CFG_GPIO_LIME_RST, 1);
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/* Lime memory clock adjusted to 100MHz */
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out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
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/* Wait untill time expired. Because of requirements in lime manual */
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udelay(300);
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/* Write lime controller memory parameters */
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out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
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mb862xx.winSizeX = 640;
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mb862xx.winSizeY = 480;
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mb862xx.gdfBytesPP = 2;
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mb862xx.gdfIndex = GDF_15BIT_555RGB;
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return CFG_LIME_BASE_0;
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}
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void board_backlight_switch (int flag)
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{
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if (flag) {
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/* pwm duty, lamp on */
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out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x64);
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out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701);
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} else {
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/* lamp off */
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out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x00);
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out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x00);
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}
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}
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#if defined(CONFIG_CONSOLE_EXTRA_INFO)
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/*
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* Return text to be printed besides the logo.
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*/
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void video_get_info_str (int line_number, char *info)
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{
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if (line_number == 1) {
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strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
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} else {
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info [0] = '\0';
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}
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}
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#endif
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#endif /* CONFIG_VIDEO */
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@ -1700,6 +1700,7 @@ trap_reloc:
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rlwinm r8,r9,0,15,13
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rlwinm r8,r8,0,17,15
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mtmsr r8
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mfspr r8,dvlim
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addi r3,r0,0x0000
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mtspr dvlim,r3
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mfspr r3,ivpr
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@ -1714,6 +1715,7 @@ trap_reloc:
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..ag: dcbf r0,r3
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addi r3,r3,-32
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bdnz ..ag
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mtspr dvlim,r8
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sync
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mtmsr r9
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blr
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@ -41,7 +41,9 @@
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#define CONFIG_SYS_CLK_FREQ 33333400
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#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
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#define CONFIG_4xx_DCACHE /* enable dcache */
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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@ -272,6 +274,7 @@
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CFG_BOOTFILE \
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CFG_ROOTPATH \
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"netdev=eth0\0" \
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"ethrotate=no\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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@ -354,10 +357,6 @@
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#define CONFIG_CMD_SDRAM
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/* POST support */
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/* ethernet POST sometimes freezes the CPU.
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* So disable it for now until issue is solved
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*/
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#if 0
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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@ -366,15 +365,6 @@
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CFG_POST_FPU | \
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CFG_POST_ETHER | \
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CFG_POST_SPR)
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#else
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#define CONFIG_POST (CFG_POST_MEMORY | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_I2C | \
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CFG_POST_CACHE | \
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CFG_POST_FPU | \
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CFG_POST_SPR)
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#endif
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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@ -248,6 +248,18 @@
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 1
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/* Video console */
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MB862xx
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define VIDEO_FB_16BPP_PIXEL_SWAP
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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/* USB */
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#ifdef CONFIG_440EPX
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#define CONFIG_USB_OHCI
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@ -294,6 +306,10 @@
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_SDRAM
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#ifdef CONFIG_VIDEO
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#define CONFIG_CMD_BMP
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#endif
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#ifdef CONFIG_440EPX
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#define CONFIG_CMD_USB
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#endif
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@ -61,6 +61,7 @@
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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#define CFG_TLB_FOR_BOOT_FLASH 0x0003
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#define CFG_BOOT_BASE_ADDR 0xf0000000
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
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