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arm: mach-k3: Enable dcache in SPL

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Add support for enabling dcache already in SPL. It accelerates the boot
and resolves the risk to run into unaligned 64-bit accesses.

Based on original patch by Lokesh Vulta.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Jan Kiszka 2020-05-18 07:57:22 +02:00 committed by Lokesh Vutla
parent 6cfd09d4ed
commit c02712a748
5 changed files with 40 additions and 0 deletions
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1
arch/arm/mach-k3/am6_init.c
View File

@ -197,6 +197,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_dcache();
}
u32 spl_mmc_boot_mode(const u32 boot_device)

35
arch/arm/mach-k3/common.c
View File

@ -406,3 +406,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
}
}
}
void spl_enable_dcache(void)
{
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE;
dram_init_banksize();
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
ram_top += get_effective_memsize();
/* keep ram_top in the 32-bit address space */
if (ram_top >= 0x100000000)
ram_top = (phys_addr_t) 0x100000000;
gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
dcache_enable();
#endif
}
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
void spl_board_prepare_for_boot(void)
{
dcache_disable();
}
void spl_board_prepare_for_boot_linux(void)
{
dcache_disable();
}
#endif

1
arch/arm/mach-k3/common.h
View File

@ -27,3 +27,4 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size);
void start_non_linux_remote_cores(void);
int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr);
void k3_sysfw_print_ver(void);
void spl_enable_dcache(void);

1
arch/arm/mach-k3/j721e_init.c
View File

@ -221,6 +221,7 @@ void board_init_f(ulong dummy)
if (ret)
panic("DRAM init failed: %d\n", ret);
#endif
spl_enable_dcache();
}
u32 spl_mmc_boot_mode(const u32 boot_device)

2
board/ti/am65x/evm.c
View File

@ -69,11 +69,13 @@ int dram_init_banksize(void)
/* Bank 0 declares the memory available in the DDR low region */
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = 0x80000000;
gd->ram_size = 0x80000000;
#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR high region */
gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
gd->bd->bi_dram[1].size = 0x80000000;
gd->ram_size = 0x100000000;
#endif
return 0;