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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-net

Browse Source 
- DaVinci emac DM work
- NXP driver work
- macb updates for RISC-V
This commit is contained in:
Tom Rini 2019-07-25 15:02:36 -04:00
commit bfe28bc70f
63 changed files with 3076 additions and 463 deletions

14
arch/arm/Kconfig
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@ -1352,6 +1352,19 @@ config TARGET_LS1021ATWR
select SUPPORT_SPL
imply SCSI
config TARGET_LS1021ATSN
bool "Support ls1021atsn"
select ARCH_LS1021A
select ARCH_SUPPORT_PSCI
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select CPU_V7A
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select SUPPORT_SPL
imply SCSI
config TARGET_LS1021AIOT
bool "Support ls1021aiot"
select ARCH_LS1021A
@ -1745,6 +1758,7 @@ source "board/freescale/ls1028a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1021atsn/Kconfig"
source "board/freescale/ls1021aiot/Kconfig"
source "board/freescale/ls1046aqds/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"

2
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -296,7 +296,7 @@ int cpu_mmc_init(bd_t *bis)
int cpu_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
tsec_standard_init(bis);
#endif

10
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@ -16,12 +16,17 @@
#include <tsec.h>
#include <asm/arch/immap_ls102xa.h>
#include <fsl_sec.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
void ft_fixup_enet_phy_connect_type(void *fdt)
{
#ifdef CONFIG_DM_ETH
struct udevice *dev;
#else
struct eth_device *dev;
#endif
struct tsec_private *priv;
const char *enet_path, *phy_path;
char enet[16];
@ -29,7 +34,12 @@ void ft_fixup_enet_phy_connect_type(void *fdt)
int phy_node;
int i = 0;
uint32_t ph;
#ifdef CONFIG_DM_ETH
char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
"ethernet@2d90000" };
#else
char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
#endif
for (; i < ARRAY_SIZE(name); i++) {
dev = eth_get_dev_by_name(name[i]);

2
arch/arm/dts/Makefile
View File

@ -328,7 +328,7 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-qds-lpuart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \

13
arch/arm/dts/fsl-ls1028a-qds.dts
View File

@ -86,3 +86,16 @@
&usb2 {
status = "okay";
};
&enetc1 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&qds_phy0>;
};
&mdio0 {
status = "okay";
qds_phy0: phy@5 {
reg = <5>;
};
};

13
arch/arm/dts/fsl-ls1028a-rdb.dts
View File

@ -86,3 +86,16 @@
&usb2 {
status = "okay";
};
&enetc0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&rdb_phy0>;
};
&mdio0 {
status = "okay";
rdb_phy0: phy@2 {
reg = <2>;
};
};

24
arch/arm/dts/fsl-ls1028a.dtsi
View File

@ -117,6 +117,30 @@
#size-cells = <2>;
device_type = "pci";
ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
enetc0: pci@0,0 {
reg = <0x000000 0 0 0 0>;
status = "disabled";
};
enetc1: pci@0,1 {
reg = <0x000100 0 0 0 0>;
status = "disabled";
};
enetc2: pci@0,2 {
reg = <0x000200 0 0 0 0>;
status = "okay";
phy-mode = "internal";
};
mdio0: pci@0,3 {
#address-cells=<0>;
#size-cells=<1>;
reg = <0x000300 0 0 0 0>;
status = "disabled";
};
enetc6: pci@0,6 {
reg = <0x000600 0 0 0 0>;
status = "okay";
phy-mode = "internal";
};
};
i2c0: i2c@2000000 {

77
arch/arm/dts/ls1021a-tsn.dts Normal file
View File

@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2018 NXP Semiconductors
* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
*/
/dts-v1/;
#include "ls1021a.dtsi"
/ {
model = "NXP LS1021A-TSN Board";
aliases {
enet0-sgmii-phy = &sgmii_phy2;
enet1-sgmii-phy = &sgmii_phy1;
spi0 = &qspi;
spi1 = &dspi1;
};
};
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy2>;
phy-mode = "sgmii";
status = "okay";
};
&enet1 {
tbi-handle = <&tbi1>;
phy-handle = <&sgmii_phy1>;
phy-mode = "sgmii";
status = "okay";
};
&i2c0 {
status = "okay";
};
&mdio0 {
/* AR8031 */
sgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
/* AR8031 */
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
/* SGMII PCS for enet0 */
tbi0: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
&mdio1 {
/* SGMII PCS for enet1 */
tbi1: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
&qspi {
bus-num = <0>;
status = "okay";
flash@0 {
compatible = "spi-flash";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&uart0 {
status = "okay";
};

32
arch/arm/dts/ls1021a-twr.dtsi
View File

@ -51,6 +51,26 @@
};
};
&enet0 {
tbi-handle = <&tbi0>;
phy-handle = <&sgmii_phy2>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet1 {
tbi-handle = <&tbi1>;
phy-handle = <&sgmii_phy0>;
phy-connection-type = "sgmii";
status = "okay";
};
&enet2 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii-id";
status = "okay";
};
&i2c0 {
status = "okay";
};
@ -84,12 +104,24 @@
sgmii_phy0: ethernet-phy@0 {
reg = <0x0>;
};
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
/* SGMII PCS for enet0 */
tbi0: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";
};
};
&mdio1 {
/* SGMII PCS for enet1 */
tbi1: tbi-phy@1f {
reg = <0x1f>;
device_type = "tbi-phy";

30
arch/arm/dts/ls1021a.dtsi
View File

@ -350,12 +350,36 @@
<&platform_clk 1>;
};
enet0: ethernet@2d10000 {
compatible = "fsl,etsec2";
reg = <0x2d10000 0x1000>;
status = "disabled";
};
enet1: ethernet@2d50000 {
compatible = "fsl,etsec2";
reg = <0x2d50000 0x1000>;
status = "disabled";
};
enet2: ethernet@2d90000 {
compatible = "fsl,etsec2";
reg = <0x2d90000 0x1000>;
status = "disabled";
};
mdio0: mdio@2d24000 {
compatible = "gianfar";
device_type = "mdio";
compatible = "fsl,etsec2-mdio";
reg = <0x2d24000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
};
mdio1: mdio@2d64000 {
compatible = "fsl,etsec2-mdio";
reg = <0x2d64000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2d24000 0x4000>;
};
usb@8600000 {

13
arch/arm/mach-davinci/cpu.c
View File

@ -5,7 +5,6 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/hardware.h>
#include <asm/io.h>
@ -90,15 +89,3 @@ int set_cpu_clk_info(void)
gd->bd->bi_dsp_freq = 0;
return 0;
}
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(bd_t *bis)
{
#if defined(CONFIG_DRIVER_TI_EMAC)
davinci_emac_initialize();
#endif
return 0;
}

3
arch/arm/mach-omap2/omap3/emac.c
View File

@ -7,7 +7,6 @@
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/am35x_def.h>
@ -24,5 +23,5 @@ int cpu_eth_init(bd_t *bis)
reset &= ~CPGMACSS_SW_RST;
writel(reset, &am35x_scm_general_regs->ip_sw_reset);
return davinci_emac_initialize();
return 0;
}

6
board/davinci/da8xxevm/da850evm.c
View File

@ -13,7 +13,6 @@
#include <environment.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
@ -482,11 +481,6 @@ int board_eth_init(bd_t *bis)
if (rmii_hw_init())
printf("RMII hardware init failed!!!\n");
#endif
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */

14
board/davinci/da8xxevm/omapl138_lcdk.c
View File

@ -11,7 +11,6 @@
#include <common.h>
#include <i2c.h>
#include <net.h>
#include <netdev.h>
#include <spi.h>
#include <spi_flash.h>
#include <asm/arch/hardware.h>
@ -229,19 +228,6 @@ int board_init(void)
#ifdef CONFIG_DRIVER_TI_EMAC
/*
* Initializes on-board ethernet controllers.
*/
int board_eth_init(bd_t *bis)
{
if (!davinci_emac_initialize()) {
printf("Error: Ethernet init failed!\n");
return -1;
}
return 0;
}
#endif /* CONFIG_DRIVER_TI_EMAC */
#define CFG_MAC_ADDR_SPI_BUS 0

18
board/freescale/ls1021atsn/Kconfig Normal file
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@ -0,0 +1,18 @@
# SPDX-License-Identifier: GPL-2.0
if TARGET_LS1021ATSN
config SYS_BOARD
default "ls1021atsn"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "ls102xa"
config SYS_CONFIG_NAME
default "ls1021atsn"
source "board/freescale/common/Kconfig"
endif

8
board/freescale/ls1021atsn/MAINTAINERS Normal file
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@ -0,0 +1,8 @@
NXP LS1021A-TSN Board
M: Vladimir Oltean <olteanv@gmail.com>
S: Maintained
F: arch/arm/dts/ls1021a-tsn.dts
F: board/freescale/ls1021atsn/
F: include/configs/ls1021atsn.h
F: configs/ls1021atsn_qspi_defconfig
F: configs/ls1021atsn_sdcard_defconfig

3
board/freescale/ls1021atsn/Makefile Normal file
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@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += ls1021atsn.o
obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o

97
board/freescale/ls1021atsn/README.rst Normal file
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@ -0,0 +1,97 @@
.. SPDX-License-Identifier: GPL-2.0
LS1021A-TSN Board Overview
==========================
- 1GB DDR3 at 800 MHz
- Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash
- Ethernet
- 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031)
- One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R)
- One internal RGMII port connected to the switch
- SDHC
- microSDHC/SDXC connector
- Other I/O
- One Serial port
- Arduino and expansion headers
- mPCIE slot
- SATA port
- USB3.0 port
LS1021A Memory map
==================
The addresses in brackets are physical addresses.
============== ============== ============================== =======
Start Address End Address Description Size
============== ============== ============================== =======
0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
============== ============== ============================== =======
Compiling and flashing
======================
The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that
can be used to update its internal QSPI flash (which is empty out of the
factory).
To compile and flash an SD card image::
make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/
=> tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100
For the QSPI flash, first obtain the Reset Configuration Word binary for
bootimg from the QSPI flash from the rcw project
(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw)::
make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/
The above RCW binary takes care of swapping the QSPI AMBA memory, so that the
U-Boot binary does not need to be swapped when flashing it.
To compile and flash a U-Boot image for QSPI::
make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/
Then optionally create a custom uboot-env.txt file (although the default
environment already supports distro boot) and convert it to binary format::
mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt
To program the QSPI flash with the images::
=> tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize}
=> tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize}
=> tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize}
The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC
addresses of the Ethernet interfaces, however the EEPROM comes blank out of
the factory, and the MAC addresses are printed on a label on the bottom of
the boards.
To write the MAC addresses to the EEPROM, the following needs to be done once::
=> mac id
=> mac 0 00:1F:7B:xx:xx:xx
=> mac 1 00:1F:7B:xx:xx:xx
=> mac 2 00:1F:7B:xx:xx:xx
=> mac save
The switch ports do not have their own MAC address - they inherit it from the
master enet2 port.
Known issues and limitations
============================
- The 4 SJA1105 switch ports are not functional in U-Boot for now.
- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is
no way to talk to the CPLD for e.g. running the "qixis_reset" command, or
turning the fan on, etc.

260
board/freescale/ls1021atsn/ls1021atsn.c Normal file
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@ -0,0 +1,260 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2019 NXP Semiconductors
*/
#include <common.h>
#include <asm/arch-ls102xa/ls102xa_soc.h>
#include <asm/arch/ls102xa_devdis.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/fsl_serdes.h>
#include "../common/sleep.h"
#include <fsl_validate.h>
#include <fsl_immap.h>
#include <fsl_csu.h>
#include <netdev.h>
#include <spl.h>
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
static void ddrmc_init(void)
{
#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
out_be32(&ddr->sdram_cfg_2,
DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
out_be32(&ddr->init_ext_addr, (1 << 31));
/* DRAM VRef will not be trained */
out_be32(&ddr->ddr_cdr2,
DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
} else
#endif
{
out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
}
out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
/* DDR erratum A-009942 */
tmp = in_be32(&ddr->debug[28]);
out_be32(&ddr->debug[28], tmp | 0x0070006f);
udelay(1);
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
/* enter self-refresh */
temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
} else
#endif
temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
#ifdef CONFIG_DEEP_SLEEP
if (is_warm_boot()) {
/* exit self-refresh */
temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
}
#endif
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
}
int dram_init(void)
{
ddrmc_init();
erratum_a008850_post();
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
fsl_dp_resume();
#endif
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/*
* Clear BD & FR bits for big endian BD's and frame data (aka set
* correct eTSEC endianness). This is crucial in ensuring that it does
* not report Data Parity Errors in its RX/TX FIFOs when attempting to
* send traffic.
*/
clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
/* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
arch_soc_init();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot()) {
timer_init();
dram_init();
}
#endif
return 0;
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
void (*second_uboot)(void);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
get_clocks();
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
fsl_dp_disable_console();
#endif
preloader_console_init();
dram_init();
/* Allow OCRAM access permission as R/W */
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
enable_layerscape_ns_access();
#endif
/*
* if it is woken up from deep sleep, then jump to second
* stage U-Boot and continue executing without recopying
* it from SD since it has already been reserved in memory
* in last boot.
*/
if (is_warm_boot()) {
second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
second_uboot();
}
board_init_r(NULL, 0);
}
#endif
int board_init(void)
{
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
#endif
ls102xa_smmu_stream_id_init();
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_U_QE
u_qe_init();
#endif
return 0;
}
#if defined(CONFIG_SPL_BUILD)
void spl_board_init(void)
{
ls102xa_smmu_stream_id_init();
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
return 0;
}
#endif
#if defined(CONFIG_MISC_INIT_R)
int misc_init_r(void)
{
#ifdef CONFIG_FSL_DEVICE_DISABLE
device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
#endif
#ifdef CONFIG_FSL_CAAM
return sec_init();
#endif
}
#endif
#if defined(CONFIG_DEEP_SLEEP)
void board_sleep_prepare(void)
{
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
}
#endif
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
return 0;
}

15
board/freescale/ls1021atsn/ls102xa_pbi.cfg Normal file
View File

@ -0,0 +1,15 @@
# PBI commands
09570200 ffffffff
09570158 00000300
8940007c 21f47300
# Configure Scratch register
09ee0200 10000000
# Configure alternate space
09570158 00001000
# Flush PBL data
096100c0 000FFFFF
09ea085c 00502880
09ea0560 80800000

8
board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg Normal file
View File

@ -0,0 +1,8 @@
# PBL preamble and RCW header
aa55aa55 01ee0100
# Disable IFC, enable QSPI and DSPI
0608000c 00000000 00000000 00000000
30000000 08007900 40105a00 21046000
00000000 00000000 00000000 10002000
20124801 8804b340 00000000 00000000

38
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -248,44 +248,6 @@ int board_mmc_init(bd_t *bis)
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
if (is_serdes_configured(SGMII_TSEC1)) {
puts("eTSEC1 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
puts("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
return pci_eth_init(bis);
}

1
board/logicpd/am3517evm/am3517evm.c
View File

@ -28,7 +28,6 @@
#include <linux/usb/gadget.h>
#include <linux/usb/musb.h>
#include <i2c.h>
#include <netdev.h>
#include "am3517evm.h"
DECLARE_GLOBAL_DATA_PTR;

3
board/ti/ti816x/evm.c
View File

@ -9,7 +9,6 @@
#include <common.h>
#include <environment.h>
#include <spl.h>
#include <netdev.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
@ -56,7 +55,7 @@ int board_eth_init(bd_t *bis)
printf("Unable to read MAC address. Set <ethaddr>\n");
}
return davinci_emac_initialize();
return 0;
}
#ifdef CONFIG_SPL_BUILD

1
configs/am3517_evm_defconfig
View File

@ -44,6 +44,7 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_PINCTRL=y

1
configs/da850_am18xxevm_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_DM_SERIAL=y

1
configs/da850evm_defconfig
View File

@ -59,6 +59,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_PINCTRL=y

1
configs/da850evm_direct_nor_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_PINCTRL=y

1
configs/da850evm_nand_defconfig
View File

@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DM_SERIAL=y

79
configs/ls1021atsn_qspi_defconfig Normal file
View File

@ -0,0 +1,79 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATSN=y
CONFIG_SYS_TEXT_BASE=0x40100000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
CONFIG_QSPI_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_FAT=y
CONFIG_FSL_ESDHC=y
CONFIG_CMD_SF=y
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_DATAFLASH=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_PCI=y
CONFIG_CMD_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_CMD_MMC=y
CONFIG_DM_MMC=y
CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_FSL=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_HAS_FSL_XHCI_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_FIXED=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMDLINE_TAG=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_LONGHELP=y
CONFIG_FIT=y
CONFIG_CMD_DM=y
CONFIG_AHCI=y
CONFIG_CMD_I2C=y
CONFIG_BLK=y
CONFIG_CMD_PART=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_FS_UUID=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DISTRO_DEFAULTS=y

91
configs/ls1021atsn_sdcard_defconfig Normal file
View File

@ -0,0 +1,91 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1021ATSN=y
CONFIG_SPL_TEXT_BASE=0x10000000
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL=y
CONFIG_SPL_FRAMEWORK=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
CONFIG_HUSH_PARSER=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_CMD_SF=y
CONFIG_OF_CONTROL=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SPI=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_NETDEVICES=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_MII=y
CONFIG_SYS_NS16550=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_DATAFLASH=y
CONFIG_FSL_DSPI=y
CONFIG_FSL_QSPI=y
CONFIG_PCI=y
CONFIG_CMD_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_CMD_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_FSL=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_HAS_FSL_XHCI_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_EXT2=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_PHYLIB=y
CONFIG_PHY_GIGE=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_FIXED=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMDLINE_TAG=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_LONGHELP=y
CONFIG_FIT=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_CMD_DM=y
CONFIG_AHCI=y
CONFIG_CMD_I2C=y
CONFIG_BLK=y
CONFIG_DM_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_CMD_FS_UUID=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DISTRO_DEFAULTS=y

2
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_nor_defconfig
View File

@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_nor_lpuart_defconfig
View File

@ -42,7 +42,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_qspi_defconfig
View File

@ -42,7 +42,9 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -53,7 +53,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_sdcard_ifc_defconfig
View File

@ -54,7 +54,9 @@ CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

2
configs/ls1021atwr_sdcard_qspi_defconfig
View File

@ -53,7 +53,9 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_DM_ETH=y
CONFIG_TSEC_ENET=y
CONFIG_PHY_ATHEROS=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

6
configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
View File

@ -39,13 +39,17 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

5
configs/ls1028aqds_tfa_defconfig
View File

@ -42,10 +42,13 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

4
configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
View File

@ -40,12 +40,16 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_ECAM_GENERIC=y
CONFIG_PCIE_LAYERSCAPE=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y

3
configs/ls1028ardb_tfa_defconfig
View File

@ -43,9 +43,12 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FSL_ENETC=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y

1
configs/omapl138_lcdk_defconfig
View File

@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=30000000
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_DM_SERIAL=y

1
configs/ti816x_evm_defconfig
View File

@ -47,6 +47,7 @@ CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_DRIVER_TI_EMAC=y
CONFIG_SYS_NS16550=y

4
doc/device-tree-bindings/net/fsl-tsec-phy.txt
View File

@ -28,13 +28,13 @@ device that exists on this bus, a PHY node should be created.
Required properties:
- compatible : Should define the compatible device type for the
mdio. Currently supported string/device is "fsl,tsec-mdio".
mdio. Currently supported string/device is "fsl,etsec2-mdio".
- reg : Offset and length of the register set for the device
Example:
mdio@24520 {
compatible = "fsl,tsec-mdio";
compatible = "fsl,etsec2-mdio";
reg = <0x24520 0x20>;
ethernet-phy@0 {

82
doc/device-tree-bindings/net/mdio-mux-reg.txt Normal file
View File

@ -0,0 +1,82 @@
Device tree structures used by register based MDIO muxes is described here.
This binding is based on reg-mux.txt binding in Linux and is currently used by
mdio-mux-i2creg driver in U-Boot.
Required properties:
#mux-control-cells = <1> indicates how many registers are used for mux
selection. mux-reg-mask property described below must
include this number of pairs.
mux-reg-masks = <reg mask> describes pairs of register offset and register mask.
Register bits enabled in mask are set to the selection
value defined in reg property of child MDIOs to control
selection.
Properties described in mdio-mux.txt also apply.
Example structure, used on Freescale LS1028A QDS board:
&i2c0 {
status = "okay";
u-boot,dm-pre-reloc;
fpga@66 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "simple-mfd";
reg = <0x66>;
mux-mdio@54 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-i2creg";
reg = <0x54>;
#mux-control-cells = <1>;
mux-reg-masks = <0x54 0xf0>;
mdio-parent-bus = <&mdio0>;
/* on-board MDIO with a single RGMII PHY */
mdio@00 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
/* on-board 1G RGMII PHY */
qds_phy0: phy@5 {
reg = <5>;
};
};
/* card slot 1 */
mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
/* VSC8234 1G SGMII card */
sgmii_port0: phy@1c {
reg = <0x1c>;
};
};
/* card slot 2 */
mdio@50 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x50>;
};
/* card slot 3 */
mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
};
/* card slot 4 */
mdio@70 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
};
};
};
};
/* Parent MDIO, defined in SoC .dtsi file, just enabled here */
&mdio0 {
status = "okay";
};

15
drivers/net/Kconfig
View File

@ -588,4 +588,19 @@ config HIGMACV300_ETH
This driver supports HIGMACV300 Ethernet controller found on
HiSilicon SoCs.
config FSL_ENETC
bool "NXP ENETC Ethernet controller"
depends on DM_PCI && DM_ETH && DM_MDIO
help
This driver supports the NXP ENETC Ethernet controller found on some
of the NXP SoCs.
config MDIO_MUX_I2CREG
bool "MDIO MUX accessed as a register over I2C"
depends on DM_MDIO_MUX && DM_I2C
help
This driver is used for MDIO muxes driven by writing to a register of
an I2C chip. The board it was developed for uses a mux controlled by
on-board FPGA which in turn is accessed as a chip over I2C.
endif # NETDEVICES

2
drivers/net/Makefile
View File

@ -37,6 +37,7 @@ obj-$(CONFIG_LAN91C96) += lan91c96.o
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MDIO_MUX_I2CREG) += mdio_mux_i2creg.o
obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
@ -79,3 +80,4 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-y += mscc_eswitch/
obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o
obj-$(CONFIG_MDIO_SANDBOX) += mdio_sandbox.o
obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o

8
drivers/net/designware.c
View File

@ -480,18 +480,16 @@ static int _dw_free_pkt(struct dw_eth_dev *priv)
static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
{
struct phy_device *phydev;
int mask = 0xffffffff, ret;
int phy_addr = -1, ret;
#ifdef CONFIG_PHY_ADDR
mask = 1 << CONFIG_PHY_ADDR;
phy_addr = CONFIG_PHY_ADDR;
#endif
phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
if (!phydev)
return -ENODEV;
phy_connect_dev(phydev, dev);
phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);

597
drivers/net/fsl_enetc.c Normal file
View File

@ -0,0 +1,597 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ENETC ethernet controller driver
* Copyright 2017-2019 NXP
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <memalign.h>
#include <asm/io.h>
#include <pci.h>
#include <miiphy.h>
#include "fsl_enetc.h"
/*
* Bind the device:
* - set a more explicit name on the interface
*/
static int enetc_bind(struct udevice *dev)
{
char name[16];
static int eth_num_devices;
/*
* prefer using PCI function numbers to number interfaces, but these
* are only available if dts nodes are present. For PCI they are
* optional, handle that case too. Just in case some nodes are present
* and some are not, use different naming scheme - enetc-N based on
* PCI function # and enetc#N based on interface count
*/
if (ofnode_valid(dev->node))
sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
else
sprintf(name, "enetc#%u", eth_num_devices++);
device_set_name(dev, name);
return 0;
}
/* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
struct enetc_mdio_priv priv;
priv.regs_base = bus->priv;
return enetc_mdio_read_priv(&priv, addr, devad, reg);
}
static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
struct enetc_mdio_priv priv;
priv.regs_base = bus->priv;
return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
}
/* only interfaces that can pin out through serdes have internal MDIO */
static bool enetc_has_imdio(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
return !!(priv->imdio.priv);
}
/* set up serdes for SGMII */
static int enetc_init_sgmii(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
bool is2500 = false;
u16 reg;
if (!enetc_has_imdio(dev))
return 0;
if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
is2500 = true;
/*
* Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
* Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
* on PLL configuration. Setting 1G for 2.5G here is counter intuitive
* but intentional.
*/
reg = ENETC_PCS_IF_MODE_SGMII;
reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
ENETC_PCS_IF_MODE, reg);
/* Dev ability - SGMII */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
/* Adjust link timer for SGMII */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
reg = ENETC_PCS_CR_DEF_VAL;
reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
/* restart PCS AN */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
ENETC_PCS_CR, reg);
return 0;
}
/* set up MAC for RGMII */
static int enetc_init_rgmii(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
u32 if_mode;
/* enable RGMII AN */
if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
if_mode |= ENETC_PM_IF_MODE_AN_ENA;
enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
return 0;
}
/* set up MAC and serdes for SXGMII */
static int enetc_init_sxgmii(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
u32 if_mode;
/* set ifmode to (US)XGMII */
if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
if (!enetc_has_imdio(dev))
return 0;
/* Dev ability - SXGMII */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
/* Restart PCS AN */
enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
ENETC_PCS_CR,
ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
return 0;
}
/* Apply protocol specific configuration to MAC, serdes as needed */
static void enetc_start_pcs(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
const char *if_str;
priv->if_type = PHY_INTERFACE_MODE_NONE;
/* check internal mdio capability, not all ports need it */
if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
/*
* set up internal MDIO, this is part of ETH PCI function and is
* used to access serdes / internal SoC PHYs.
* We don't currently register it as a MDIO bus as it goes away
* when the interface is removed, so it can't practically be
* used in the console.
*/
priv->imdio.read = enetc_mdio_read;
priv->imdio.write = enetc_mdio_write;
priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
}
if (!ofnode_valid(dev->node)) {
enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
return;
}
if_str = ofnode_read_string(dev->node, "phy-mode");
if (if_str)
priv->if_type = phy_get_interface_by_name(if_str);
else
enetc_dbg(dev,
"phy-mode property not found, defaulting to SGMII\n");
if (priv->if_type < 0)
priv->if_type = PHY_INTERFACE_MODE_NONE;
switch (priv->if_type) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
enetc_init_sgmii(dev);
break;
case PHY_INTERFACE_MODE_RGMII:
enetc_init_rgmii(dev);
break;
case PHY_INTERFACE_MODE_XGMII:
enetc_init_sxgmii(dev);
break;
};
}
/* Configure the actual/external ethernet PHY, if one is found */
static void enetc_start_phy(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
struct udevice *miidev;
struct phy_device *phy;
u32 phandle, phy_id;
ofnode phy_node;
int supported;
if (!ofnode_valid(dev->node)) {
enetc_dbg(dev, "no enetc ofnode found, skipping PHY set-up\n");
return;
}
if (ofnode_read_u32(dev->node, "phy-handle", &phandle)) {
enetc_dbg(dev, "phy-handle not found, skipping PHY set-up\n");
return;
}
phy_node = ofnode_get_by_phandle(phandle);
if (!ofnode_valid(phy_node)) {
enetc_dbg(dev, "invalid phy node, skipping PHY set-up\n");
return;
}
enetc_dbg(dev, "phy node: %s\n", ofnode_get_name(phy_node));
if (ofnode_read_u32(phy_node, "reg", &phy_id)) {
enetc_dbg(dev,
"missing reg in PHY node, skipping PHY set-up\n");
return;
}
if (uclass_get_device_by_ofnode(UCLASS_MDIO,
ofnode_get_parent(phy_node),
&miidev)) {
enetc_dbg(dev, "can't find MDIO bus for node %s\n",
ofnode_get_name(ofnode_get_parent(phy_node)));
return;
}
phy = dm_mdio_phy_connect(miidev, phy_id, dev, priv->if_type);
if (!phy) {
enetc_dbg(dev, "dm_mdio_phy_connect returned null\n");
return;
}
supported = GENMASK(6, 0); /* speeds up to 1G & AN */
phy->advertising = phy->supported & supported;
phy_config(phy);
phy_startup(phy);
}
/*
* Probe ENETC driver:
* - initialize port and station interface BARs
*/
static int enetc_probe(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) {
enetc_dbg(dev, "interface disabled\n");
return -ENODEV;
}
priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
if (!priv->enetc_txbd || !priv->enetc_rxbd) {
/* free should be able to handle NULL, just free all pointers */
free(priv->enetc_txbd);
free(priv->enetc_rxbd);
return -ENOMEM;
}
/* initialize register */
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
if (!priv->regs_base) {
enetc_dbg(dev, "failed to map BAR0\n");
return -EINVAL;
}
priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
return 0;
}
/*
* Remove the driver from an interface:
* - free up allocated memory
*/
static int enetc_remove(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
free(priv->enetc_txbd);
free(priv->enetc_rxbd);
return 0;
}
/* ENETC Port MAC address registers, accepts big-endian format */
static void enetc_set_primary_mac_addr(struct enetc_priv *priv, const u8 *addr)
{
u16 lower = *(const u16 *)(addr + 4);
u32 upper = *(const u32 *)addr;
enetc_write_port(priv, ENETC_PSIPMAR0, upper);
enetc_write_port(priv, ENETC_PSIPMAR1, lower);
}
/* Configure port parameters (# of rings, frame size, enable port) */
static void enetc_enable_si_port(struct enetc_priv *priv)
{
u32 val;
/* set Rx/Tx BDR count */
val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
enetc_write_port(priv, ENETC_PSICFGR(0), val);
/* set Rx max frame size */
enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
/* enable MAC port */
enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
/* enable port */
enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
/* set SI cache policy */
enetc_write(priv, ENETC_SICAR0,
ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
/* enable SI */
enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
}
/* returns DMA address for a given buffer index */
static inline u64 enetc_rxb_address(struct udevice *dev, int i)
{
return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
}
/*
* Setup a single Tx BD Ring (ID = 0):
* - set Tx buffer descriptor address
* - set the BD count
* - initialize the producer and consumer index
*/
static void enetc_setup_tx_bdr(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
struct bd_ring *tx_bdr = &priv->tx_bdr;
u64 tx_bd_add = (u64)priv->enetc_txbd;
/* used later to advance to the next Tx BD */
tx_bdr->bd_count = ENETC_BD_CNT;
tx_bdr->next_prod_idx = 0;
tx_bdr->next_cons_idx = 0;
tx_bdr->cons_idx = priv->regs_base +
ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
tx_bdr->prod_idx = priv->regs_base +
ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
/* set Tx BD address */
enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
lower_32_bits(tx_bd_add));
enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
upper_32_bits(tx_bd_add));
/* set Tx 8 BD count */
enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
tx_bdr->bd_count);
/* reset both producer/consumer indexes */
enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
/* enable TX ring */
enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
}
/*
* Setup a single Rx BD Ring (ID = 0):
* - set Rx buffer descriptors address (one descriptor per buffer)
* - set buffer size as max frame size
* - enable Rx ring
* - reset consumer and producer indexes
* - set buffer for each descriptor
*/
static void enetc_setup_rx_bdr(struct udevice *dev)
{
struct enetc_priv *priv = dev_get_priv(dev);
struct bd_ring *rx_bdr = &priv->rx_bdr;
u64 rx_bd_add = (u64)priv->enetc_rxbd;
int i;
/* used later to advance to the next BD produced by ENETC HW */
rx_bdr->bd_count = ENETC_BD_CNT;
rx_bdr->next_prod_idx = 0;
rx_bdr->next_cons_idx = 0;
rx_bdr->cons_idx = priv->regs_base +
ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
rx_bdr->prod_idx = priv->regs_base +
ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
/* set Rx BD address */
enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
lower_32_bits(rx_bd_add));
enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
upper_32_bits(rx_bd_add));
/* set Rx BD count (multiple of 8) */
enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
rx_bdr->bd_count);
/* set Rx buffer size */
enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
/* fill Rx BD */
memset(priv->enetc_rxbd, 0,
rx_bdr->bd_count * sizeof(union enetc_rx_bd));
for (i = 0; i < rx_bdr->bd_count; i++) {
priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
/* each RX buffer must be aligned to 64B */
WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
}
/* reset producer (ENETC owned) and consumer (SW owned) index */
enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
/* enable Rx ring */
enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
}
/*
* Start ENETC interface:
* - perform FLR
* - enable access to port and SI registers
* - set mac address
* - setup TX/RX buffer descriptors
* - enable Tx/Rx rings
*/
static int enetc_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_platdata(dev);
struct enetc_priv *priv = dev_get_priv(dev);
/* reset and enable the PCI device */
dm_pci_flr(dev);
dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
if (!is_valid_ethaddr(plat->enetaddr)) {
enetc_dbg(dev, "invalid MAC address, generate random ...\n");
net_random_ethaddr(plat->enetaddr);
}
enetc_set_primary_mac_addr(priv, plat->enetaddr);
enetc_enable_si_port(priv);
/* setup Tx/Rx buffer descriptors */
enetc_setup_tx_bdr(dev);
enetc_setup_rx_bdr(dev);
enetc_start_pcs(dev);
enetc_start_phy(dev);
return 0;
}
/*
* Stop the network interface:
* - just quiesce it, we can wipe all configuration as _start starts from
* scratch each time
*/
static void enetc_stop(struct udevice *dev)
{
/* FLR is sufficient to quiesce the device */
dm_pci_flr(dev);
}
/*
* ENETC transmit packet:
* - check if Tx BD ring is full
* - set buffer/packet address (dma address)
* - set final fragment flag
* - try while producer index equals consumer index or timeout
*/
static int enetc_send(struct udevice *dev, void *packet, int length)
{
struct enetc_priv *priv = dev_get_priv(dev);
struct bd_ring *txr = &priv->tx_bdr;
void *nv_packet = (void *)packet;
int tries = ENETC_POLL_TRIES;
u32 pi, ci;
pi = txr->next_prod_idx;
ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
/* Tx ring is full when */
if (((pi + 1) % txr->bd_count) == ci) {
enetc_dbg(dev, "Tx BDR full\n");
return -ETIMEDOUT;
}
enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
/* prepare Tx BD */
memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
priv->enetc_txbd[pi].addr =
cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
dmb();
/* send frame: increment producer index */
pi = (pi + 1) % txr->bd_count;
txr->next_prod_idx = pi;
enetc_write_reg(txr->prod_idx, pi);
while ((--tries >= 0) &&
(pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
udelay(10);
return tries > 0 ? 0 : -ETIMEDOUT;
}
/*
* Receive frame:
* - wait for the next BD to get ready bit set
* - clean up the descriptor
* - move on and indicate to HW that the cleaned BD is available for Rx
*/
static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct enetc_priv *priv = dev_get_priv(dev);
struct bd_ring *rxr = &priv->rx_bdr;
int tries = ENETC_POLL_TRIES;
int pi = rxr->next_prod_idx;
int ci = rxr->next_cons_idx;
u32 status;
int len;
u8 rdy;
do {
dmb();
status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
/* check if current BD is ready to be consumed */
rdy = ENETC_RXBD_STATUS_R(status);
} while (--tries >= 0 && !rdy);
if (!rdy)
return -EAGAIN;
dmb();
len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
*packetp = (uchar *)enetc_rxb_address(dev, pi);
enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
ENETC_RXBD_STATUS_ERRORS(status),
upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
/* BD clean up and advance to next in ring */
memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
ci = (ci + 1) % rxr->bd_count;
rxr->next_cons_idx = ci;
dmb();
/* free up the slot in the ring for HW */
enetc_write_reg(rxr->cons_idx, ci);
return len;
}
static const struct eth_ops enetc_ops = {
.start = enetc_start,
.send = enetc_send,
.recv = enetc_recv,
.stop = enetc_stop,
};
U_BOOT_DRIVER(eth_enetc) = {
.name = "enetc_eth",
.id = UCLASS_ETH,
.bind = enetc_bind,
.probe = enetc_probe,
.remove = enetc_remove,
.ops = &enetc_ops,
.priv_auto_alloc_size = sizeof(struct enetc_priv),
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};
static struct pci_device_id enetc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
{}
};
U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);

229
drivers/net/fsl_enetc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* ENETC ethernet controller driver
* Copyright 2017-2019 NXP
*/
#ifndef _ENETC_H
#define _ENETC_H
#define enetc_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
/* PCI function IDs */
#define PCI_DEVICE_ID_ENETC_ETH 0xE100
#define PCI_DEVICE_ID_ENETC_MDIO 0xEE01
/* ENETC Ethernet controller registers */
/* Station interface register offsets */
#define ENETC_SIMR 0x000
#define ENETC_SIMR_EN BIT(31)
#define ENETC_SICAR0 0x040
/* write cache cfg: snoop, no allocate, data & BD coherent */
#define ENETC_SICAR_WR_CFG 0x6767
/* read cache cfg: coherent copy, look up, don't alloc in cache */
#define ENETC_SICAR_RD_CFG 0x27270000
#define ENETC_SIROCT 0x300
#define ENETC_SIRFRM 0x308
#define ENETC_SITOCT 0x320
#define ENETC_SITFRM 0x328
/* Rx/Tx Buffer Descriptor Ring registers */
enum enetc_bdr_type {TX, RX};
#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 + (off))
#define ENETC_BDR_IDX_MASK 0xffff
/* Rx BDR reg offsets */
#define ENETC_RBMR 0x00
#define ENETC_RBMR_EN BIT(31)
#define ENETC_RBBSR 0x08
/* initial consumer index for Rx BDR */
#define ENETC_RBCIR 0x0c
#define ENETC_RBBAR0 0x10
#define ENETC_RBBAR1 0x14
#define ENETC_RBPIR 0x18
#define ENETC_RBLENR 0x20
/* Tx BDR reg offsets */
#define ENETC_TBMR 0x00
#define ENETC_TBMR_EN BIT(31)
#define ENETC_TBBAR0 0x10
#define ENETC_TBBAR1 0x14
#define ENETC_TBPIR 0x18
#define ENETC_TBCIR 0x1c
#define ENETC_TBLENR 0x20
/* Port registers offset */
#define ENETC_PORT_REGS_OFF 0x10000
/* Port registers */
#define ENETC_PMR 0x0000
#define ENETC_PMR_SI0_EN BIT(16)
#define ENETC_PSIPMMR 0x0018
#define ENETC_PSIPMAR0 0x0100
#define ENETC_PSIPMAR1 0x0104
#define ENETC_PCAPR0 0x0900
#define ENETC_PCAPRO_MDIO BIT(11)
#define ENETC_PSICFGR(n) (0x0940 + (n) * 0x10)
#define ENETC_PSICFGR_SET_TXBDR(val) ((val) & 0xff)
#define ENETC_PSICFGR_SET_RXBDR(val) (((val) & 0xff) << 16)
/* MAC configuration */
#define ENETC_PM_CC 0x8008
#define ENETC_PM_CC_DEFAULT 0x0810
#define ENETC_PM_CC_RX_TX_EN 0x8813
#define ENETC_PM_MAXFRM 0x8014
#define ENETC_RX_MAXFRM_SIZE PKTSIZE_ALIGN
#define ENETC_PM_IMDIO_BASE 0x8030
#define ENETC_PM_IF_MODE 0x8300
#define ENETC_PM_IF_MODE_RG BIT(2)
#define ENETC_PM_IF_MODE_AN_ENA BIT(15)
#define ENETC_PM_IF_IFMODE_MASK GENMASK(1, 0)
/* buffer descriptors count must be multiple of 8 and aligned to 128 bytes */
#define ENETC_BD_CNT CONFIG_SYS_RX_ETH_BUFFER
#define ENETC_BD_ALIGN 128
/* single pair of Rx/Tx rings */
#define ENETC_RX_BDR_CNT 1
#define ENETC_TX_BDR_CNT 1
#define ENETC_RX_BDR_ID 0
#define ENETC_TX_BDR_ID 0
/* Tx buffer descriptor */
struct enetc_tx_bd {
__le64 addr;
__le16 buf_len;
__le16 frm_len;
__le16 err_csum;
__le16 flags;
};
#define ENETC_TXBD_FLAGS_F BIT(15)
#define ENETC_POLL_TRIES 32000
/* Rx buffer descriptor */
union enetc_rx_bd {
/* SW provided BD format */
struct {
__le64 addr;
u8 reserved[8];
} w;
/* ENETC returned BD format */
struct {
__le16 inet_csum;
__le16 parse_summary;
__le32 rss_hash;
__le16 buf_len;
__le16 vlan_opt;
union {
struct {
__le16 flags;
__le16 error;
};
__le32 lstatus;
};
} r;
};
#define ENETC_RXBD_STATUS_R(status) (((status) >> 30) & 0x1)
#define ENETC_RXBD_STATUS_F(status) (((status) >> 31) & 0x1)
#define ENETC_RXBD_STATUS_ERRORS(status) (((status) >> 16) & 0xff)
#define ENETC_RXBD_STATUS(flags) ((flags) << 16)
/* Tx/Rx ring info */
struct bd_ring {
void *cons_idx;
void *prod_idx;
/* next BD index to use */
int next_prod_idx;
int next_cons_idx;
int bd_count;
};
/* ENETC private structure */
struct enetc_priv {
struct enetc_tx_bd *enetc_txbd;
union enetc_rx_bd *enetc_rxbd;
void *regs_base; /* base ENETC registers */
void *port_regs; /* base ENETC port registers */
/* Rx/Tx buffer descriptor rings info */
struct bd_ring tx_bdr;
struct bd_ring rx_bdr;
int if_type;
struct mii_dev imdio;
};
/* register accessors */
#define enetc_read_reg(x) readl((x))
#define enetc_write_reg(x, val) writel((val), (x))
#define enetc_read(priv, off) enetc_read_reg((priv)->regs_base + (off))
#define enetc_write(priv, off, v) \
enetc_write_reg((priv)->regs_base + (off), v)
/* port register accessors */
#define enetc_port_regs(priv, off) ((priv)->port_regs + (off))
#define enetc_read_port(priv, off) \
enetc_read_reg(enetc_port_regs((priv), (off)))
#define enetc_write_port(priv, off, v) \
enetc_write_reg(enetc_port_regs((priv), (off)), v)
/* BDR register accessors, see ENETC_BDR() */
#define enetc_bdr_read(priv, t, n, off) \
enetc_read(priv, ENETC_BDR(t, n, off))
#define enetc_bdr_write(priv, t, n, off, val) \
enetc_write(priv, ENETC_BDR(t, n, off), val)
/* PCS / internal SoC PHY ID, it defaults to 0 on all interfaces */
#define ENETC_PCS_PHY_ADDR 0
/* PCS registers */
#define ENETC_PCS_CR 0x00
#define ENETC_PCS_CR_RESET_AN 0x1200
#define ENETC_PCS_CR_DEF_VAL 0x0140
#define ENETC_PCS_CR_RST BIT(15)
#define ENETC_PCS_DEV_ABILITY 0x04
#define ENETC_PCS_DEV_ABILITY_SGMII 0x4001
#define ENETC_PCS_DEV_ABILITY_SXGMII 0x5001
#define ENETC_PCS_LINK_TIMER1 0x12
#define ENETC_PCS_LINK_TIMER1_VAL 0x06a0
#define ENETC_PCS_LINK_TIMER2 0x13
#define ENETC_PCS_LINK_TIMER2_VAL 0x0003
#define ENETC_PCS_IF_MODE 0x14
#define ENETC_PCS_IF_MODE_SGMII BIT(0)
#define ENETC_PCS_IF_MODE_SGMII_AN BIT(1)
#define ENETC_PCS_IF_MODE_SPEED_1G BIT(3)
/* PCS replicator block for USXGMII */
#define ENETC_PCS_DEVAD_REPL 0x1f
/* ENETC external MDIO registers */
#define ENETC_MDIO_BASE 0x1c00
#define ENETC_MDIO_CFG 0x00
#define ENETC_EMDIO_CFG_C22 0x00809508
#define ENETC_EMDIO_CFG_C45 0x00809548
#define ENETC_EMDIO_CFG_RD_ER BIT(1)
#define ENETC_EMDIO_CFG_BSY BIT(0)
#define ENETC_MDIO_CTL 0x04
#define ENETC_MDIO_CTL_READ BIT(15)
#define ENETC_MDIO_DATA 0x08
#define ENETC_MDIO_STAT 0x0c
#define ENETC_MDIO_READ_ERR 0xffff
struct enetc_mdio_priv {
void *regs_base;
};
/*
* these functions are implemented by ENETC_MDIO and are re-used by ENETC driver
* to drive serdes / internal SoC PHYs
*/
int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
int reg);
int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
int reg, u16 val);
#endif /* _ENETC_H */

149
drivers/net/fsl_enetc_mdio.c Normal file
View File

@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ENETC ethernet controller driver
* Copyright 2019 NXP
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <pci.h>
#include <miiphy.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <miiphy.h>
#include "fsl_enetc.h"
static void enetc_mdio_wait_bsy(struct enetc_mdio_priv *priv)
{
while (enetc_read(priv, ENETC_MDIO_CFG) & ENETC_EMDIO_CFG_BSY)
cpu_relax();
}
int enetc_mdio_read_priv(struct enetc_mdio_priv *priv, int addr, int devad,
int reg)
{
if (devad == MDIO_DEVAD_NONE)
enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C22);
else
enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C45);
enetc_mdio_wait_bsy(priv);
if (devad == MDIO_DEVAD_NONE) {
enetc_write(priv, ENETC_MDIO_CTL, ENETC_MDIO_CTL_READ |
(addr << 5) | reg);
} else {
enetc_write(priv, ENETC_MDIO_CTL, (addr << 5) + devad);
enetc_mdio_wait_bsy(priv);
enetc_write(priv, ENETC_MDIO_STAT, reg);
enetc_mdio_wait_bsy(priv);
enetc_write(priv, ENETC_MDIO_CTL, ENETC_MDIO_CTL_READ |
(addr << 5) | devad);
}
enetc_mdio_wait_bsy(priv);
if (enetc_read(priv, ENETC_MDIO_CFG) & ENETC_EMDIO_CFG_RD_ER)
return ENETC_MDIO_READ_ERR;
return enetc_read(priv, ENETC_MDIO_DATA);
}
int enetc_mdio_write_priv(struct enetc_mdio_priv *priv, int addr, int devad,
int reg, u16 val)
{
if (devad == MDIO_DEVAD_NONE)
enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C22);
else
enetc_write(priv, ENETC_MDIO_CFG, ENETC_EMDIO_CFG_C45);
enetc_mdio_wait_bsy(priv);
if (devad != MDIO_DEVAD_NONE) {
enetc_write(priv, ENETC_MDIO_CTL, (addr << 5) + devad);
enetc_write(priv, ENETC_MDIO_STAT, reg);
} else {
enetc_write(priv, ENETC_MDIO_CTL, (addr << 5) + reg);
}
enetc_mdio_wait_bsy(priv);
enetc_write(priv, ENETC_MDIO_DATA, val);
enetc_mdio_wait_bsy(priv);
return 0;
}
/* DM wrappers */
static int dm_enetc_mdio_read(struct udevice *dev, int addr, int devad, int reg)
{
struct enetc_mdio_priv *priv = dev_get_priv(dev);
return enetc_mdio_read_priv(priv, addr, devad, reg);
}
static int dm_enetc_mdio_write(struct udevice *dev, int addr, int devad,
int reg, u16 val)
{
struct enetc_mdio_priv *priv = dev_get_priv(dev);
return enetc_mdio_write_priv(priv, addr, devad, reg, val);
}
static const struct mdio_ops enetc_mdio_ops = {
.read = dm_enetc_mdio_read,
.write = dm_enetc_mdio_write,
};
static int enetc_mdio_bind(struct udevice *dev)
{
char name[16];
static int eth_num_devices;
/*
* prefer using PCI function numbers to number interfaces, but these
* are only available if dts nodes are present. For PCI they are
* optional, handle that case too. Just in case some nodes are present
* and some are not, use different naming scheme - enetc-N based on
* PCI function # and enetc#N based on interface count
*/
if (ofnode_valid(dev->node))
sprintf(name, "emdio-%u", PCI_FUNC(pci_get_devfn(dev)));
else
sprintf(name, "emdio#%u", eth_num_devices++);
device_set_name(dev, name);
return 0;
}
static int enetc_mdio_probe(struct udevice *dev)
{
struct enetc_mdio_priv *priv = dev_get_priv(dev);
priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
if (!priv->regs_base) {
enetc_dbg(dev, "failed to map BAR0\n");
return -EINVAL;
}
priv->regs_base += ENETC_MDIO_BASE;
dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
return 0;
}
U_BOOT_DRIVER(enetc_mdio) = {
.name = "enetc_mdio",
.id = UCLASS_MDIO,
.bind = enetc_mdio_bind,
.probe = enetc_mdio_probe,
.ops = &enetc_mdio_ops,
.priv_auto_alloc_size = sizeof(struct enetc_mdio_priv),
};
static struct pci_device_id enetc_mdio_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_MDIO) },
};
U_BOOT_PCI_DEVICE(enetc_mdio, enetc_mdio_ids);

208
drivers/net/macb.c
View File

@ -45,9 +45,17 @@
DECLARE_GLOBAL_DATA_PTR;
#define MACB_RX_BUFFER_SIZE 4096
#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
/*
* These buffer sizes must be power of 2 and divisible
* by RX_BUFFER_MULTIPLE
*/
#define MACB_RX_BUFFER_SIZE 128
#define GEM_RX_BUFFER_SIZE 2048
#define RX_BUFFER_MULTIPLE 64
#define MACB_RX_RING_SIZE 32
#define MACB_TX_RING_SIZE 16
#define MACB_TX_TIMEOUT 1000
#define MACB_AUTONEG_TIMEOUT 5000000
@ -77,31 +85,16 @@ struct macb_dma_desc {
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
#define RXADDR_USED 0x00000001
#define RXADDR_WRAP 0x00000002
#define RXBUF_FRMLEN_MASK 0x00000fff
#define RXBUF_FRAME_START 0x00004000
#define RXBUF_FRAME_END 0x00008000
#define RXBUF_TYPEID_MATCH 0x00400000
#define RXBUF_ADDR4_MATCH 0x00800000
#define RXBUF_ADDR3_MATCH 0x01000000
#define RXBUF_ADDR2_MATCH 0x02000000
#define RXBUF_ADDR1_MATCH 0x04000000
#define RXBUF_BROADCAST 0x80000000
#define TXBUF_FRMLEN_MASK 0x000007ff
#define TXBUF_FRAME_END 0x00008000
#define TXBUF_NOCRC 0x00010000
#define TXBUF_EXHAUSTED 0x08000000
#define TXBUF_UNDERRUN 0x10000000
#define TXBUF_MAXRETRY 0x20000000
#define TXBUF_WRAP 0x40000000
#define TXBUF_USED 0x80000000
struct macb_device {
void *regs;
bool is_big_endian;
const struct macb_config *config;
unsigned int rx_tail;
unsigned int tx_head;
unsigned int tx_tail;
@ -112,6 +105,7 @@ struct macb_device {
void *tx_buffer;
struct macb_dma_desc *rx_ring;
struct macb_dma_desc *tx_ring;
size_t rx_buffer_size;
unsigned long rx_buffer_dma;
unsigned long rx_ring_dma;
@ -137,6 +131,13 @@ struct macb_device {
phy_interface_t phy_interface;
#endif
};
struct macb_config {
unsigned int dma_burst_length;
int (*clk_init)(struct udevice *dev, ulong rate);
};
#ifndef CONFIG_DM_ETH
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
#endif
@ -316,9 +317,9 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
ctrl = length & TXBUF_FRMLEN_MASK;
ctrl |= TXBUF_FRAME_END;
ctrl |= MACB_BIT(TX_LAST);
if (tx_head == (MACB_TX_RING_SIZE - 1)) {
ctrl |= TXBUF_WRAP;
ctrl |= MACB_BIT(TX_WRAP);
macb->tx_head = 0;
} else {
macb->tx_head++;
@ -340,7 +341,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
barrier();
macb_invalidate_ring_desc(macb, TX);
ctrl = macb->tx_ring[tx_head].ctrl;
if (ctrl & TXBUF_USED)
if (ctrl & MACB_BIT(TX_USED))
break;
udelay(1);
}
@ -348,9 +349,9 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
dma_unmap_single(packet, length, paddr);
if (i <= MACB_TX_TIMEOUT) {
if (ctrl & TXBUF_UNDERRUN)
if (ctrl & MACB_BIT(TX_UNDERRUN))
printf("%s: TX underrun\n", name);
if (ctrl & TXBUF_EXHAUSTED)
if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
printf("%s: TX buffers exhausted in mid frame\n", name);
} else {
printf("%s: TX timeout\n", name);
@ -369,14 +370,14 @@ static void reclaim_rx_buffers(struct macb_device *macb,
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
macb->rx_ring[i].addr &= ~RXADDR_USED;
macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
macb->rx_ring[i].addr &= ~RXADDR_USED;
macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
i++;
}
@ -396,26 +397,27 @@ static int _macb_recv(struct macb_device *macb, uchar **packetp)
for (;;) {
macb_invalidate_ring_desc(macb, RX);
if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
if (status & RXBUF_FRAME_START) {
if (status & MACB_BIT(RX_SOF)) {
if (next_rx_tail != macb->rx_tail)
reclaim_rx_buffers(macb, next_rx_tail);
macb->wrapped = false;
}
if (status & RXBUF_FRAME_END) {
buffer = macb->rx_buffer + 128 * macb->rx_tail;
if (status & MACB_BIT(RX_EOF)) {
buffer = macb->rx_buffer +
macb->rx_buffer_size * macb->rx_tail;
length = status & RXBUF_FRMLEN_MASK;
macb_invalidate_rx_buffer(macb);
if (macb->wrapped) {
unsigned int headlen, taillen;
headlen = 128 * (MACB_RX_RING_SIZE
- macb->rx_tail);
headlen = macb->rx_buffer_size *
(MACB_RX_RING_SIZE - macb->rx_tail);
taillen = length - headlen;
memcpy((void *)net_rx_packets[0],
buffer, headlen);
@ -495,21 +497,38 @@ static int macb_phy_find(struct macb_device *macb, const char *name)
* when operation failed.
*/
#ifdef CONFIG_DM_ETH
static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
{
fdt_addr_t addr;
void *gemgxl_regs;
addr = dev_read_addr_index(dev, 1);
if (addr == FDT_ADDR_T_NONE)
return -ENODEV;
gemgxl_regs = (void __iomem *)addr;
if (!gemgxl_regs)
return -ENODEV;
/*
* SiFive GEMGXL TX clock operation mode:
*
* 0 = GMII mode. Use 125 MHz gemgxlclk from PRCI in TX logic
* and output clock on GMII output signal GTX_CLK
* 1 = MII mode. Use MII input signal TX_CLK in TX logic
*/
writel(rate != 125000000, gemgxl_regs);
return 0;
}
int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
{
#ifdef CONFIG_CLK
struct macb_device *macb = dev_get_priv(dev);
struct clk tx_clk;
ulong rate;
int ret;
/*
* "tx_clk" is an optional clock source for MACB.
* Ignore if it does not exist in DT.
*/
ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
if (ret)
return 0;
switch (speed) {
case _10BASET:
rate = 2500000; /* 2.5 MHz */
@ -525,6 +544,17 @@ int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
return 0;
}
if (macb->config->clk_init)
return macb->config->clk_init(dev, rate);
/*
* "tx_clk" is an optional clock source for MACB.
* Ignore if it does not exist in DT.
*/
ret = clk_get_by_name(dev, "tx_clk", &tx_clk);
if (ret)
return 0;
if (tx_clk.dev) {
ret = clk_set_rate(&tx_clk, rate);
if (ret)
@ -699,7 +729,7 @@ static int gmac_init_multi_queues(struct macb_device *macb)
if (queue_mask & (1 << i))
num_queues++;
macb->dummy_desc->ctrl = TXBUF_USED;
macb->dummy_desc->ctrl = MACB_BIT(TX_USED);
macb->dummy_desc->addr = 0;
flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
@ -710,6 +740,31 @@ static int gmac_init_multi_queues(struct macb_device *macb)
return 0;
}
static void gmac_configure_dma(struct macb_device *macb)
{
u32 buffer_size;
u32 dmacfg;
buffer_size = macb->rx_buffer_size / RX_BUFFER_MULTIPLE;
dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
dmacfg |= GEM_BF(RXBS, buffer_size);
if (macb->config->dma_burst_length)
dmacfg = GEM_BFINS(FBLDO,
macb->config->dma_burst_length, dmacfg);
dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
dmacfg &= ~GEM_BIT(ENDIA_PKT);
if (macb->is_big_endian)
dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
else
dmacfg &= ~GEM_BIT(ENDIA_DESC);
dmacfg &= ~GEM_BIT(ADDR64);
gem_writel(macb, DMACFG, dmacfg);
}
#ifdef CONFIG_DM_ETH
static int _macb_init(struct udevice *dev, const char *name)
#else
@ -732,10 +787,10 @@ static int _macb_init(struct macb_device *macb, const char *name)
paddr = macb->rx_buffer_dma;
for (i = 0; i < MACB_RX_RING_SIZE; i++) {
if (i == (MACB_RX_RING_SIZE - 1))
paddr |= RXADDR_WRAP;
paddr |= MACB_BIT(RX_WRAP);
macb->rx_ring[i].addr = paddr;
macb->rx_ring[i].ctrl = 0;
paddr += 128;
paddr += macb->rx_buffer_size;
}
macb_flush_ring_desc(macb, RX);
macb_flush_rx_buffer(macb);
@ -743,9 +798,10 @@ static int _macb_init(struct macb_device *macb, const char *name)
for (i = 0; i < MACB_TX_RING_SIZE; i++) {
macb->tx_ring[i].addr = 0;
if (i == (MACB_TX_RING_SIZE - 1))
macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
macb->tx_ring[i].ctrl = MACB_BIT(TX_USED) |
MACB_BIT(TX_WRAP);
else
macb->tx_ring[i].ctrl = TXBUF_USED;
macb->tx_ring[i].ctrl = MACB_BIT(TX_USED);
}
macb_flush_ring_desc(macb, TX);
@ -762,6 +818,8 @@ static int _macb_init(struct macb_device *macb, const char *name)
macb_writel(macb, TBQP, macb->tx_ring_dma);
if (macb_is_gem(macb)) {
/* Initialize DMA properties */
gmac_configure_dma(macb);
/* Check the multi queue and initialize the queue for tx */
gmac_init_multi_queues(macb);
@ -774,14 +832,21 @@ static int _macb_init(struct macb_device *macb, const char *name)
#ifdef CONFIG_DM_ETH
if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
(macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
gem_writel(macb, UR, GEM_BIT(RGMII));
gem_writel(macb, USRIO, GEM_BIT(RGMII));
else
gem_writel(macb, UR, 0);
gem_writel(macb, USRIO, 0);
if (macb->phy_interface == PHY_INTERFACE_MODE_SGMII) {
unsigned int ncfgr = macb_readl(macb, NCFGR);
ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
macb_writel(macb, NCFGR, ncfgr);
}
#else
#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
gem_writel(macb, UR, GEM_BIT(RGMII));
gem_writel(macb, USRIO, GEM_BIT(RGMII));
#else
gem_writel(macb, UR, 0);
gem_writel(macb, USRIO, 0);
#endif
#endif
} else {
@ -903,8 +968,12 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
config = GEM_BF(CLK, GEM_CLK_DIV48);
else if (macb_hz < 160000000)
config = GEM_BF(CLK, GEM_CLK_DIV64);
else
else if (macb_hz < 240000000)
config = GEM_BF(CLK, GEM_CLK_DIV96);
else if (macb_hz < 320000000)
config = GEM_BF(CLK, GEM_CLK_DIV128);
else
config = GEM_BF(CLK, GEM_CLK_DIV224);
return config;
}
@ -932,8 +1001,14 @@ static void _macb_eth_initialize(struct macb_device *macb)
int id = 0; /* This is not used by functions we call */
u32 ncfgr;
if (macb_is_gem(macb))
macb->rx_buffer_size = GEM_RX_BUFFER_SIZE;
else
macb->rx_buffer_size = MACB_RX_BUFFER_SIZE;
/* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
macb->rx_buffer = dma_alloc_coherent(macb->rx_buffer_size *
MACB_RX_RING_SIZE,
&macb->rx_buffer_dma);
macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
&macb->rx_ring_dma);
@ -1142,12 +1217,17 @@ static int macb_enable_clk(struct udevice *dev)
}
#endif
static const struct macb_config default_gem_config = {
.dma_burst_length = 16,
.clk_init = NULL,
};
static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
const char *phy_mode;
__maybe_unused int ret;
int ret;
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
NULL);
@ -1160,6 +1240,12 @@ static int macb_eth_probe(struct udevice *dev)
macb->regs = (void *)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
macb->config = (struct macb_config *)dev_get_driver_data(dev);
if (!macb->config)
macb->config = &default_gem_config;
#ifdef CONFIG_CLK
ret = macb_enable_clk(dev);
if (ret)
@ -1220,13 +1306,25 @@ static int macb_eth_ofdata_to_platdata(struct udevice *dev)
return macb_late_eth_ofdata_to_platdata(dev);
}
static const struct macb_config sama5d4_config = {
.dma_burst_length = 4,
.clk_init = NULL,
};
static const struct macb_config sifive_config = {
.dma_burst_length = 16,
.clk_init = macb_sifive_clk_init,
};
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,at91sam9260-macb" },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
{ .compatible = "atmel,sama5d4-gem" },
{ .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "sifive,fu540-c000-gem",
.data = (ulong)&sifive_config },
{ }
};

860
drivers/net/macb.h
View File

@ -5,221 +5,410 @@
#ifndef __DRIVERS_MACB_H__
#define __DRIVERS_MACB_H__
#define MACB_GREGS_NBR 16
#define MACB_GREGS_VERSION 2
#define MACB_MAX_QUEUES 8
/* MACB register offsets */
#define MACB_NCR 0x0000
#define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008
#define GEM_UR 0x000c
#define MACB_DMACFG 0x0010
#define MACB_TSR 0x0014
#define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c
#define MACB_RSR 0x0020
#define MACB_ISR 0x0024
#define MACB_IER 0x0028
#define MACB_IDR 0x002c
#define MACB_IMR 0x0030
#define MACB_MAN 0x0034
#define MACB_PTR 0x0038
#define MACB_PFR 0x003c
#define MACB_FTO 0x0040
#define MACB_SCF 0x0044
#define MACB_MCF 0x0048
#define MACB_FRO 0x004c
#define MACB_FCSE 0x0050
#define MACB_ALE 0x0054
#define MACB_DTF 0x0058
#define MACB_LCOL 0x005c
#define MACB_EXCOL 0x0060
#define MACB_TUND 0x0064
#define MACB_CSE 0x0068
#define MACB_RRE 0x006c
#define MACB_ROVR 0x0070
#define MACB_RSE 0x0074
#define MACB_ELE 0x0078
#define MACB_RJA 0x007c
#define MACB_USF 0x0080
#define MACB_STE 0x0084
#define MACB_RLE 0x0088
#define MACB_TPF 0x008c
#define MACB_HRB 0x0090
#define MACB_HRT 0x0094
#define MACB_SA1B 0x0098
#define MACB_SA1T 0x009c
#define MACB_SA2B 0x00a0
#define MACB_SA2T 0x00a4
#define MACB_SA3B 0x00a8
#define MACB_SA3T 0x00ac
#define MACB_SA4B 0x00b0
#define MACB_SA4T 0x00b4
#define MACB_TID 0x00b8
#define MACB_TPQ 0x00bc
#define MACB_USRIO 0x00c0
#define MACB_WOL 0x00c4
#define MACB_MID 0x00fc
#define MACB_NCR 0x0000 /* Network Control */
#define MACB_NCFGR 0x0004 /* Network Config */
#define MACB_NSR 0x0008 /* Network Status */
#define MACB_TAR 0x000c /* AT91RM9200 only */
#define MACB_TCR 0x0010 /* AT91RM9200 only */
#define MACB_TSR 0x0014 /* Transmit Status */
#define MACB_RBQP 0x0018 /* RX Q Base Address */
#define MACB_TBQP 0x001c /* TX Q Base Address */
#define MACB_RSR 0x0020 /* Receive Status */
#define MACB_ISR 0x0024 /* Interrupt Status */
#define MACB_IER 0x0028 /* Interrupt Enable */
#define MACB_IDR 0x002c /* Interrupt Disable */
#define MACB_IMR 0x0030 /* Interrupt Mask */
#define MACB_MAN 0x0034 /* PHY Maintenance */
#define MACB_PTR 0x0038
#define MACB_PFR 0x003c
#define MACB_FTO 0x0040
#define MACB_SCF 0x0044
#define MACB_MCF 0x0048
#define MACB_FRO 0x004c
#define MACB_FCSE 0x0050
#define MACB_ALE 0x0054
#define MACB_DTF 0x0058
#define MACB_LCOL 0x005c
#define MACB_EXCOL 0x0060
#define MACB_TUND 0x0064
#define MACB_CSE 0x0068
#define MACB_RRE 0x006c
#define MACB_ROVR 0x0070
#define MACB_RSE 0x0074
#define MACB_ELE 0x0078
#define MACB_RJA 0x007c
#define MACB_USF 0x0080
#define MACB_STE 0x0084
#define MACB_RLE 0x0088
#define MACB_TPF 0x008c
#define MACB_HRB 0x0090
#define MACB_HRT 0x0094
#define MACB_SA1B 0x0098
#define MACB_SA1T 0x009c
#define MACB_SA2B 0x00a0
#define MACB_SA2T 0x00a4
#define MACB_SA3B 0x00a8
#define MACB_SA3T 0x00ac
#define MACB_SA4B 0x00b0
#define MACB_SA4T 0x00b4
#define MACB_TID 0x00b8
#define MACB_TPQ 0x00bc
#define MACB_USRIO 0x00c0
#define MACB_WOL 0x00c4
#define MACB_MID 0x00fc
#define MACB_TBQPH 0x04C8
#define MACB_RBQPH 0x04D4
/* GEM specific register offsets */
#define GEM_DCFG1 0x0280
#define GEM_DCFG6 0x0294
/* GEM register offsets. */
#define GEM_NCFGR 0x0004 /* Network Config */
#define GEM_USRIO 0x000c /* User IO */
#define GEM_DMACFG 0x0010 /* DMA Configuration */
#define GEM_JML 0x0048 /* Jumbo Max Length */
#define GEM_HRB 0x0080 /* Hash Bottom */
#define GEM_HRT 0x0084 /* Hash Top */
#define GEM_SA1B 0x0088 /* Specific1 Bottom */
#define GEM_SA1T 0x008C /* Specific1 Top */
#define GEM_SA2B 0x0090 /* Specific2 Bottom */
#define GEM_SA2T 0x0094 /* Specific2 Top */
#define GEM_SA3B 0x0098 /* Specific3 Bottom */
#define GEM_SA3T 0x009C /* Specific3 Top */
#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
#define GEM_SA4T 0x00A4 /* Specific4 Top */
#define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
#define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
#define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
#define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
#define GEM_OTX 0x0100 /* Octets transmitted */
#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
#define GEM_ORX 0x0150 /* Octets received */
#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
#define GEM_RXCNT 0x0158 /* Frames Received Counter */
#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
#define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
#define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
#define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
#define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
#define GEM_TA 0x01d8 /* 1588 Timer Adjust */
#define GEM_TI 0x01dc /* 1588 Timer Increment */
#define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
#define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
#define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
#define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
#define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
#define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
#define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
#define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
#define GEM_DCFG1 0x0280 /* Design Config 1 */
#define GEM_DCFG2 0x0284 /* Design Config 2 */
#define GEM_DCFG3 0x0288 /* Design Config 3 */
#define GEM_DCFG4 0x028c /* Design Config 4 */
#define GEM_DCFG5 0x0290 /* Design Config 5 */
#define GEM_DCFG6 0x0294 /* Design Config 6 */
#define GEM_DCFG7 0x0298 /* Design Config 7 */
#define GEM_DCFG8 0x029C /* Design Config 8 */
#define GEM_DCFG10 0x02A4 /* Design Config 10 */
#define MACB_MAX_QUEUES 8
#define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
#define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
/* GEM specific multi queues register offset */
/* hw_q can be 0~7 */
#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
/* Screener Type 2 match registers */
#define GEM_SCRT2 0x540
/* EtherType registers */
#define GEM_ETHT 0x06E0
/* Type 2 compare registers */
#define GEM_T2CMPW0 0x0700
#define GEM_T2CMPW1 0x0704
#define T2CMP_OFST(t2idx) (t2idx * 2)
/* type 2 compare registers
* each location requires 3 compare regs
*/
#define GEM_IP4SRC_CMP(idx) (idx * 3)
#define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
#define GEM_PORT_CMP(idx) (idx * 3 + 2)
/* Which screening type 2 EtherType register will be used (0 - 7) */
#define SCRT2_ETHT 0
#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
#define GEM_TBQPH(hw_q) (0x04C8)
#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
#define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
#define GEM_RBQPH(hw_q) (0x04D4)
#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
#define MACB_LLB_OFFSET 1
#define MACB_LLB_SIZE 1
#define MACB_RE_OFFSET 2
#define MACB_RE_SIZE 1
#define MACB_TE_OFFSET 3
#define MACB_TE_SIZE 1
#define MACB_MPE_OFFSET 4
#define MACB_MPE_SIZE 1
#define MACB_CLRSTAT_OFFSET 5
#define MACB_CLRSTAT_SIZE 1
#define MACB_INCSTAT_OFFSET 6
#define MACB_INCSTAT_SIZE 1
#define MACB_WESTAT_OFFSET 7
#define MACB_WESTAT_SIZE 1
#define MACB_BP_OFFSET 8
#define MACB_BP_SIZE 1
#define MACB_TSTART_OFFSET 9
#define MACB_TSTART_SIZE 1
#define MACB_THALT_OFFSET 10
#define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11
#define MACB_NCR_TPF_SIZE 1
#define MACB_TZQ_OFFSET 12
#define MACB_TZQ_SIZE 1
#define MACB_LB_OFFSET 0 /* reserved */
#define MACB_LB_SIZE 1
#define MACB_LLB_OFFSET 1 /* Loop back local */
#define MACB_LLB_SIZE 1
#define MACB_RE_OFFSET 2 /* Receive enable */
#define MACB_RE_SIZE 1
#define MACB_TE_OFFSET 3 /* Transmit enable */
#define MACB_TE_SIZE 1
#define MACB_MPE_OFFSET 4 /* Management port enable */
#define MACB_MPE_SIZE 1
#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
#define MACB_CLRSTAT_SIZE 1
#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
#define MACB_INCSTAT_SIZE 1
#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
#define MACB_WESTAT_SIZE 1
#define MACB_BP_OFFSET 8 /* Back pressure */
#define MACB_BP_SIZE 1
#define MACB_TSTART_OFFSET 9 /* Start transmission */
#define MACB_TSTART_SIZE 1
#define MACB_THALT_OFFSET 10 /* Transmit halt */
#define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
#define MACB_NCR_TPF_SIZE 1
#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
#define MACB_TZQ_SIZE 1
#define MACB_SRTSM_OFFSET 15
#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
#define MACB_OSSMODE_SIZE 1
/* Bitfields in NCFGR */
#define MACB_SPD_OFFSET 0
#define MACB_SPD_SIZE 1
#define MACB_FD_OFFSET 1
#define MACB_FD_SIZE 1
#define MACB_BIT_RATE_OFFSET 2
#define MACB_BIT_RATE_SIZE 1
#define MACB_JFRAME_OFFSET 3
#define MACB_JFRAME_SIZE 1
#define MACB_CAF_OFFSET 4
#define MACB_CAF_SIZE 1
#define MACB_NBC_OFFSET 5
#define MACB_NBC_SIZE 1
#define MACB_NCFGR_MTI_OFFSET 6
#define MACB_NCFGR_MTI_SIZE 1
#define MACB_UNI_OFFSET 7
#define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8
#define MACB_BIG_SIZE 1
#define MACB_EAE_OFFSET 9
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
#define MACB_RTY_OFFSET 12
#define MACB_RTY_SIZE 1
#define MACB_PAE_OFFSET 13
#define MACB_PAE_SIZE 1
#define MACB_RBOF_OFFSET 14
#define MACB_RBOF_SIZE 2
#define MACB_RLCE_OFFSET 16
#define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17
#define MACB_DRFCS_SIZE 1
#define MACB_EFRHD_OFFSET 18
#define MACB_EFRHD_SIZE 1
#define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1
#define MACB_SPD_OFFSET 0 /* Speed */
#define MACB_SPD_SIZE 1
#define MACB_FD_OFFSET 1 /* Full duplex */
#define MACB_FD_SIZE 1
#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
#define MACB_BIT_RATE_SIZE 1
#define MACB_JFRAME_OFFSET 3 /* reserved */
#define MACB_JFRAME_SIZE 1
#define MACB_CAF_OFFSET 4 /* Copy all frames */
#define MACB_CAF_SIZE 1
#define MACB_NBC_OFFSET 5 /* No broadcast */
#define MACB_NBC_SIZE 1
#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
#define MACB_NCFGR_MTI_SIZE 1
#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
#define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
#define MACB_BIG_SIZE 1
#define MACB_EAE_OFFSET 9 /* External address match enable */
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
#define MACB_RTY_OFFSET 12 /* Retry test */
#define MACB_RTY_SIZE 1
#define MACB_PAE_OFFSET 13 /* Pause enable */
#define MACB_PAE_SIZE 1
#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
#define MACB_RBOF_SIZE 2
#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
#define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17 /* FCS remove */
#define MACB_DRFCS_SIZE 1
#define MACB_EFRHD_OFFSET 18
#define MACB_EFRHD_SIZE 1
#define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1
/* GEM specific NCFGR bitfields. */
#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
#define GEM_GBE_SIZE 1
#define GEM_PCSSEL_OFFSET 11
#define GEM_PCSSEL_SIZE 1
#define GEM_CLK_OFFSET 18 /* MDC clock division */
#define GEM_CLK_SIZE 3
#define GEM_DBW_OFFSET 21 /* Data bus width */
#define GEM_DBW_SIZE 2
#define GEM_RXCOEN_OFFSET 24
#define GEM_RXCOEN_SIZE 1
#define GEM_SGMIIEN_OFFSET 27
#define GEM_SGMIIEN_SIZE 1
/* Constants for data bus width. */
#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
/* Bitfields in DMACFG. */
#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
#define GEM_FBLDO_SIZE 5
#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
#define GEM_ENDIA_DESC_SIZE 1
#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
#define GEM_ENDIA_PKT_SIZE 1
#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
#define GEM_RXBMS_SIZE 2
#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
#define GEM_TXPBMS_SIZE 1
#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
#define GEM_TXCOEN_SIZE 1
#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
#define GEM_RXBS_SIZE 8
#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
#define GEM_DDRP_SIZE 1
#define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
#define GEM_RXEXT_SIZE 1
#define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
#define GEM_TXEXT_SIZE 1
#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
#define GEM_ADDR64_SIZE 1
#define GEM_GBE_OFFSET 10
#define GEM_GBE_SIZE 1
#define GEM_CLK_OFFSET 18
#define GEM_CLK_SIZE 3
#define GEM_DBW_OFFSET 21
#define GEM_DBW_SIZE 2
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0
#define MACB_NSR_LINK_SIZE 1
#define MACB_MDIO_OFFSET 1
#define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2
#define MACB_IDLE_SIZE 1
/* Bitfields in UR */
#define GEM_RGMII_OFFSET 0
#define GEM_RGMII_SIZE 1
#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1
#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
#define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
#define MACB_UBR_OFFSET 0
#define MACB_UBR_SIZE 1
#define MACB_COL_OFFSET 1
#define MACB_COL_SIZE 1
#define MACB_TSR_RLE_OFFSET 2
#define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3
#define MACB_TGO_SIZE 1
#define MACB_BEX_OFFSET 4
#define MACB_BEX_SIZE 1
#define MACB_COMP_OFFSET 5
#define MACB_COMP_SIZE 1
#define MACB_UND_OFFSET 6
#define MACB_UND_SIZE 1
#define MACB_UBR_OFFSET 0 /* Used bit read */
#define MACB_UBR_SIZE 1
#define MACB_COL_OFFSET 1 /* Collision occurred */
#define MACB_COL_SIZE 1
#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
#define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3 /* Transmit go */
#define MACB_TGO_SIZE 1
#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
#define MACB_BEX_SIZE 1
#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
#define MACB_COMP_SIZE 1
#define MACB_UND_OFFSET 6 /* Trnasmit under run */
#define MACB_UND_SIZE 1
/* Bitfields in RSR */
#define MACB_BNA_OFFSET 0
#define MACB_BNA_SIZE 1
#define MACB_REC_OFFSET 1
#define MACB_REC_SIZE 1
#define MACB_OVR_OFFSET 2
#define MACB_OVR_SIZE 1
#define MACB_BNA_OFFSET 0 /* Buffer not available */
#define MACB_BNA_SIZE 1
#define MACB_REC_OFFSET 1 /* Frame received */
#define MACB_REC_SIZE 1
#define MACB_OVR_OFFSET 2 /* Receive overrun */
#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
#define MACB_MFD_OFFSET 0
#define MACB_MFD_SIZE 1
#define MACB_RCOMP_OFFSET 1
#define MACB_RCOMP_SIZE 1
#define MACB_RXUBR_OFFSET 2
#define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3
#define MACB_TXUBR_SIZE 1
#define MACB_ISR_TUND_OFFSET 4
#define MACB_ISR_TUND_SIZE 1
#define MACB_ISR_RLE_OFFSET 5
#define MACB_ISR_RLE_SIZE 1
#define MACB_TXERR_OFFSET 6
#define MACB_TXERR_SIZE 1
#define MACB_TCOMP_OFFSET 7
#define MACB_TCOMP_SIZE 1
#define MACB_ISR_LINK_OFFSET 9
#define MACB_ISR_LINK_SIZE 1
#define MACB_ISR_ROVR_OFFSET 10
#define MACB_ISR_ROVR_SIZE 1
#define MACB_HRESP_OFFSET 11
#define MACB_HRESP_SIZE 1
#define MACB_PFR_OFFSET 12
#define MACB_PFR_SIZE 1
#define MACB_PTZ_OFFSET 13
#define MACB_PTZ_SIZE 1
#define MACB_MFD_OFFSET 0 /* Management frame sent */
#define MACB_MFD_SIZE 1
#define MACB_RCOMP_OFFSET 1 /* Receive complete */
#define MACB_RCOMP_SIZE 1
#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
#define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
#define MACB_TXUBR_SIZE 1
#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
#define MACB_ISR_TUND_SIZE 1
#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
#define MACB_ISR_RLE_SIZE 1
#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
#define MACB_TXERR_SIZE 1
#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
#define MACB_TCOMP_SIZE 1
#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
#define MACB_ISR_LINK_SIZE 1
#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
#define MACB_ISR_ROVR_SIZE 1
#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
#define MACB_HRESP_SIZE 1
#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
#define MACB_PFR_SIZE 1
#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
#define MACB_PTZ_SIZE 1
#define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
#define MACB_WOL_SIZE 1
#define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
#define MACB_DRQFR_SIZE 1
#define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
#define MACB_SFR_SIZE 1
#define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
#define MACB_DRQFT_SIZE 1
#define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
#define MACB_SFT_SIZE 1
#define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
#define MACB_PDRQFR_SIZE 1
#define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
#define MACB_PDRSFR_SIZE 1
#define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
#define MACB_PDRQFT_SIZE 1
#define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
#define MACB_PDRSFT_SIZE 1
#define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
#define MACB_SRI_SIZE 1
/* Timer increment fields */
#define MACB_TI_CNS_OFFSET 0
#define MACB_TI_CNS_SIZE 8
#define MACB_TI_ACNS_OFFSET 8
#define MACB_TI_ACNS_SIZE 8
#define MACB_TI_NIT_OFFSET 16
#define MACB_TI_NIT_SIZE 8
/* Bitfields in MAN */
#define MACB_DATA_OFFSET 0
#define MACB_DATA_SIZE 16
#define MACB_CODE_OFFSET 16
#define MACB_CODE_SIZE 2
#define MACB_REGA_OFFSET 18
#define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23
#define MACB_PHYA_SIZE 5
#define MACB_RW_OFFSET 28
#define MACB_RW_SIZE 2
#define MACB_SOF_OFFSET 30
#define MACB_SOF_SIZE 2
#define MACB_DATA_OFFSET 0 /* data */
#define MACB_DATA_SIZE 16
#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
#define MACB_CODE_SIZE 2
#define MACB_REGA_OFFSET 18 /* Register address */
#define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23 /* PHY address */
#define MACB_PHYA_SIZE 5
#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
#define MACB_RW_SIZE 2
#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
#define MACB_SOF_SIZE 2
/* Bitfields in USRIO */
/* Bitfields in USRIO (AVR32) */
#define MACB_MII_OFFSET 0
#define MACB_MII_SIZE 1
#define MACB_EAM_OFFSET 1
@ -232,6 +421,8 @@
/* Bitfields in USRIO (AT91) */
#define MACB_RMII_OFFSET 0
#define MACB_RMII_SIZE 1
#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
#define GEM_RGMII_SIZE 1
#define MACB_CLKEN_OFFSET 1
#define MACB_CLKEN_SIZE 1
@ -249,17 +440,166 @@
/* Bitfields in MID */
#define MACB_IDNUM_OFFSET 16
#define MACB_IDNUM_SIZE 16
#define MACB_IDNUM_SIZE 12
#define MACB_REV_OFFSET 0
#define MACB_REV_SIZE 16
/* Bitfields in DCFG1 */
/* Bitfields in DCFG1. */
#define GEM_IRQCOR_OFFSET 23
#define GEM_IRQCOR_SIZE 1
#define GEM_DBWDEF_OFFSET 25
#define GEM_DBWDEF_SIZE 3
/* constants for data bus width */
#define GEM_DBW32 0
#define GEM_DBW64 1
#define GEM_DBW128 2
/* Bitfields in DCFG2. */
#define GEM_RX_PKT_BUFF_OFFSET 20
#define GEM_RX_PKT_BUFF_SIZE 1
#define GEM_TX_PKT_BUFF_OFFSET 21
#define GEM_TX_PKT_BUFF_SIZE 1
/* Bitfields in DCFG5. */
#define GEM_TSU_OFFSET 8
#define GEM_TSU_SIZE 1
/* Bitfields in DCFG6. */
#define GEM_PBUF_LSO_OFFSET 27
#define GEM_PBUF_LSO_SIZE 1
#define GEM_DAW64_OFFSET 23
#define GEM_DAW64_SIZE 1
/* Bitfields in DCFG8. */
#define GEM_T1SCR_OFFSET 24
#define GEM_T1SCR_SIZE 8
#define GEM_T2SCR_OFFSET 16
#define GEM_T2SCR_SIZE 8
#define GEM_SCR2ETH_OFFSET 8
#define GEM_SCR2ETH_SIZE 8
#define GEM_SCR2CMP_OFFSET 0
#define GEM_SCR2CMP_SIZE 8
/* Bitfields in DCFG10 */
#define GEM_TXBD_RDBUFF_OFFSET 12
#define GEM_TXBD_RDBUFF_SIZE 4
#define GEM_RXBD_RDBUFF_OFFSET 8
#define GEM_RXBD_RDBUFF_SIZE 4
/* Bitfields in TISUBN */
#define GEM_SUBNSINCR_OFFSET 0
#define GEM_SUBNSINCR_SIZE 16
/* Bitfields in TI */
#define GEM_NSINCR_OFFSET 0
#define GEM_NSINCR_SIZE 8
/* Bitfields in TSH */
#define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
#define GEM_TSH_SIZE 16
/* Bitfields in TSL */
#define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
#define GEM_TSL_SIZE 32
/* Bitfields in TN */
#define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
#define GEM_TN_SIZE 30
/* Bitfields in TXBDCTRL */
#define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
#define GEM_TXTSMODE_SIZE 2
/* Bitfields in RXBDCTRL */
#define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
#define GEM_RXTSMODE_SIZE 2
/* Bitfields in SCRT2 */
#define GEM_QUEUE_OFFSET 0 /* Queue Number */
#define GEM_QUEUE_SIZE 4
#define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
#define GEM_VLANPR_SIZE 3
#define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
#define GEM_VLANEN_SIZE 1
#define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
#define GEM_ETHT2IDX_SIZE 3
#define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
#define GEM_ETHTEN_SIZE 1
#define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
#define GEM_CMPA_SIZE 5
#define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
#define GEM_CMPAEN_SIZE 1
#define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
#define GEM_CMPB_SIZE 5
#define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
#define GEM_CMPBEN_SIZE 1
#define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
#define GEM_CMPC_SIZE 5
#define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
#define GEM_CMPCEN_SIZE 1
/* Bitfields in ETHT */
#define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
#define GEM_ETHTCMP_SIZE 16
/* Bitfields in T2CMPW0 */
#define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
#define GEM_T2CMP_SIZE 16
#define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
#define GEM_T2MASK_SIZE 16
/* Bitfields in T2CMPW1 */
#define GEM_T2DISMSK_OFFSET 9 /* disable mask */
#define GEM_T2DISMSK_SIZE 1
#define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
#define GEM_T2CMPOFST_SIZE 2
#define GEM_T2OFST_OFFSET 0 /* offset value */
#define GEM_T2OFST_SIZE 7
/* Offset for screener type 2 compare values (T2CMPOFST).
* Note the offset is applied after the specified point,
* e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
* of 12 bytes from this would be the source IP address in an IP header
*/
#define GEM_T2COMPOFST_SOF 0
#define GEM_T2COMPOFST_ETYPE 1
#define GEM_T2COMPOFST_IPHDR 2
#define GEM_T2COMPOFST_TCPUDP 3
/* offset from EtherType to IP address */
#define ETYPE_SRCIP_OFFSET 12
#define ETYPE_DSTIP_OFFSET 16
/* offset from IP header to port */
#define IPHDR_SRCPORT_OFFSET 0
#define IPHDR_DSTPORT_OFFSET 2
/* Transmit DMA buffer descriptor Word 1 */
#define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
#define GEM_DMA_TXVALID_SIZE 1
/* Receive DMA buffer descriptor Word 0 */
#define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
#define GEM_DMA_RXVALID_SIZE 1
/* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
#define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
#define GEM_DMA_SECL_SIZE 2
#define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
#define GEM_DMA_NSEC_SIZE 30
/* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
/* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
* Old hardware supports only 6 bit precision but it is enough for PTP.
* Less accuracy is used always instead of checking hardware version.
*/
#define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
#define GEM_DMA_SECH_SIZE 4
#define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
#define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
#define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
/* Bitfields in ADJ */
#define GEM_ADDSUB_OFFSET 31
#define GEM_ADDSUB_SIZE 1
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
@ -273,6 +613,8 @@
#define GEM_CLK_DIV48 3
#define GEM_CLK_DIV64 4
#define GEM_CLK_DIV96 5
#define GEM_CLK_DIV128 6
#define GEM_CLK_DIV224 7
/* Constants for MAN register */
#define MACB_MAN_SOF 1
@ -280,19 +622,38 @@
#define MACB_MAN_READ 2
#define MACB_MAN_CODE 2
/* Capability mask bits */
#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
#define MACB_CAPS_USRIO_DISABLED 0x00000010
#define MACB_CAPS_JUMBO 0x00000020
#define MACB_CAPS_GEM_HAS_PTP 0x00000040
#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
#define MACB_CAPS_FIFO_MODE 0x10000000
#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
#define MACB_CAPS_SG_DISABLED 0x40000000
#define MACB_CAPS_MACB_IS_GEM 0x80000000
/* LSO settings */
#define MACB_LSO_UFO_ENABLE 0x01
#define MACB_LSO_TSO_ENABLE 0x02
/* Bit manipulation macros */
#define MACB_BIT(name) \
(1 << MACB_##name##_OFFSET)
#define MACB_BF(name, value) \
#define MACB_BF(name,value) \
(((value) & ((1 << MACB_##name##_SIZE) - 1)) \
<< MACB_##name##_OFFSET)
#define MACB_BFEXT(name, value)\
#define MACB_BFEXT(name,value)\
(((value) >> MACB_##name##_OFFSET) \
& ((1 << MACB_##name##_SIZE) - 1))
#define MACB_BFINS(name, value, old) \
#define MACB_BFINS(name,value,old) \
(((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
<< MACB_##name##_OFFSET)) \
| MACB_BF(name, value))
| MACB_BF(name,value))
#define GEM_BIT(name) \
(1 << GEM_##name##_OFFSET)
@ -316,6 +677,95 @@
readl((port)->regs + GEM_##reg)
#define gem_writel(port, reg, value) \
writel((value), (port)->regs + GEM_##reg)
/* DMA descriptor bitfields */
#define MACB_RX_USED_OFFSET 0
#define MACB_RX_USED_SIZE 1
#define MACB_RX_WRAP_OFFSET 1
#define MACB_RX_WRAP_SIZE 1
#define MACB_RX_WADDR_OFFSET 2
#define MACB_RX_WADDR_SIZE 30
#define MACB_RX_FRMLEN_OFFSET 0
#define MACB_RX_FRMLEN_SIZE 12
#define MACB_RX_OFFSET_OFFSET 12
#define MACB_RX_OFFSET_SIZE 2
#define MACB_RX_SOF_OFFSET 14
#define MACB_RX_SOF_SIZE 1
#define MACB_RX_EOF_OFFSET 15
#define MACB_RX_EOF_SIZE 1
#define MACB_RX_CFI_OFFSET 16
#define MACB_RX_CFI_SIZE 1
#define MACB_RX_VLAN_PRI_OFFSET 17
#define MACB_RX_VLAN_PRI_SIZE 3
#define MACB_RX_PRI_TAG_OFFSET 20
#define MACB_RX_PRI_TAG_SIZE 1
#define MACB_RX_VLAN_TAG_OFFSET 21
#define MACB_RX_VLAN_TAG_SIZE 1
#define MACB_RX_TYPEID_MATCH_OFFSET 22
#define MACB_RX_TYPEID_MATCH_SIZE 1
#define MACB_RX_SA4_MATCH_OFFSET 23
#define MACB_RX_SA4_MATCH_SIZE 1
#define MACB_RX_SA3_MATCH_OFFSET 24
#define MACB_RX_SA3_MATCH_SIZE 1
#define MACB_RX_SA2_MATCH_OFFSET 25
#define MACB_RX_SA2_MATCH_SIZE 1
#define MACB_RX_SA1_MATCH_OFFSET 26
#define MACB_RX_SA1_MATCH_SIZE 1
#define MACB_RX_EXT_MATCH_OFFSET 28
#define MACB_RX_EXT_MATCH_SIZE 1
#define MACB_RX_UHASH_MATCH_OFFSET 29
#define MACB_RX_UHASH_MATCH_SIZE 1
#define MACB_RX_MHASH_MATCH_OFFSET 30
#define MACB_RX_MHASH_MATCH_SIZE 1
#define MACB_RX_BROADCAST_OFFSET 31
#define MACB_RX_BROADCAST_SIZE 1
#define MACB_RX_FRMLEN_MASK 0xFFF
#define MACB_RX_JFRMLEN_MASK 0x3FFF
/* RX checksum offload disabled: bit 24 clear in NCFGR */
#define GEM_RX_TYPEID_MATCH_OFFSET 22
#define GEM_RX_TYPEID_MATCH_SIZE 2
/* RX checksum offload enabled: bit 24 set in NCFGR */
#define GEM_RX_CSUM_OFFSET 22
#define GEM_RX_CSUM_SIZE 2
#define MACB_TX_FRMLEN_OFFSET 0
#define MACB_TX_FRMLEN_SIZE 11
#define MACB_TX_LAST_OFFSET 15
#define MACB_TX_LAST_SIZE 1
#define MACB_TX_NOCRC_OFFSET 16
#define MACB_TX_NOCRC_SIZE 1
#define MACB_MSS_MFS_OFFSET 16
#define MACB_MSS_MFS_SIZE 14
#define MACB_TX_LSO_OFFSET 17
#define MACB_TX_LSO_SIZE 2
#define MACB_TX_TCP_SEQ_SRC_OFFSET 19
#define MACB_TX_TCP_SEQ_SRC_SIZE 1
#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
#define MACB_TX_BUF_EXHAUSTED_SIZE 1
#define MACB_TX_UNDERRUN_OFFSET 28
#define MACB_TX_UNDERRUN_SIZE 1
#define MACB_TX_ERROR_OFFSET 29
#define MACB_TX_ERROR_SIZE 1
#define MACB_TX_WRAP_OFFSET 30
#define MACB_TX_WRAP_SIZE 1
#define MACB_TX_USED_OFFSET 31
#define MACB_TX_USED_SIZE 1
#define GEM_TX_FRMLEN_OFFSET 0
#define GEM_TX_FRMLEN_SIZE 14
/* Buffer descriptor constants */
#define GEM_RX_CSUM_NONE 0
#define GEM_RX_CSUM_IP_ONLY 1
#define GEM_RX_CSUM_IP_TCP 2
#define GEM_RX_CSUM_IP_UDP 3
/* limit RX checksum offload to TCP and UDP packets */
#define GEM_RX_CSUM_CHECKED_MASK 2
#define gem_writel_queue_TBQP(port, value, queue_num) \
writel((value), (port)->regs + GEM_TBQP(queue_num))

29
drivers/net/sun8i_emac.c
View File

@ -846,31 +846,44 @@ static const struct eth_ops sun8i_emac_eth_ops = {
static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
{
int node, ret;
int emac_node, ephy_node, ret, ephy_handle;
emac_node = fdt_path_offset(gd->fdt_blob,
"/soc/ethernet@1c30000");
if (emac_node < 0) {
debug("failed to get emac node\n");
return emac_node;
}
ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
emac_node, "phy-handle");
/* look for mdio-mux node for internal PHY node */
node = fdt_path_offset(gd->fdt_blob,
"/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
if (node < 0) {
ephy_node = fdt_path_offset(gd->fdt_blob,
"/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
if (ephy_node < 0) {
debug("failed to get mdio-mux with internal PHY\n");
return node;
return ephy_node;
}
ret = fdt_node_check_compatible(gd->fdt_blob, node,
/* This is not the phy we are looking for */
if (ephy_node != ephy_handle)
return 0;
ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
"allwinner,sun8i-h3-mdio-internal");
if (ret < 0) {
debug("failed to find mdio-internal node\n");
return ret;
}
ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0,
ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
&priv->ephy_clk);
if (ret) {
dev_err(dev, "failed to get EPHY TX clock\n");
return ret;
}
ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0,
ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
&priv->ephy_rst);
if (ret) {
dev_err(dev, "failed to get EPHY TX reset\n");

77
drivers/net/ti/davinci_emac.c
View File

@ -26,7 +26,6 @@
#include <net.h>
#include <miiphy.h>
#include <malloc.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/arch/emac_defs.h>
#include <asm/io.h>
@ -107,8 +106,9 @@ static u_int8_t num_phy;
phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT];
static int davinci_eth_set_mac_addr(struct eth_device *dev)
static int davinci_emac_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
unsigned long mac_hi;
unsigned long mac_lo;
@ -118,12 +118,12 @@ static int davinci_eth_set_mac_addr(struct eth_device *dev)
* Using channel 0 only - other channels are disabled
* */
writel(0, &adap_emac->MACINDEX);
mac_hi = (dev->enetaddr[3] << 24) |
(dev->enetaddr[2] << 16) |
(dev->enetaddr[1] << 8) |
(dev->enetaddr[0]);
mac_lo = (dev->enetaddr[5] << 8) |
(dev->enetaddr[4]);
mac_hi = (pdata->enetaddr[3] << 24) |
(pdata->enetaddr[2] << 16) |
(pdata->enetaddr[1] << 8) |
(pdata->enetaddr[0]);
mac_lo = (pdata->enetaddr[5] << 8) |
(pdata->enetaddr[4]);
writel(mac_hi, &adap_emac->MACADDRHI);
#if defined(DAVINCI_EMAC_VERSION2)
@ -411,7 +411,7 @@ static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr)
}
/* Eth device open */
static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
static int davinci_emac_start(struct udevice *dev)
{
dv_reg_p addr;
u_int32_t clkdiv, cnt, mac_control;
@ -447,7 +447,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)
writel(1, &adap_emac->TXCONTROL);
writel(1, &adap_emac->RXCONTROL);
davinci_eth_set_mac_addr(dev);
davinci_emac_write_hwaddr(dev);
/* Set DMA 8 TX / 8 RX Head pointers to 0 */
addr = &adap_emac->TX0HDP;
@ -588,7 +588,7 @@ static void davinci_eth_ch_teardown(int ch)
}
/* Eth device close */
static void davinci_eth_close(struct eth_device *dev)
static void davinci_emac_stop(struct udevice *dev)
{
debug_emac("+ emac_close\n");
@ -619,8 +619,8 @@ static int tx_send_loop = 0;
* This function sends a single packet on the network and returns
* positive number (number of bytes transmitted) or negative for error
*/
static int davinci_eth_send_packet (struct eth_device *dev,
void *packet, int length)
static int davinci_emac_send(struct udevice *dev,
void *packet, int length)
{
int ret_status = -1;
int index;
@ -672,7 +672,7 @@ static int davinci_eth_send_packet (struct eth_device *dev,
/*
* This function handles receipt of a packet from the network
*/
static int davinci_eth_rcv_packet (struct eth_device *dev)
static int davinci_emac_recv(struct udevice *dev, int flags, uchar **packetp)
{
volatile emac_desc *rx_curr_desc;
volatile emac_desc *curr_desc;
@ -682,6 +682,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
rx_curr_desc = emac_rx_active_head;
if (!rx_curr_desc)
return 0;
*packetp = rx_curr_desc->buffer;
status = rx_curr_desc->pkt_flag_len;
if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) {
if (status & EMAC_CPPI_RX_ERROR_FRAME) {
@ -693,7 +694,6 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
rx_curr_desc->buff_off_len & 0xffff;
invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN));
net_process_received_packet(rx_curr_desc->buffer, len);
ret = len;
}
@ -742,6 +742,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
}
return (ret);
}
return (0);
}
@ -750,30 +751,12 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)
* EMAC modules power or pin multiplexors, that is done by board_init()
* much earlier in bootup process. Returns 1 on success, 0 otherwise.
*/
int davinci_emac_initialize(void)
static int davinci_emac_probe(struct udevice *dev)
{
u_int32_t phy_id;
u_int16_t tmp;
int i;
int ret;
struct eth_device *dev;
dev = malloc(sizeof *dev);
if (dev == NULL)
return -1;
memset(dev, 0, sizeof *dev);
strcpy(dev->name, "DaVinci-EMAC");
dev->iobase = 0;
dev->init = davinci_eth_open;
dev->halt = davinci_eth_close;
dev->send = davinci_eth_send_packet;
dev->recv = davinci_eth_rcv_packet;
dev->write_hwaddr = davinci_eth_set_mac_addr;
eth_register(dev);
davinci_eth_mdio_enable();
@ -854,5 +837,29 @@ int davinci_emac_initialize(void)
phy[i].auto_negotiate(i);
}
#endif
return(1);
return 0;
}
static const struct eth_ops davinci_emac_ops = {
.start = davinci_emac_start,
.send = davinci_emac_send,
.recv = davinci_emac_recv,
.stop = davinci_emac_stop,
.write_hwaddr = davinci_emac_write_hwaddr,
};
static const struct udevice_id davinci_emac_ids[] = {
{ .compatible = "ti,davinci-dm6467-emac" },
{ .compatible = "ti,am3517-emac", },
{ .compatible = "ti,dm816-emac", },
{ }
};
U_BOOT_DRIVER(davinci_emac) = {
.name = "davinci_emac",
.id = UCLASS_ETH,
.of_match = davinci_emac_ids,
.probe = davinci_emac_probe,
.ops = &davinci_emac_ops,
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
};

59
drivers/net/tsec.c
View File

@ -259,8 +259,8 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
u16 status;
int result = 0;
u16 status;
int i;
/* Find an empty buffer descriptor */
@ -268,7 +268,7 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx buffers full\n", dev->name);
printf("%s: tsec: tx buffers full\n", dev->name);
return result;
}
}
@ -287,7 +287,7 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
i++) {
if (i >= TOUT_LOOP) {
debug("%s: tsec: tx error\n", dev->name);
printf("%s: tsec: tx error\n", dev->name);
return result;
}
}
@ -560,6 +560,8 @@ static int tsec_init(struct udevice *dev)
struct tsec_private *priv = (struct tsec_private *)dev->priv;
#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_platdata(dev);
#else
struct eth_device *pdata = dev;
#endif
struct tsec __iomem *regs = priv->regs;
u32 tempval;
@ -580,21 +582,12 @@ static int tsec_init(struct udevice *dev)
* order (BE), MACnADDR1 is set to 0xCDAB7856 and
* MACnADDR2 is set to 0x34120000.
*/
#ifndef CONFIG_DM_ETH
tempval = (dev->enetaddr[5] << 24) | (dev->enetaddr[4] << 16) |
(dev->enetaddr[3] << 8) | dev->enetaddr[2];
#else
tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
(pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
#endif
out_be32(&regs->macstnaddr1, tempval);
#ifndef CONFIG_DM_ETH
tempval = (dev->enetaddr[1] << 24) | (dev->enetaddr[0] << 16);
#else
tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
#endif
out_be32(&regs->macstnaddr2, tempval);
@ -708,9 +701,9 @@ static int init_phy(struct tsec_private *priv)
*/
static int tsec_initialize(bd_t *bis, struct tsec_info_struct *tsec_info)
{
struct tsec_private *priv;
struct eth_device *dev;
int i;
struct tsec_private *priv;
dev = (struct eth_device *)malloc(sizeof(*dev));
@ -794,12 +787,14 @@ int tsec_standard_init(bd_t *bis)
#else /* CONFIG_DM_ETH */
int tsec_probe(struct udevice *dev)
{
struct tsec_private *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
struct fsl_pq_mdio_info mdio_info;
struct tsec_private *priv = dev_get_priv(dev);
struct ofnode_phandle_args phandle_args;
ofnode parent;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct fsl_pq_mdio_info mdio_info;
const char *phy_mode;
fdt_addr_t reg;
ofnode parent;
int ret;
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
@ -807,7 +802,7 @@ int tsec_probe(struct udevice *dev)
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
debug("phy-handle does not exist under tsec %s\n", dev->name);
printf("phy-handle does not exist under tsec %s\n", dev->name);
return -ENOENT;
} else {
int reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
@ -816,29 +811,27 @@ int tsec_probe(struct udevice *dev)
}
parent = ofnode_get_parent(phandle_args.node);
if (ofnode_valid(parent)) {
int reg = ofnode_get_addr_index(parent, 0);
priv->phyregs_sgmii = (struct tsec_mii_mng *)reg;
} else {
debug("No parent node for PHY?\n");
if (!ofnode_valid(parent)) {
printf("No parent node for PHY?\n");
return -ENOENT;
}
if (dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
&phandle_args)) {
priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
} else {
int reg = ofnode_read_u32_default(phandle_args.node, "reg",
CONFIG_SYS_TBIPA_VALUE);
priv->tbiaddr = reg;
}
reg = ofnode_get_addr_index(parent, 0);
priv->phyregs_sgmii = (struct tsec_mii_mng *)
(reg + TSEC_MDIO_REGS_OFFSET);
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
&phandle_args);
if (ret == 0)
ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
priv->tbiaddr = tbiaddr;
phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
if (phy_mode)
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
if (pdata->phy_interface == -1) {
debug("Invalid PHY interface '%s'\n", phy_mode);
printf("Invalid PHY interface '%s'\n", phy_mode);
return -EINVAL;
}
priv->interface = pdata->phy_interface;
@ -887,7 +880,7 @@ static const struct eth_ops tsec_ops = {
};
static const struct udevice_id tsec_ids[] = {
{ .compatible = "fsl,tsec" },
{ .compatible = "fsl,etsec2" },
{ }
};

250
include/configs/ls1021atsn.h Normal file
View File

@ -0,0 +1,250 @@
/* SPDX-License-Identifier: GPL-2.0
* Copyright 2016-2018 NXP Semiconductors
* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
#define CONFIG_SYS_FSL_CLK
#define CONFIG_DEEP_SLEEP
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/* XHCI Support - enabled by default */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
#define DDR_SDRAM_CFG 0x470c0008
#define DDR_CS0_BNDS 0x008000bf
#define DDR_CS0_CONFIG 0x80014302
#define DDR_TIMING_CFG_0 0x50550004
#define DDR_TIMING_CFG_1 0xbcb38c56
#define DDR_TIMING_CFG_2 0x0040d120
#define DDR_TIMING_CFG_3 0x010e1000
#define DDR_TIMING_CFG_4 0x00000001
#define DDR_TIMING_CFG_5 0x03401400
#define DDR_SDRAM_CFG_2 0x00401010
#define DDR_SDRAM_MODE 0x00061c60
#define DDR_SDRAM_MODE_2 0x00180000
#define DDR_SDRAM_INTERVAL 0x18600618
#define DDR_DDR_WRLVL_CNTL 0x8655f605
#define DDR_DDR_WRLVL_CNTL_2 0x05060607
#define DDR_DDR_WRLVL_CNTL_3 0x05050505
#define DDR_DDR_CDR1 0x80040000
#define DDR_DDR_CDR2 0x00000001
#define DDR_SDRAM_CLK_CNTL 0x02000000
#define DDR_DDR_ZQ_CNTL 0x89080600
#define DDR_CS0_CONFIG_2 0
#define DDR_SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG2_D_INIT 0x00000010
#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
#define SDRAM_CFG2_FRC_SR 0x80000000
#define SDRAM_CFG_BI 0x00000001
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI \
"board/freescale/ls1021atsn/ls102xa_pbi.cfg"
#endif
#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_FSL_PBL_RCW \
"board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
#endif /* ifdef CONFIG_SECURE_BOOT */
#define CONFIG_SPL_MAX_SIZE 0x1a000
#define CONFIG_SPL_STACK 0x1001d000
#define CONFIG_SPL_PAD_TO 0x1c000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#ifdef CONFIG_U_BOOT_HDR_SIZE
/*
* HDR would be appended at end of image and copied to DDR along
* with U-Boot image. Here u-boot max. size is 512K. So if binary
* size increases then increase this size in case of secure boot as
* it uses raw U-Boot image instead of FIT image.
*/
#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
#else
#define CONFIG_SYS_MONITOR_LEN 0x100000
#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x80000000
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#ifndef CONFIG_DM_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#endif
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_BAUDRATE 115200
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* QSPI */
#define FSL_QSPI_FLASH_SIZE (1 << 24)
#define FSL_QSPI_FLASH_NUM 2
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#ifdef CONFIG_PCI
#define CONFIG_PCI_SCAN_SHOW
#endif
#define CONFIG_LAYERSCAPE_NS_ACCESS
#define COUNTER_FREQUENCY 12500000
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 256
#define CONFIG_FSL_DEVICE_DISABLE
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(USB, usb, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
"initrd_high=0xffffffff\0" \
"fdt_high=0xffffffff\0" \
"fdt_addr=0x64f00000\0" \
"kernel_addr=0x61000000\0" \
"kernelheader_addr=0x60800000\0" \
"scriptaddr=0x80000000\0" \
"scripthdraddr=0x80080000\0" \
"fdtheader_addr_r=0x80100000\0" \
"kernelheader_addr_r=0x80200000\0" \
"kernel_addr_r=0x80008000\0" \
"kernelheader_size=0x40000\0" \
"fdt_addr_r=0x8f000000\0" \
"ramdisk_addr_r=0xa0000000\0" \
"load_addr=0x80008000\0" \
"kernel_size=0x2800000\0" \
"kernel_addr_sd=0x8000\0" \
"kernel_size_sd=0x14000\0" \
"kernelhdr_addr_sd=0x4000\0" \
"kernelhdr_size_sd=0x10\0" \
BOOTENV \
"boot_scripts=ls1021atsn_boot.scr\0" \
"boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; " \
"for distro_bootpart in ${devplist}; do " \
"if fstype ${devtype} " \
"${devnum}:${distro_bootpart} " \
"bootfstype; then " \
"run scan_dev_for_boot; " \
"fi; " \
"done\0" \
"scan_dev_for_boot=" \
"echo Scanning ${devtype} " \
"${devnum}:${distro_bootpart}...; " \
"for prefix in ${boot_prefixes}; do " \
"run scan_dev_for_scripts; " \
"run scan_dev_for_extlinux; " \
"done;" \
"\0" \
"boot_a_script=" \
"load ${devtype} ${devnum}:${distro_bootpart} " \
"${scriptaddr} ${prefix}${script}; " \
"env exists secureboot && load ${devtype} " \
"${devnum}:${distro_bootpart} " \
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
"&& esbc_validate ${scripthdraddr};" \
"source ${scriptaddr}\0" \
"qspi_bootcmd=echo Trying load from qspi..;" \
"sf probe && sf read $load_addr " \
"$kernel_addr $kernel_size; env exists secureboot " \
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
"bootm $load_addr#$board\0" \
"sd_bootcmd=echo Trying load from SD ..;" \
"mmcinfo && mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd && " \
"env exists secureboot && mmc read $kernelheader_addr_r " \
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$board\0"
/* Miscellaneous configurable options */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_LS102XA_STREAM_ID
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif
/* Environment */
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SD_BOOT)
#define CONFIG_ENV_OFFSET 0x300000
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x20000
#elif defined(CONFIG_QSPI_BOOT)
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_OFFSET 0x300000
#define CONFIG_ENV_SECT_SIZE 0x40000
#endif
#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
#endif

30
include/configs/ls1021atwr.h
View File

@ -260,33 +260,7 @@
*/
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII_DEFAULT_TSEC 1
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_ATHEROS
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_ETHPRIME "ethernet@2d10000"
#endif
/* PCIe */
@ -444,7 +418,7 @@
#undef CONFIG_BOOTCOMMAND
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
"env exists secureboot && esbc_halt"
#elif defined(CONFIG_SD_BOOT)
#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \

4
include/configs/ls1028a_common.h
View File

@ -194,4 +194,8 @@
#include <asm/fsl_secure_boot.h>
#endif
/* Ethernet */
/* smallest ENETC BD ring has 8 entries */
#define CONFIG_SYS_RX_ETH_BUFFER 8
#endif /* __L1028A_COMMON_H */

18
include/configs/sifive-fu540.h
View File

@ -18,12 +18,12 @@
#define CONFIG_SYS_MALLOC_LEN SZ_8M
#define CONFIG_SYS_BOOTM_LEN SZ_16M
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
/* Environment options */
#define CONFIG_ENV_SIZE SZ_4K
#define CONFIG_ENV_SIZE SZ_128K
#define BOOT_TARGET_DEVICES(func) \
func(DHCP, dhcp, na)
@ -33,11 +33,15 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffffffffffff\0" \
"initrd_high=0xffffffffffffffff\0" \
"kernel_addr_r=0x80600000\0" \
"fdt_addr_r=0x82200000\0" \
"scriptaddr=0x82300000\0" \
"pxefile_addr_r=0x82400000\0" \
"ramdisk_addr_r=0x82500000\0" \
"kernel_addr_r=0x84000000\0" \
"fdt_addr_r=0x88000000\0" \
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
BOOTENV
#define CONFIG_PREBOOT \
"setenv fdt_addr ${fdtcontroladdr};" \
"fdt addr ${fdtcontroladdr};"
#endif /* __CONFIG_H */

1
include/netdev.h
View File

@ -30,7 +30,6 @@ int bcm_sf2_eth_register(bd_t *bis, u8 dev_num);
int bfin_EMAC_initialize(bd_t *bis);
int calxedaxgmac_initialize(u32 id, ulong base_addr);
int cs8900_initialize(u8 dev_num, int base_addr);
int davinci_emac_initialize(void);
int dc21x4x_initialize(bd_t *bis);
int designware_initialize(ulong base_addr, u32 interface);
int dm9000_initialize(bd_t *bis);

4
include/tsec.h
View File

@ -17,6 +17,8 @@
#include <config.h>
#include <phy.h>
#define TSEC_MDIO_REGS_OFFSET 0x520
#ifndef CONFIG_DM_ETH
#ifdef CONFIG_ARCH_LS1021A
@ -27,7 +29,7 @@
#define TSEC_MDIO_OFFSET 0x01000
#endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET)
#define TSEC_GET_REGS(num, offset) \
(struct tsec __iomem *)\