rockchip: pinctrl: Add a full pinctrl driver
We can make use of the device tree to configure pinctrl settings. Add this support for the driver so we can use it in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
parent
342999f9b3
commit
bea705c993
@ -24,8 +24,103 @@ DECLARE_GLOBAL_DATA_PTR;
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struct rk3288_pinctrl_priv {
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struct rk3288_grf *grf;
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struct rk3288_pmu *pmu;
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int num_banks;
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};
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/**
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* Encode variants of iomux registers into a type variable
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*/
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#define IOMUX_GPIO_ONLY BIT(0)
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#define IOMUX_WIDTH_4BIT BIT(1)
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#define IOMUX_SOURCE_PMU BIT(2)
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#define IOMUX_UNROUTED BIT(3)
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/**
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* @type: iomux variant using IOMUX_* constants
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following iomux registers.
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*/
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struct rockchip_iomux {
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u8 type;
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s16 offset;
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};
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/**
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* @reg: register offset of the gpio bank
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* @nr_pins: number of pins in this bank
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* @bank_num: number of the bank, to account for holes
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* @name: name of the bank
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* @iomux: array describing the 4 iomux sources of the bank
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*/
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struct rockchip_pin_bank {
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u16 reg;
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u8 nr_pins;
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u8 bank_num;
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char *name;
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struct rockchip_iomux iomux[4];
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};
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#define PIN_BANK(id, pins, label) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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{ .offset = -1 }, \
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}, \
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}
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#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
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{ \
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.bank_num = id, \
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.nr_pins = pins, \
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.name = label, \
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.iomux = { \
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{ .type = iom0, .offset = -1 }, \
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{ .type = iom1, .offset = -1 }, \
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{ .type = iom2, .offset = -1 }, \
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{ .type = iom3, .offset = -1 }, \
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}, \
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}
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#ifndef CONFIG_SPL_BUILD
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static struct rockchip_pin_bank rk3288_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_UNROUTED
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),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
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IOMUX_UNROUTED,
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IOMUX_UNROUTED,
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0
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),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
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PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0,
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0
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),
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PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
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0,
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0,
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IOMUX_UNROUTED
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),
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PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
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PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
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0,
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IOMUX_WIDTH_4BIT,
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IOMUX_UNROUTED
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),
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PIN_BANK(8, 16, "gpio8"),
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};
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#endif
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static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
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{
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switch (pwm_id) {
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@ -410,7 +505,106 @@ static int rk3288_pinctrl_set_state_simple(struct udevice *dev,
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return rk3288_pinctrl_request(dev, func, 0);
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}
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#ifndef CONFIG_SPL_BUILD
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static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index,
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int muxval, int flags)
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{
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struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
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struct rockchip_pin_bank *bank = &rk3288_pin_banks[banknum];
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uint shift, muxnum, ind = index;
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u32 *addr;
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debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags);
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for (muxnum = 0; muxnum < 4; muxnum++) {
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struct rockchip_iomux *mux = &bank->iomux[muxnum];
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uint mask;
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if (ind >= 8) {
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ind -= 8;
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continue;
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}
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if (mux->type & IOMUX_SOURCE_PMU)
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addr = priv->pmu->gpio0_iomux;
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else
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addr = (u32 *)priv->grf - 4;
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addr += mux->offset;
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shift = ind & 7;
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if (mux->type & IOMUX_WIDTH_4BIT) {
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mask = 0xf;
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shift *= 4;
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if (shift >= 16) {
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shift -= 16;
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addr++;
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}
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} else {
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mask = 3;
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shift *= 2;
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}
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debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr,
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mask, shift);
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rk_clrsetreg(addr, mask << shift, muxval << shift);
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break;
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}
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if (flags) {
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uint val = 0;
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if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP))
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val = 1;
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else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN))
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val = 2;
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shift = (index & 7) * 2;
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ind = index >> 3;
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if (banknum == 0)
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addr = &priv->pmu->gpio0pull[ind];
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else
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addr = &priv->grf->gpio1_p[banknum - 1][ind];
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debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val,
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shift);
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rk_clrsetreg(addr, 3 << shift, val << shift);
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}
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return 0;
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}
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static int rk3288_pinctrl_set_state(struct udevice *dev, struct udevice *config)
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{
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const void *blob = gd->fdt_blob;
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int pcfg_node, ret, flags, count, i;
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u32 cell[40], *ptr;
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debug("%s: %s %s\n", __func__, dev->name, config->name);
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ret = fdtdec_get_int_array_count(blob, config->of_offset,
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"rockchip,pins", cell,
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ARRAY_SIZE(cell));
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if (ret < 0) {
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debug("%s: bad array %d\n", __func__, ret);
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return -EINVAL;
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}
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count = ret;
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for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) {
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pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]);
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if (pcfg_node < 0)
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return -EINVAL;
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flags = pinctrl_decode_pin_config(blob, pcfg_node);
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if (flags < 0)
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return flags;
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ret = rk3288_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2],
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flags);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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static struct pinctrl_ops rk3288_pinctrl_ops = {
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#ifndef CONFIG_SPL_BUILD
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.set_state = rk3288_pinctrl_set_state,
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#endif
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.set_state_simple = rk3288_pinctrl_set_state_simple,
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.request = rk3288_pinctrl_request,
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.get_periph_id = rk3288_pinctrl_get_periph_id,
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@ -422,15 +616,49 @@ static int rk3288_pinctrl_bind(struct udevice *dev)
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return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
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}
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#ifndef CONFIG_SPL_BUILD
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static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv,
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struct rockchip_pin_bank *banks,
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int count)
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{
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struct rockchip_pin_bank *bank;
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uint reg, muxnum, banknum;
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reg = 0;
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for (banknum = 0; banknum < count; banknum++) {
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bank = &banks[banknum];
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bank->reg = reg;
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debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4);
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for (muxnum = 0; muxnum < 4; muxnum++) {
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struct rockchip_iomux *mux = &bank->iomux[muxnum];
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if (!(mux->type & IOMUX_UNROUTED))
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mux->offset = reg;
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if (mux->type & IOMUX_WIDTH_4BIT)
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reg += 2;
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else
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reg += 1;
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}
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}
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return 0;
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}
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#endif
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static int rk3288_pinctrl_probe(struct udevice *dev)
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{
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struct rk3288_pinctrl_priv *priv = dev_get_priv(dev);
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int ret = 0;
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
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debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu);
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#ifndef CONFIG_SPL_BUILD
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ret = rk3288_pinctrl_parse_tables(priv, rk3288_pin_banks,
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ARRAY_SIZE(rk3288_pin_banks));
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#endif
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return 0;
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return ret;
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}
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static const struct udevice_id rk3288_pinctrl_ids[] = {
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