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ARM: tegra: pinmux: move some type definitions

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On some future SoCs, some per-drive-group features became per-pin
features. Move all type definitions early in the header so they can
be enabled irrespective of the setting of TEGRA_PMX_SOC_HAS_DRVGRPS.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2015-02-24 14:08:26 -07:00 committed by Tom Warren
parent 439f57684e
commit bc13472867
2 changed files with 44 additions and 44 deletions
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58
arch/arm/include/asm/arch-tegra/pinmux.h
View File

@ -63,6 +63,35 @@ enum pmux_pin_rcv_sel {
}; };
#endif #endif
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
/* Defines a pin group cfg's low-power mode select */
enum pmux_lpmd {
PMUX_LPMD_X8 = 0,
PMUX_LPMD_X4,
PMUX_LPMD_X2,
PMUX_LPMD_X,
PMUX_LPMD_NONE = -1,
};
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pmux_schmt {
PMUX_SCHMT_DISABLE = 0,
PMUX_SCHMT_ENABLE = 1,
PMUX_SCHMT_NONE = -1,
};
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pmux_hsm {
PMUX_HSM_DISABLE = 0,
PMUX_HSM_ENABLE = 1,
PMUX_HSM_NONE = -1,
};
#endif
/* /*
* This defines the configuration for a pin, including the function assigned, * This defines the configuration for a pin, including the function assigned,
* pull up/down settings and tristate settings. Having set up one of these * pull up/down settings and tristate settings. Having set up one of these
@ -142,35 +171,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
#define PMUX_DRVDN_MAX 127 #define PMUX_DRVDN_MAX 127
#define PMUX_DRVDN_NONE -1 #define PMUX_DRVDN_NONE -1
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
/* Defines a pin group cfg's low-power mode select */
enum pmux_lpmd {
PMUX_LPMD_X8 = 0,
PMUX_LPMD_X4,
PMUX_LPMD_X2,
PMUX_LPMD_X,
PMUX_LPMD_NONE = -1,
};
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pmux_schmt {
PMUX_SCHMT_DISABLE = 0,
PMUX_SCHMT_ENABLE = 1,
PMUX_SCHMT_NONE = -1,
};
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pmux_hsm {
PMUX_HSM_DISABLE = 0,
PMUX_HSM_ENABLE = 1,
PMUX_HSM_NONE = -1,
};
#endif
/* /*
* This defines the configuration for a pin group's pad control config * This defines the configuration for a pin group's pad control config
*/ */

30
arch/arm/mach-tegra/pinmux-common.c
View File

@ -56,6 +56,21 @@
((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH)) ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
#endif #endif
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
#define pmux_lpmd_isvalid(lpm) \
(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
#define pmux_schmt_isvalid(schmt) \
(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
#define pmux_hsm_isvalid(hsm) \
(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#endif
#define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset)) #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
#if defined(CONFIG_TEGRA20) #if defined(CONFIG_TEGRA20)
@ -352,21 +367,6 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
#define pmux_drv_isvalid(drv) \ #define pmux_drv_isvalid(drv) \
(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX)) (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
#define pmux_lpmd_isvalid(lpm) \
(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
#define pmux_schmt_isvalid(schmt) \
(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM
#define pmux_hsm_isvalid(hsm) \
(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#endif
#ifdef TEGRA_PMX_GRPS_HAVE_HSM #ifdef TEGRA_PMX_GRPS_HAVE_HSM
#define HSM_SHIFT 2 #define HSM_SHIFT 2
#endif #endif