delta board: DA9030 initialization and i2c support. Some minor changes to
make the pxa i2c driver work with the monahans cpu.
This commit is contained in:
Markus Klotzbuecher
Markus Klotzbcher
parent
552fc624f2
commit
ba70d6a417
@ -26,9 +26,13 @@
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*/
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#include <common.h>
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#include <i2c.h>
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#include <da9030.h>
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#include <asm/arch/pxa-regs.h>
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/* ------------------------------------------------------------------------- */
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static void init_DA9030(void);
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/*
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* Miscelaneous platform dependent initialisations
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@ -54,6 +58,7 @@ int board_late_init(void)
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{
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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init_DA9030();
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return 0;
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}
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@ -73,3 +78,65 @@ int dram_init (void)
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return 0;
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}
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/* initialize the DA9030 Power Controller */
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static void init_DA9030()
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{
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uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
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/* setup I2C GPIO's */
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GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */
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GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */
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/* rising Edge on EXTON */
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GPIO17 = 0x8800;
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udelay(5);
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GPIO17 = 0xc800;
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udelay(100000); /* wait for DA9030 */
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/* reset the watchdog and go active (0xec) */
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val = (SYS_CONTROL_A_HWRES_ENABLE |
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(0x6<<4) |
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SYS_CONTROL_A_WDOG_ACTION |
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SYS_CONTROL_A_WATCHDOG);
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i2c_reg_write(addr, SYS_CONTROL_A, val);
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i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */
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i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */
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i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */
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i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */
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i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */
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i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */
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i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */
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i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */
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i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */
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i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */
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i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */
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i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */
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i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */
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i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */
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i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */
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i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */
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i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */
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val = i2c_reg_read(addr, STATUS);
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if(val & STATUS_CHDET)
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printf("Charger detected, turning on LED.\n");
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else {
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printf("No charger detetected.\n");
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/* undervoltage? print error and power down */
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}
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}
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#if 0
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/* reset the DA9030 watchdog */
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void hw_watchdog_reset(void)
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{
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uchar addr = (uchar) DA9030_I2C_ADDR, val = 0;
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val = i2c_reg_read(addr, SYS_CONTROL_A);
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val |= SYS_CONTROL_A_WATCHDOG;
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i2c_reg_write(addr, SYS_CONTROL_A, val);
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}
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#endif
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@ -47,7 +47,13 @@
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/*#define DEBUG_I2C 1 /###* activate local debugging output */
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#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */
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#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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#if (CFG_I2C_SPEED == 400000)
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#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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#else
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#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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#endif
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#define I2C_ISR_INIT 0x7FF
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#ifdef DEBUG_I2C
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@ -91,7 +97,11 @@ static void i2c_reset( void )
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ICR |= ICR_UR; /* reset the unit */
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udelay(100);
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ICR &= ~ICR_IUE; /* disable unit */
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#ifdef CONFIG_CPU_MONAHANS
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CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */
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#else /* CONFIG_CPU_MONAHANS */
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CKEN |= CKEN14_I2C; /* set the global I2C clock on */
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#endif
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ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */
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ICR = I2C_ICR_INIT; /* set control register values */
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ISR = I2C_ISR_INIT; /* set clear interrupt bits */
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@ -104,9 +114,8 @@ static void i2c_reset( void )
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* i2c_isr_set_cleared: - wait until certain bits of the I2C status register
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* are set and cleared
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*
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* @return: 0 in case of success, 1 means timeout (no match within 10 ms).
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* @return: 1 in case of success, 0 means timeout (no match within 10 ms).
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*/
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static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask )
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{
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int timeout = 10000;
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@ -360,9 +369,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
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msg.data = 0x00;
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if ((ret=i2c_transfer(&msg))) return -1;
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*(buffer++) = msg.data;
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*buffer = msg.data;
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PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer));
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buffer++;
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}
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@ -475,11 +475,11 @@ typedef void (*ExcpHndlr) (void) ;
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#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
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#define ICR_TB 0x8 /* transfer byte bit */
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#define ICR_MA 0x10 /* master abort */
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#define ICR_SCLE 0x20 /* master clock enable */
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#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
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#define ICR_IUE 0x40 /* unit enable */
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#define ICR_GCD 0x80 /* general call disable */
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#define ICR_ITEIE 0x100 /* enable tx interrupts */
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#define ICR_IRFIE 0x200 /* enable rx interrupts */
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#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
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#define ICR_BEIE 0x400 /* enable bus error ints */
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#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
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#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
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@ -923,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ;
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#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
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/* Missing: 32 Interrupt priority registers
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* These are the same as beneath for PXA27x: maybe can be merged if
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* GPIO Stuff is same too.
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* GPIO Stuff is same too.
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*/
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#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
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#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
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@ -49,7 +49,6 @@
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/*
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* Hardware drivers
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*/
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#undef TURN_ON_ETHERNET
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#ifdef TURN_ON_ETHERNET
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# define CONFIG_DRIVER_SMC91111 1
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@ -59,6 +58,12 @@
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# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */
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#endif
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#define CONFIG_HARD_I2C 1 /* required for DA9030 access */
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#define CFG_I2C_SPEED 400000 /* I2C speed */
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#define CFG_I2C_SLAVE 1 /* I2C controllers address */
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#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */
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/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */
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/*
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* select serial console configuration
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*/
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@ -73,8 +78,13 @@
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#ifdef TURN_ON_ETHERNET
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# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
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#else
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# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \
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& ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS))
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# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
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| CFG_CMD_ENV \
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| CFG_CMD_NAND \
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| CFG_CMD_I2C) \
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& ~(CFG_CMD_NET \
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| CFG_CMD_FLASH \
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| CFG_CMD_IMLS))
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#endif
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@ -121,7 +131,7 @@
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#define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */
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#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
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#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */
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#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
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/* valid baudrates */
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106
include/da9030.h
Normal file
106
include/da9030.h
Normal file
@ -0,0 +1,106 @@
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/*
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* (C) Copyright 2006 DENX Software Engineering
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* DA9030 register definitions */
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#define CID 0x00
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#define EVENT_A 0x01
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#define EVENT_B 0x02
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#define EVENT_C 0x03
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#define STATUS 0x04
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#define IRQ_MASK_A 0x05
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#define IRQ_MASK_B 0x06
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#define IRQ_MASK_C 0x07
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#define SYS_CONTROL_A 0x08
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#define SYS_CONTROL_B 0x09
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#define FAULT_LOG 0x0A
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#define LDO_10_11 0x10
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#define LDO_15 0x11
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#define LDO_14_16 0x12
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#define LDO_18_19 0x13
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#define LDO_17_SIMCP0 0x14
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#define BUCK2_DVC1 0x15
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#define BUCK2_DVC2 0x16
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#define REG_CONTROL_1_17 0x17
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#define REG_CONTROL_2_18 0x18
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#define USBPUMP 0x19
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#define SLEEP_CONTROL 0x1A
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#define STARTUP_CONTROL 0x1B
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#define LED1_CONTROL 0x20
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#define LED2_CONTROL 0x21
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#define LED3_CONTROL 0x22
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#define LED4_CONTROL 0x23
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#define LEDPC_CONTROL 0x24
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#define WLED_CONTROL 0x25
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#define MISC_CONTROLA 0x26
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#define MISC_CONTROLB 0x27
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#define CHARGE_CONTROL 0x28
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#define CCTR_CONTROL 0x29
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#define TCTR_CONTROL 0x2A
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#define CHARGE_PULSE 0x2B
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/* ... some missing ...*/
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#define LDO1 0x90
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#define LDO2_3 0x91
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#define LDO4_5 0x92
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#define LDO6_SIMCP 0x93
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#define LDO7_8 0x94
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#define LDO9_12 0x95
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#define BUCK 0x96
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#define REG_CONTROL_1_97 0x97
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#define REG_CONTROL_2_98 0x98
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#define REG_SLEEP_CONTROL1 0x99
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#define REG_SLEEP_CONTROL2 0x9A
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#define REG_SLEEP_CONTROL3 0x9B
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#define ADC_MAN_CONTROL 0xA0
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#define ADC_AUTO_CONTROL 0xA1
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#define VBATMON 0xA2
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#define VBATMONTXMON 0xA3
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#define TBATHIGHP 0xA4
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#define TBATHIGHN 0xA5
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#define TBATLOW 0xA6
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#define MAN_RES 0xB0
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#define VBAT_RES 0xB1
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#define VBATMIN_RES 0xB2
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#define VBATMINTXON_RES 0xB3
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#define ICHMAX_RES 0xB4
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#define ICHMIN_RES 0xB5
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#define ICHAVERAGE_RES 0xB6
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#define VCHMAX_RES 0xB7
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#define VCHMIN_RES 0xB8
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#define TBAT_RES 0xB9
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#define ADC_IN4_RES 0xBA
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#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */
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#define STATUS_PWREN1 (1<<1) /* PWREN1 value */
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#define STATUS_EXTON (1<<2) /* EXTON value */
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#define STATUS_CHDET (1<<3) /* Charger detection status */
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#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */
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#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */
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#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */
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#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */
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#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1
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#define SYS_CONTROL_A_SHUT_DOWN (1<<1)
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#define SYS_CONTROL_A_HWRES_ENABLE (1<<2)
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#define SYS_CONTROL_A_WDOG_ACTION (1<<3)
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#define SYS_CONTROL_A_WATCHDOG (1<<7)
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