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x86: fsp: Save stack address to CMOS for next S3 boot

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At the end of pre-relocation phase, save the new stack address
to CMOS and use it as the stack on next S3 boot for fsp_init()
continuation function.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Bin Meng 2017-04-21 07:24:39 -07:00
parent 9f1fad1e36
commit ba65808e7d
4 changed files with 89 additions and 1 deletions
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8
arch/x86/cpu/cpu.c
View File

@ -278,6 +278,14 @@ int reserve_arch(void)
high_table_reserve();
#endif
#if defined(CONFIG_HAVE_ACPI_RESUME) && defined(CONFIG_HAVE_FSP)
/*
* Save stack address to CMOS so that at next S3 boot,
* we can use it as the stack address for fsp_contiue()
*/
fsp_save_s3_stack();
#endif
return 0;
}
#endif

31
arch/x86/include/asm/cmos_layout.h Normal file
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@ -0,0 +1,31 @@
/*
* Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CMOS_LAYOUT_H
#define __CMOS_LAYOUT_H
/*
* The RTC internal registers and RAM is organized as two banks of 128 bytes
* each, called the standard and extended banks. The first 14 bytes of the
* standard bank contain the RTC time and date information along with four
* registers, A - D, that are used for configuration of the RTC. The extended
* bank contains a full 128 bytes of battery backed SRAM.
*
* For simplicity in U-Boot we only support CMOS in the standard bank, and
* its base address starts from offset 0x10, which leaves us 112 bytes space.
*/
#define CMOS_BASE 0x10
/*
* The file records all offsets off CMOS_BASE that is currently used by
* U-Boot for various reasons. It is put in such a unified place in order
* to be consistent across platforms.
*/
/* stack address for S3 boot in a FSP configuration, 4 bytes */
#define CMOS_FSP_STACK_ADDR CMOS_BASE
#endif /* __CMOS_LAYOUT_H */

13
arch/x86/include/asm/u-boot-x86.h
View File

@ -54,6 +54,19 @@ u32 isa_map_rom(u32 bus_addr, int size);
/* arch/x86/lib/... */
int video_bios_init(void);
/* arch/x86/lib/fsp/... */
/**
* fsp_save_s3_stack() - save stack address to CMOS for next S3 boot
*
* At the end of pre-relocation phase, save the new stack address
* to CMOS and use it as the stack on next S3 boot for fsp_init()
* continuation function.
*
* @return: 0 if OK, -ve on error
*/
int fsp_save_s3_stack(void);
void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
void board_init_f_r(void) __attribute__ ((noreturn));

38
arch/x86/lib/fsp/fsp_common.c
View File

@ -5,8 +5,12 @@
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <rtc.h>
#include <asm/acpi_s3.h>
#include <asm/cmos_layout.h>
#include <asm/early_cmos.h>
#include <asm/io.h>
#include <asm/mrccache.h>
#include <asm/post.h>
@ -76,9 +80,36 @@ static __maybe_unused void *fsp_prepare_mrc_cache(void)
return cache->data;
}
#ifdef CONFIG_HAVE_ACPI_RESUME
int fsp_save_s3_stack(void)
{
struct udevice *dev;
int ret;
if (gd->arch.prev_sleep_state == ACPI_S3)
return 0;
ret = uclass_get_device(UCLASS_RTC, 0, &dev);
if (ret) {
debug("Cannot find RTC: err=%d\n", ret);
return -ENODEV;
}
/* Save the stack address to CMOS */
ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
if (ret) {
debug("Save stack address to CMOS: err=%d\n", ret);
return -EIO;
}
return 0;
}
#endif
int arch_fsp_init(void)
{
void *nvs;
int stack = CONFIG_FSP_TEMP_RAM_ADDR;
int boot_mode = BOOT_FULL_CONFIG;
#ifdef CONFIG_HAVE_ACPI_RESUME
int prev_sleep_state = chipset_prev_sleep_state();
@ -107,6 +138,11 @@ int arch_fsp_init(void)
panic("Reboot System");
}
/*
* DM is not avaiable yet at this point, hence call
* CMOS access library which does not depend on DM.
*/
stack = cmos_read32(CMOS_FSP_STACK_ADDR);
boot_mode = BOOT_ON_S3_RESUME;
}
#endif
@ -115,7 +151,7 @@ int arch_fsp_init(void)
* Note the execution does not return to this function,
* instead it jumps to fsp_continue().
*/
fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, boot_mode, nvs);
fsp_init(stack, boot_mode, nvs);
} else {
/*
* The second time we enter here, adjust the size of malloc()