mpc8xx: remove v37 board support
This board is old enough and has no maintainer. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
03f9d7d174
commit
b8c1438a7a
@ -1,8 +0,0 @@
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = v37.o flash.o
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@ -1,543 +0,0 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
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* U-Boot port on RPXlite board
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*
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* Some of flash control words are modified. (from 2x16bit device
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* to 4x8bit device)
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* RPXLite board I tested has only 4 AM29LV800BB devices. Other devices
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* are not tested.
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*
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* (?) Does an RPXLite board which
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* does not use AM29LV800 flash memory exist ?
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* I don't know...
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*/
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#include <common.h>
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#include <mpc8xx.h>
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info);
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static int write_word (flash_info_t *info, ulong dest, ulong data);
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static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips);
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static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id);
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static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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unsigned long size_b0, size_b1;
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short manu, dev_id;
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int i;
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/* Init: no FLASHes known */
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for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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}
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/* Do sizing to get full correct info */
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flash_get_id_word((void*)CONFIG_SYS_FLASH_BASE0,&manu,&dev_id);
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size_b0 = flash_get_size(manu, dev_id, &flash_info[0]);
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flash_get_offsets (CONFIG_SYS_FLASH_BASE0, &flash_info[0],0);
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memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0);
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#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0
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/* monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_MONITOR_BASE,
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CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
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&flash_info[0]);
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#endif
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flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id);
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size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]);
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flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1);
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memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1);
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flash_info[0].size = size_b0;
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flash_info[1].size = size_b1;
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return (size_b0+size_b1);
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}
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/*-----------------------------------------------------------------------
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*/
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static void flash_get_offsets (ulong base, flash_info_t *info, int two_chips)
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{
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int i, addr_shift;
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vu_short *addr = (vu_short*)base;
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addr[0x555] = 0x00AA ;
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addr[0xAAA] = 0x0055 ;
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addr[0x555] = 0x0090 ;
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addr_shift = (two_chips ? 2 : 1 );
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/* set up sector start address table */
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if (info->flash_id & FLASH_BTYPE) {
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/* set sector offsets for bottom boot block type */
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info->start[0] = base + (0x00000000<<addr_shift);
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info->start[1] = base + (0x00002000<<addr_shift);
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info->start[2] = base + (0x00003000<<addr_shift);
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info->start[3] = base + (0x00004000<<addr_shift);
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for (i = 4; i < info->sector_count; i++) {
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info->start[i] = base + ((i-3) * (0x00008000<<addr_shift)) ;
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}
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} else {
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/* set sector offsets for top boot block type */
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i = info->sector_count - 1;
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info->start[i--] = base + info->size - (0x00002000<<addr_shift);
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info->start[i--] = base + info->size - (0x00003000<<addr_shift);
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info->start[i--] = base + info->size - (0x00004000<<addr_shift);
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for (; i >= 0; i--) {
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info->start[i] = base + i * (0x00008000<<addr_shift);
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}
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}
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/* check for protected sectors */
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for (i = 0; i < info->sector_count; i++) {
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/* read sector protection at sector address, (A7 .. A0) = 0x02 */
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/* D0 = 1 if protected */
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addr = (vu_short *)(info->start[i]);
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info->protect[i] = addr[1<<addr_shift] & 1 ;
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}
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addr = (vu_short *)info->start[0];
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*addr = 0xF0F0; /* reset bank */
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}
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/*-----------------------------------------------------------------------
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*/
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void flash_print_info (flash_info_t *info)
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{
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int i;
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("missing or unknown FLASH type\n");
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return;
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}
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switch (info->flash_id & FLASH_VENDMASK) {
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case FLASH_MAN_AMD: printf ("AMD "); break;
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case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
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case FLASH_MAN_TOSH: printf ("TOSHIBA "); break;
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default: printf ("Unknown Vendor "); break;
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}
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
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break;
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case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
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break;
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case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
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break;
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case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
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break;
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case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
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break;
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default: printf ("Unknown Chip Type\n");
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break;
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}
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printf (" Size: %ld MB in %d Sectors\n",
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info->size >> 20, info->sector_count);
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printf (" Sector Start Addresses:");
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for (i=0; i<info->sector_count; ++i) {
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if ((i % 5) == 0)
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printf ("\n ");
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printf (" %08lX%s",
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info->start[i],
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info->protect[i] ? " (RO)" : " "
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);
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}
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printf ("\n");
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}
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/*-----------------------------------------------------------------------
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*/
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/*-----------------------------------------------------------------------
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*/
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/*
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* The following code cannot be run from FLASH!
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*/
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static void flash_get_id_word( void *ptr, short *ptr_manuf, short *ptr_dev_id)
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{
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vu_short *addr = (vu_short*)ptr;
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addr[0x555] = 0x00AA ;
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addr[0xAAA] = 0x0055 ;
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addr[0x555] = 0x0090 ;
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*ptr_manuf = addr[0];
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*ptr_dev_id = addr[1];
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addr[0] = 0xf0f0; /* return to normal */
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}
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static void flash_get_id_long( void *ptr, short *ptr_manuf, short *ptr_dev_id)
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{
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vu_short *addr = (vu_short*)ptr;
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vu_short *addr1, *addr2, *addr3;
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addr1 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
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addr2 = (vu_short*) ( ((int)ptr) + (0x2AAA<<2) );
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addr3 = (vu_short*) ( ((int)ptr) + (0x5555<<2) );
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*addr1 = 0xAAAA;
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*addr2 = 0x5555;
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*addr3 = 0x9090;
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*ptr_manuf = addr[0];
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*ptr_dev_id = addr[2];
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addr[0] = 0xf0f0; /* return to normal */
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}
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static ulong flash_get_size ( short manu, short dev_id, flash_info_t *info)
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{
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switch (manu) {
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case ((short)AMD_MANUFACT):
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info->flash_id = FLASH_MAN_AMD;
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break;
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case ((short)FUJ_MANUFACT):
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info->flash_id = FLASH_MAN_FUJ;
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break;
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case ((short)TOSH_MANUFACT):
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info->flash_id = FLASH_MAN_TOSH;
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break;
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default:
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info->flash_id = FLASH_UNKNOWN;
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info->sector_count = 0;
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info->size = 0;
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return (0); /* no or unknown flash */
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}
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switch (dev_id) {
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case ((short)TOSH_ID_FVT160):
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info->flash_id += FLASH_AM160T;
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info->sector_count = 35;
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info->size = 0x00200000;
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break; /* => 1 MB */
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case ((short)TOSH_ID_FVB160):
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info->flash_id += FLASH_AM160B;
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info->sector_count = 35;
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info->size = 0x00200000;
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break; /* => 1 MB */
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case ((short)AMD_ID_LV400T):
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info->flash_id += FLASH_AM400T;
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info->sector_count = 11;
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info->size = 0x00100000;
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break; /* => 1 MB */
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case ((short)AMD_ID_LV400B):
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info->flash_id += FLASH_AM400B;
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info->sector_count = 11;
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info->size = 0x00100000;
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break; /* => 1 MB */
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case ((short)AMD_ID_LV800T):
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info->flash_id += FLASH_AM800T;
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info->sector_count = 19;
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info->size = 0x00200000;
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break; /* => 2 MB */
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case ((short)AMD_ID_LV800B):
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info->flash_id += FLASH_AM800B;
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info->sector_count = 19;
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info->size = 0x00400000; /*%%% Size doubled by yooth */
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break; /* => 4 MB */
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case ((short)AMD_ID_LV160T):
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info->flash_id += FLASH_AM160T;
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info->sector_count = 35;
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info->size = 0x00200000;
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break; /* => 4 MB */
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case ((short)AMD_ID_LV160B):
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info->flash_id += FLASH_AM160B;
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info->sector_count = 35;
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info->size = 0x00200000;
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break; /* => 4 MB */
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default:
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info->flash_id = FLASH_UNKNOWN;
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return (0); /* => no or unknown flash */
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}
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return(info->size);
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}
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/*-----------------------------------------------------------------------
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*/
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int flash_erase (flash_info_t *info, int s_first, int s_last)
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{
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vu_short *addr = (vu_short*)(info->start[0]);
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int flag, prot, sect, l_sect;
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ulong start, now, last;
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if ((s_first < 0) || (s_first > s_last)) {
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if (info->flash_id == FLASH_UNKNOWN) {
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printf ("- missing\n");
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} else {
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printf ("- no sectors to erase\n");
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}
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return 1;
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}
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if ((info->flash_id == FLASH_UNKNOWN) ||
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(info->flash_id > FLASH_AMD_COMP)) {
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printf ("Can't erase unknown flash type %08lx - aborted\n",
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info->flash_id);
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return 1;
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}
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prot = 0;
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for (sect=s_first; sect<=s_last; ++sect) {
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if (info->protect[sect]) {
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prot++;
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}
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}
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if (prot) {
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printf ("- Warning: %d protected sectors will not be erased!\n",
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prot);
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} else {
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printf ("\n");
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}
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l_sect = -1;
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/* Disable interrupts which might cause a timeout here */
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flag = disable_interrupts();
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addr[0x555] = (vu_short)0xAAAAAAAA;
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addr[0xAAA] = (vu_short)0x55555555;
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addr[0x555] = (vu_short)0x80808080;
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addr[0x555] = (vu_short)0xAAAAAAAA;
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addr[0xAAA] = (vu_short)0x55555555;
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/* Start erase on unprotected sectors */
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for (sect = s_first; sect<=s_last; sect++) {
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if (info->protect[sect] == 0) { /* not protected */
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addr = (vu_short *)(info->start[sect]) ;
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addr[0] = (vu_short)0x30303030 ;
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l_sect = sect;
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}
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}
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/* re-enable interrupts if necessary */
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if (flag)
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enable_interrupts();
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/* wait at least 80us - let's wait 1 ms */
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udelay (1000);
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/*
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* We wait for the last triggered sector
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*/
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if (l_sect < 0)
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goto DONE;
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start = get_timer (0);
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last = start;
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addr = (vu_short *)(info->start[l_sect]);
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while ((addr[0] & 0x8080) != 0x8080) {
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if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
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printf ("Timeout\n");
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return 1;
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}
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/* show that we're waiting */
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if ((now - last) > 1000) { /* every second */
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putc ('.');
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last = now;
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}
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}
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DONE:
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/* reset to read mode */
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addr = (vu_short *)info->start[0];
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addr[0] = (vu_short)0xF0F0F0F0; /* reset bank */
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printf (" done\n");
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return 0;
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}
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/*-----------------------------------------------------------------------
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* Copy memory to flash, returns:
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* 0 - OK
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* 1 - write timeout
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* 2 - Flash not erased
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*/
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
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{
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ulong cp, wp, data;
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int i, l, rc;
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wp = (addr & ~3); /* get lower word aligned address */
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/*
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* handle unaligned start bytes
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*/
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if ((l = addr - wp) != 0) {
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data = 0;
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for (i=0, cp=wp; i<l; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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for (; i<4 && cnt>0; ++i) {
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data = (data << 8) | *src++;
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--cnt;
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++cp;
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}
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for (; cnt==0 && i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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}
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/*
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* handle word aligned part
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*/
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while (cnt >= 4) {
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data = 0;
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for (i=0; i<4; ++i) {
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data = (data << 8) | *src++;
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}
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if ((rc = write_word(info, wp, data)) != 0) {
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return (rc);
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}
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wp += 4;
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cnt -= 4;
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}
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if (cnt == 0) {
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return (0);
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}
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/*
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* handle unaligned tail bytes
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*/
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data = 0;
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for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
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data = (data << 8) | *src++;
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--cnt;
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}
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for (; i<4; ++i, ++cp) {
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data = (data << 8) | (*(uchar *)cp);
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}
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return (write_word(info, wp, data));
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}
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/*-----------------------------------------------------------------------
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* Write a word to Flash, returns:
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* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
vu_short *addr = (vu_short *)(info->start[0]);
|
||||
vu_short sdata;
|
||||
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*((vu_long *)dest) & data) != data) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* First write upper 16 bits */
|
||||
sdata = (short)(data>>16);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x555] = 0xAAAA;
|
||||
addr[0xAAA] = 0x5555;
|
||||
addr[0x555] = 0xA0A0;
|
||||
|
||||
*((vu_short *)dest) = sdata;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Now write lower 16 bits */
|
||||
sdata = (short)(data&0xffff);
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[0x555] = 0xAAAA;
|
||||
addr[0xAAA] = 0x5555;
|
||||
addr[0x555] = 0xA0A0;
|
||||
|
||||
*((vu_short *)dest + 1) = sdata;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
@ -1,82 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2003-2010
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.text :
|
||||
{
|
||||
arch/powerpc/cpu/mpc8xx/start.o (.text*)
|
||||
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
|
||||
|
||||
*(.text*)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
||||
}
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
_GOT2_TABLE_ = .;
|
||||
KEEP(*(.got2))
|
||||
KEEP(*(.got))
|
||||
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
|
||||
_FIXUP_TABLE_ = .;
|
||||
KEEP(*(.fixup))
|
||||
}
|
||||
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
.u_boot_list : {
|
||||
KEEP(*(SORT(.u_boot_list*)));
|
||||
}
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
}
|
||||
__bss_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
202
board/v37/v37.c
202
board/v37/v37.c
@ -1,202 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
|
||||
* U-Boot port on RPXlite board
|
||||
*
|
||||
* DRAM related UPMA register values are modified.
|
||||
* See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "mpc8xx.h"
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
static long int dram_size (void);
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#define MBYTE (1024*1024)
|
||||
#define DRAM_DELAY 0x00000379 /* DRAM delay count */
|
||||
#define _NOT_USED_ 0xFFFFCC25
|
||||
|
||||
const uint sdram_table[] =
|
||||
{
|
||||
/* single read. (offset 0 in upm RAM) */
|
||||
0x1F07D004, 0xEEAEE004, 0x11ADD004, 0xEFBBA000,
|
||||
0x1FF75447, 0x1FF77C34, 0xEFEABC34, 0x1FB57C35,
|
||||
|
||||
/* burst read. (Offset 8 in upm RAM) */
|
||||
0x1F07D004, 0xEEAEE004, 0x00ADC004, 0x00AFC000,
|
||||
0x00AFC000, 0x01AFC000, 0x0FBB8000, 0x1FF75447,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* single write. (Offset 0x18 in upm RAM) */
|
||||
0x1F27D004, 0xEEAEA000, 0x01B90004, 0x1FF75447,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* burst write. (Offset 0x20 in upm RAM) */
|
||||
0x1F07D004, 0xEEAEA000, 0x00AD4000, 0x00AFC000,
|
||||
0x00AFC000, 0x01BB8004, 0x1FF75447, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Refresh cycle, offset 0x30 */
|
||||
0x1FF5DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
|
||||
0xFFFFFC84, 0xFFFFFC07, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
|
||||
/* Exception, 0ffset 0x3C */
|
||||
0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
};
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*
|
||||
* Return 1 for now.
|
||||
*
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
printf("Marel V37\n") ;
|
||||
return (0) ;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
phys_size_t initdram (int board_type)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||
unsigned long temp;
|
||||
volatile int delay_cnt;
|
||||
long int ramsize;
|
||||
|
||||
ramsize = dram_size();
|
||||
|
||||
/* Refresh clock prescalar */
|
||||
memctl->memc_mptpr = 0x400 ;
|
||||
|
||||
if( ramsize == 32*MBYTE )
|
||||
temp = 0xd0904110;
|
||||
else /* 16MB */
|
||||
temp = 0xd0802110;
|
||||
|
||||
memctl->memc_mbmr = temp;
|
||||
|
||||
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
||||
|
||||
/* Map controller banks 2 to the SDRAM bank */
|
||||
memctl->memc_or2 = 0xA00 | (0 - ramsize);
|
||||
memctl->memc_br2 = 0xC1;
|
||||
|
||||
memctl->memc_mbmr = temp | 0x08;
|
||||
memctl->memc_mcr = 0x80804130;
|
||||
|
||||
delay_cnt = 0;
|
||||
while( delay_cnt++ < DRAM_DELAY )
|
||||
;
|
||||
|
||||
/* Run MRS command in location 5-8 of UPMB */
|
||||
|
||||
memctl->memc_mbmr = temp | 0x04;
|
||||
memctl->memc_mar = 0x88;
|
||||
|
||||
memctl->memc_mcr = 0x80804105;
|
||||
|
||||
delay_cnt = 0;
|
||||
while( delay_cnt++ < DRAM_DELAY )
|
||||
;
|
||||
|
||||
#ifdef CONFIG_CAN_DRIVER
|
||||
/* Initialize OR3 / BR3 */
|
||||
memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
|
||||
memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
|
||||
|
||||
/* Initialize MBMR */
|
||||
memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
|
||||
|
||||
/* Initialize UPMB for CAN: single read */
|
||||
memctl->memc_mdr = 0xFFFFC004;
|
||||
memctl->memc_mcr = 0x0100 | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0x0FFFD004;
|
||||
memctl->memc_mcr = 0x0101 | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0x0FFFC000;
|
||||
memctl->memc_mcr = 0x0102 | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0x3FFFC004;
|
||||
memctl->memc_mcr = 0x0103 | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0xFFFFDC05;
|
||||
memctl->memc_mcr = 0x0104 | UPMA;
|
||||
|
||||
/* Initialize UPMB for CAN: single write */
|
||||
memctl->memc_mdr = 0xFFFCC004;
|
||||
memctl->memc_mcr = 0x0118 | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0xCFFCD004;
|
||||
memctl->memc_mcr = 0x0119 | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0x0FFCC000;
|
||||
memctl->memc_mcr = 0x011A | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0x7FFCC004;
|
||||
memctl->memc_mcr = 0x011B | UPMA;
|
||||
|
||||
memctl->memc_mdr = 0xFFFDCC05;
|
||||
memctl->memc_mcr = 0x011C | UPMA;
|
||||
#endif /* CONFIG_CAN_DRIVER */
|
||||
|
||||
return (dram_size());
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Find size of RAM from configuration pins.
|
||||
* The input pins that contain the memory size are also the debug port
|
||||
* pins. Normally they are configured as debug port pins. To be able
|
||||
* to read the memory configuration, we must deactivate the debug port
|
||||
* and enable the pcmcia input pins. Then return the register to
|
||||
* previous state.
|
||||
*/
|
||||
|
||||
static long int dram_size ()
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||
volatile sysconf8xx_t *siu = &immap->im_siu_conf;
|
||||
volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
|
||||
long int i, memory=1;
|
||||
unsigned long siu_mcr;
|
||||
|
||||
siu_mcr = siu->sc_siumcr;
|
||||
siu->sc_siumcr = siu_mcr & 0xFF9FFFFF;
|
||||
for(i=0; i<10; i++) i = i;
|
||||
|
||||
memory = (pcm->pcmc_pipr>>12) & 0x3;
|
||||
|
||||
siu->sc_siumcr = siu_mcr;
|
||||
|
||||
switch( memory )
|
||||
{
|
||||
case 1:
|
||||
return( 32*MBYTE );
|
||||
case 2:
|
||||
return( 64*MBYTE );
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return( 16*MBYTE );
|
||||
}
|
||||
@ -979,7 +979,6 @@ Active powerpc mpc8xx - - -
|
||||
Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
|
||||
Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
|
||||
Active powerpc mpc8xx - - - spc1920 - -
|
||||
Active powerpc mpc8xx - - - v37 - -
|
||||
Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
|
||||
Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
|
||||
Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
|
||||
|
||||
@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
|
||||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
v37 powerpc mpc8xx - -
|
||||
fads powerpc mpc8xx - -
|
||||
netphone powerpc mpc8xx - -
|
||||
netta2 powerpc mpc8xx - -
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
#define CONFIG_LCD_INFO /* Display Logo, (C) and system info */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_V37) || defined(CONFIG_EDT32F10)
|
||||
#if defined(CONFIG_EDT32F10)
|
||||
#undef CONFIG_LCD_LOGO
|
||||
#undef CONFIG_LCD_INFO
|
||||
#endif
|
||||
@ -413,12 +413,6 @@ void lcd_enable (void)
|
||||
immr->im_siu_conf.sc_sdcr |= (1 << (31 - 25)); /* LAM = 1 */
|
||||
lcdp->lcd_lccr |= LCCR_PON;
|
||||
|
||||
#ifdef CONFIG_V37
|
||||
/* Turn on display backlight */
|
||||
immr->im_cpm.cp_pbpar |= 0x00008000;
|
||||
immr->im_cpm.cp_pbdir |= 0x00008000;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_LWMON)
|
||||
{ uchar c = pic_read (0x60);
|
||||
#if defined(CONFIG_LCD) && defined(CONFIG_LWMON) && (CONFIG_POST & CONFIG_SYS_POST_SYSMON)
|
||||
|
||||
@ -1023,29 +1023,6 @@ typedef struct scc_enet {
|
||||
# endif /* CONFIG_FEC_ENET */
|
||||
#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
|
||||
|
||||
/*** V37 **********************************************************/
|
||||
|
||||
#ifdef CONFIG_V37
|
||||
/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of
|
||||
* this may be unique to the Marel V37 configuration.
|
||||
* Note TENA is on Port B.
|
||||
*/
|
||||
#define PROFF_ENET PROFF_SCC2
|
||||
#define CPM_CR_ENET CPM_CR_CH_SCC2
|
||||
#define SCC_ENET 1
|
||||
#define PA_ENET_RXD ((ushort)0x0004)
|
||||
#define PA_ENET_TXD ((ushort)0x0008)
|
||||
#define PA_ENET_TCLK ((ushort)0x0400)
|
||||
#define PA_ENET_RCLK ((ushort)0x0200)
|
||||
#define PB_ENET_TENA ((uint)0x00002000)
|
||||
#define PC_ENET_CLSN ((ushort)0x0040)
|
||||
#define PC_ENET_RENA ((ushort)0x0080)
|
||||
|
||||
#define SICR_ENET_MASK ((uint)0x0000ff00)
|
||||
#define SICR_ENET_CLKRT ((uint)0x00002e00)
|
||||
#endif /* CONFIG_V37 */
|
||||
|
||||
|
||||
/*********************************************************************/
|
||||
|
||||
/* SCC Event register as used by Ethernet.
|
||||
|
||||
@ -1,375 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2000, 2001
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
|
||||
#define CONFIG_V37 1 /* ...on a Marel V37 board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x40000000
|
||||
|
||||
#define CONFIG_LCD
|
||||
#define CONFIG_MPC8XX_LCD
|
||||
#define CONFIG_SHARP_LQ084V1DG21
|
||||
#undef CONFIG_LCD_LOGO
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* I2C Configuration
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_I2C 1
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x2
|
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1
|
||||
#undef CONFIG_8xx_CONS_SMC2 /* Console is on SMC2 */
|
||||
#undef CONFIG_8xx_CONS_NONE
|
||||
#define CONFIG_BAUDRATE 9600 /* console baudrate = 115kbps */
|
||||
#if 0
|
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||
#else
|
||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
|
||||
#endif
|
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
|
||||
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"tftpboot; " \
|
||||
"setenv bootargs console=tty0 " \
|
||||
"root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
|
||||
"bootm"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_DATE
|
||||
|
||||
|
||||
/*
|
||||
* JFFS2 partitions
|
||||
*
|
||||
*/
|
||||
/* No command line, one static partition, whole device */
|
||||
#undef CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_JFFS2_DEV "nor1"
|
||||
#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
|
||||
#define CONFIG_JFFS2_PART_OFFSET 0x00000000
|
||||
|
||||
/* mtdparts command line support */
|
||||
/* Note: fake mtd_id used, no linux mtd map file */
|
||||
/*
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define MTDIDS_DEFAULT "nor1=v37-1"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)"
|
||||
*/
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE0 0x40000000
|
||||
#define CONFIG_SYS_FLASH_BASE1 0x60000000
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE1
|
||||
|
||||
#if defined(DEBUG)
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#endif
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1
|
||||
#define CONFIG_ENV_ADDR 0x80000000/* Address of Environment */
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
#define CONFIG_ENV_OFFSET 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||
#else
|
||||
#define CONFIG_SYS_SYPCR 0xFFFFFF88
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
* PCMCIA config., multi-function pin tri-state
|
||||
*/
|
||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_FRC | SIUMCR_GB5E)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/*%%%#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
|
||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_RTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
/*
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
||||
*-----------------------------------------------------------------------
|
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
||||
* interrupt status bit
|
||||
*
|
||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
||||
*/
|
||||
/* up to 50 MHz we use a 1:1 clock */
|
||||
#define CONFIG_SYS_PLPRCR ( (1524 << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TMIST | PLPRCR_TEXPS )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
/* up to 50 MHz we use a 1:1 clock */
|
||||
#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_TBS)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#undef CONFIG_IDE_PCCARD /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0 and OR0 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
|
||||
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH 0xF56
|
||||
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_BR5_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V)
|
||||
|
||||
/*
|
||||
* BR1 and OR1 (Battery backed SRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_BR1_PRELIM 0x80000401
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xFFC00736
|
||||
|
||||
/*
|
||||
* BR2 and OR2 (SDRAM)
|
||||
*/
|
||||
#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB */
|
||||
|
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
|
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
/* Marel V37 mem setting */
|
||||
|
||||
#define CONFIG_SYS_BR3_CAN 0xC0000401
|
||||
#define CONFIG_SYS_OR3_CAN 0xFFFF0724
|
||||
|
||||
/*
|
||||
#define CONFIG_SYS_BR3_PRELIM 0xFA400001
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xFFFF8910
|
||||
#define CONFIG_SYS_BR4_PRELIM 0xFA000401
|
||||
#define CONFIG_SYS_OR4_PRELIM 0xFFFE0970
|
||||
*/
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*/
|
||||
|
||||
/* periodic timer for refresh */
|
||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
|
||||
|
||||
/*
|
||||
* Refresh clock Prescalar
|
||||
*/
|
||||
#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 10 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | \
|
||||
MAMR_GPL_A4DIS | MAMR_RLFA_4X | MAMR_WLFA_3X | MAMR_TLFA_16X)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user