m68k: m5253evbe: Remove this board
The m5253evbe board has been marked as orphan since June of 2014 and should have been dropped a while ago. Do so now. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
d68b6ad138
commit
b740074ac4
@ -144,10 +144,6 @@ config TARGET_M5253DEMO
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bool "Support M5253DEMO"
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bool "Support M5253DEMO"
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select M5253
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select M5253
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config TARGET_M5253EVBE
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bool "Support M5253EVBE"
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select M5253
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config TARGET_M5272C3
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config TARGET_M5272C3
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bool "Support M5272C3"
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bool "Support M5272C3"
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select M5272
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select M5272
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@ -214,7 +210,6 @@ source "board/freescale/m52277evb/Kconfig"
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source "board/freescale/m5235evb/Kconfig"
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source "board/freescale/m5235evb/Kconfig"
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source "board/freescale/m5249evb/Kconfig"
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source "board/freescale/m5249evb/Kconfig"
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source "board/freescale/m5253demo/Kconfig"
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source "board/freescale/m5253demo/Kconfig"
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source "board/freescale/m5253evbe/Kconfig"
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source "board/freescale/m5272c3/Kconfig"
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source "board/freescale/m5272c3/Kconfig"
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source "board/freescale/m5275evb/Kconfig"
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source "board/freescale/m5275evb/Kconfig"
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source "board/freescale/m5282evb/Kconfig"
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source "board/freescale/m5282evb/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_M5253EVBE
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config SYS_CPU
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default "mcf52x2"
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config SYS_BOARD
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default "m5253evbe"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "M5253EVBE"
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endif
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@ -1,6 +0,0 @@
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M5253EVBE BOARD
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#M: Hayden Fraser <Hayden.Fraser@freescale.com>
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S: Orphan (since 2014-06)
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F: board/freescale/m5253evbe/
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F: include/configs/M5253EVBE.h
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F: configs/M5253EVBE_defconfig
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@ -1,6 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y = m5253evbe.o
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@ -1,102 +0,0 @@
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Freescale Amadeus Plus M5253EVBE board
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======================================
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Hayden Fraser(Hayden.Fraser@freescale.com)
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Created 06/05/2007
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===========================================
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1. SWITCH SETTINGS
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==================
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1.1 N/A
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2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL
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===========================================
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2.1. For the initial bringup, we adopted a consistent memory scheme between U-Boot and
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linux kernel, you can customize it based on your system requirements:
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SDR: 0x00000000-0x00ffffff
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SRAM0: 0x20010000-0x20017fff
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SRAM1: 0x20000000-0x2000ffff
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MBAR1: 0x10000000-0x4fffffff
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MBAR2: 0x80000000-0xCfffffff
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Flash: 0xffe00000-0xffffffff
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3. DEFINITIONS AND COMPILATION
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==============================
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3.1 Explanation on NEW definitions in include/configs/M5253EVBE.h
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CONFIG_MCF52x2 Processor family
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CONFIG_MCF5253 MCF5253 specific
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CONFIG_SYS_CLK Define Amadeus Plus CPU Clock
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CONFIG_SYS_MBAR MBAR base address
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CONFIG_SYS_MBAR2 MBAR2 base address
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3.2 Compilation
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export CROSS_COMPILE=/usr/local/freescale-coldfire-4.1-elf/bin/m68k-elf-
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cd u-boot-1-2-x
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make distclean
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make M5253EVBE_config
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make
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4. SCREEN DUMP
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==============
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4.1 U-Boot 1.2.0 (Jun 18 2007 - 18:20:00)
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CPU: Freescale Coldfire MCF5253 at 62 MHz
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Board: Freescale MCF5253 EVBE
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DRAM: 16 MB
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FLASH: 2 MB
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In: serial
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Out: serial
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Err: serial
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=> flinfo
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Bank # 1: CFI conformant FLASH (16 x 16) Size: 2 MB in 35 Sectors
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AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x49
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Erase timeout: 16384 ms, write timeout: 1 ms
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Sector Start Addresses:
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FFE00000 RO FFE04000 RO FFE06000 RO FFE08000 RO FFE10000 RO
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FFE20000 FFE30000 FFE40000 FFE50000 FFE60000
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FFE70000 FFE80000 FFE90000 FFEA0000 FFEB0000
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FFEC0000 FFED0000 FFEE0000 FFEF0000 FFF00000
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FFF10000 FFF20000 FFF30000 FFF40000 FFF50000
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FFF60000 FFF70000 FFF80000 FFF90000 FFFA0000
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FFFB0000 FFFC0000 FFFD0000 FFFE0000 FFFF0000
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=> bdinfo
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boot_params = 0x00F62F90
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memstart = 0x00000000
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memsize = 0x01000000
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flashstart = 0xFFE00000
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flashsize = 0x00200000
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flashoffset = 0x00000000
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baudrate = 19200 bps
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=> printenv
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bootdelay=5
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baudrate=19200
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stdin=serial
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stdout=serial
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stderr=serial
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Environment size: 134/8188 bytes
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=> saveenv
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Saving Environment to Flash...
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Un-Protected 1 sectors
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Erasing Flash...
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. done
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Erased 1 sectors
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Writing to Flash... done
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Protected 1 sectors
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=>
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5. COMPILER
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-----------
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To create U-Boot the CodeSourcery's version of the GNU Toolchain for the ColdFire architecture
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compiler set (freescale-coldfire-4.1-elf) from www.codesourcery.com was used.
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You can download it from:http://www.codesourcery.com/gnu_toolchains/coldfire/download.html
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compiler that you used - for example, codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
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codesourcery_elf requires -MQ in rules.mk, old M68K 2.95.3 just -M
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@ -1,128 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*/
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale MCF5253 EVBE\n");
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return 0;
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};
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int dram_init(void)
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{
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
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u32 RC, dramsize;
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RC = (CONFIG_SYS_CLK / 1000000) >> 1;
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RC = (RC * 15) >> 4;
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/* Initialize DRAM Control Register: DCR */
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mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
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asm("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x00002320);
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asm("nop");
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/* Initialize DMR0 */
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dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
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mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
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asm("nop");
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mbar_writeLong(MCFSIM_DACR0, 0x00002328);
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asm("nop");
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/* Write to this block to initiate precharge */
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*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
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asm("nop");
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/* Set RE bit in DACR */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x8000);
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asm("nop");
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/* Wait for at least 8 auto refresh cycles to occur */
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udelay(500);
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/* Finish the configuration by issuing the MRS */
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mbar_writeLong(MCFSIM_DACR0,
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mbar_readLong(MCFSIM_DACR0) | 0x0040);
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asm("nop");
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*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
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}
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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return 0;
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}
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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#ifdef CONFIG_IDE
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#include <ata.h>
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int ide_preinit(void)
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{
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return (0);
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}
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void ide_set_reset(int idereset)
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{
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atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
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long period;
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/* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
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int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
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{50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
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{30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
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{30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
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{25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
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};
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if (idereset) {
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/* control reset */
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out_8(&ata->cr, 0);
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udelay(100);
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} else {
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mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
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#define CALC_TIMING(t) (t + period - 1) / period
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period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
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/*ata->ton = CALC_TIMING (180); */
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out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
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out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
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out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
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out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
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out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
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out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
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out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
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/* IORDY enable */
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out_8(&ata->cr, 0x40);
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udelay(2000);
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/* IORDY enable */
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setbits_8(&ata->cr, 0x01);
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}
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}
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#endif /* CONFIG_IDE */
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@ -1,16 +0,0 @@
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CONFIG_M68K=y
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CONFIG_SYS_TEXT_BASE=0xFFE00000
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CONFIG_TARGET_M5253EVBE=y
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CONFIG_BOOTDELAY=5
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# CONFIG_DISPLAY_BOARDINFO is not set
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# CONFIG_CMDLINE_EDITING is not set
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# CONFIG_AUTO_COMPLETE is not set
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_IDE=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_MAC_PARTITION=y
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# CONFIG_NET is not set
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CONFIG_MTD_NOR_FLASH=y
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@ -1,163 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* Hayden Fraser (Hayden.Fraser@freescale.com)
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*/
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#ifndef _M5253EVBE_H
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#define _M5253EVBE_H
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#define CONFIG_MCFTMR
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT (0)
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#undef CONFIG_WATCHDOG /* disable watchdog */
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#ifndef CONFIG_MONITOR_IS_IN_RAM
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#define CONFIG_ENV_OFFSET 0x4000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#else
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#define CONFIG_ENV_ADDR 0xffe04000
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#define CONFIG_ENV_SECT_SIZE 0x2000
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#endif
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#define LDS_BOARD_TEXT \
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. = DEFINED(env_offset) ? env_offset : .; \
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env/embedded.o(.text)
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/*
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* BOOTP options
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*/
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#undef CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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/* ATA */
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#define CONFIG_IDE_RESET 1
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#define CONFIG_IDE_PREINIT 1
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#define CONFIG_ATAPI
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#undef CONFIG_LBA48
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_IDE_MAXDEVICE 2
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#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0
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#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
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#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
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#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
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#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
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#define CONFIG_SYS_LOAD_ADDR 0x00100000
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#define CONFIG_SYS_MEMTEST_START 0x400
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#define CONFIG_SYS_MEMTEST_END 0x380000
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#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
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#define CONFIG_SYS_FAST_CLK
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#ifdef CONFIG_SYS_FAST_CLK
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# define CONFIG_SYS_PLLCR 0x1243E054
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# define CONFIG_SYS_CLK 140000000
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#else
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# define CONFIG_SYS_PLLCR 0x135a4140
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# define CONFIG_SYS_CLK 70000000
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#endif
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
|
|
||||||
* You should know what you are doing if you make changes here.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
|
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||||||
#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Start addresses for the final memory configuration
|
|
||||||
* (Set up by the startup code)
|
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
|
|
||||||
|
|
||||||
#ifdef CONFIG_MONITOR_IS_IN_RAM
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE 0x20000
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN 0x40000
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10)
|
|
||||||
#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 8 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization ??
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
|
|
||||||
|
|
||||||
/* FLASH organization */
|
|
||||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_CFI 1
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
|
||||||
#define CONFIG_SYS_FLASH_SIZE 0x200000
|
|
||||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
|
||||||
|
|
||||||
/* Cache Configuration */
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
|
||||||
|
|
||||||
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
|
||||||
CONFIG_SYS_INIT_RAM_SIZE - 8)
|
|
||||||
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
|
||||||
CONFIG_SYS_INIT_RAM_SIZE - 4)
|
|
||||||
#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
|
|
||||||
#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
|
|
||||||
CF_ADDRMASK(2) | \
|
|
||||||
CF_ACR_EN | CF_ACR_SM_ALL)
|
|
||||||
#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
|
|
||||||
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
|
|
||||||
CF_ACR_EN | CF_ACR_SM_ALL)
|
|
||||||
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
|
|
||||||
CF_CACR_DBWE)
|
|
||||||
|
|
||||||
/* Port configuration */
|
|
||||||
#define CONFIG_SYS_FECI2C 0xF0
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CS0_BASE 0xFFE00000
|
|
||||||
#define CONFIG_SYS_CS0_MASK 0x001F0021
|
|
||||||
#define CONFIG_SYS_CS0_CTRL 0x00001D80
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Port configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
|
|
||||||
#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
|
|
||||||
#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
|
|
||||||
#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
|
|
||||||
#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
|
|
||||||
#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
|
|
||||||
#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
|
|
||||||
|
|
||||||
#endif /* _M5253EVB_H */
|
|
||||||
Loading…
Reference in New Issue
Block a user