dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device tree node to specify the ranges, removing the board-specific PCI code and ensuring that the host bridge is configured. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
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@ -7,5 +7,4 @@
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obj-y += cpu.o
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obj-y += early_uart.o
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obj-y += fsp_configs.o
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obj-y += pci.o
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obj-y += valleyview.o
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@ -1,46 +0,0 @@
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/fsp/fsp_support.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_PREF_BUS,
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CONFIG_PCI_PREF_PHYS,
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CONFIG_PCI_PREF_SIZE,
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PCI_REGION_PREFETCH);
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pci_set_region(hose->regions + 3,
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0,
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0,
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gd->ram_size < 0x80000000 ? gd->ram_size : 0x80000000,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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}
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@ -111,6 +111,16 @@
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};
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pci {
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compatible = "intel,pci-baytrail", "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0xd0000000 0xd0000000 0 0x10000000
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x10000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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};
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -22,3 +22,4 @@ CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_SYS_VSNPRINTF=y
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CONFIG_DM_PCI=y
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@ -32,6 +32,7 @@
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0xe000
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#define CONFIG_PCI_CONFIG_HOST_BRIDGE
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#define CONFIG_SYS_EARLY_PCI_INIT
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#define CONFIG_PCI_PNP
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#define CONFIG_RTL8169
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