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Merge branch 'master' of git://git.denx.de/u-boot-sunxi

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This commit is contained in:
Tom Rini 2018-08-20 13:41:56 -04:00
commit b71d9e8b38
20 changed files with 2878 additions and 132 deletions
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169
arch/arm/dts/axp81x.dtsi Normal file
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@ -0,0 +1,169 @@
/*
* Copyright 2017 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/* AXP813/818 Integrated Power Management Chip */
&axp81x {
interrupt-controller;
#interrupt-cells = <1>;
axp_adc: adc {
compatible = "x-powers,axp813-adc";
#io-channel-cells = <1>;
};
axp_gpio: gpio {
compatible = "x-powers,axp813-gpio";
gpio-controller;
#gpio-cells = <2>;
gpio0_ldo: gpio0-ldo {
pins = "GPIO0";
function = "ldo";
};
gpio1_ldo: gpio1-ldo {
pins = "GPIO1";
function = "ldo";
};
};
battery_power_supply: battery-power-supply {
compatible = "x-powers,axp813-battery-power-supply";
status = "disabled";
};
regulators {
/* Default work frequency for buck regulators */
x-powers,dcdc-freq = <3000>;
reg_dcdc1: dcdc1 {
};
reg_dcdc2: dcdc2 {
};
reg_dcdc3: dcdc3 {
};
reg_dcdc4: dcdc4 {
};
reg_dcdc5: dcdc5 {
};
reg_dcdc6: dcdc6 {
};
reg_dcdc7: dcdc7 {
};
reg_aldo1: aldo1 {
};
reg_aldo2: aldo2 {
};
reg_aldo3: aldo3 {
};
reg_dldo1: dldo1 {
};
reg_dldo2: dldo2 {
};
reg_dldo3: dldo3 {
};
reg_dldo4: dldo4 {
};
reg_eldo1: eldo1 {
};
reg_eldo2: eldo2 {
};
reg_eldo3: eldo3 {
};
reg_fldo1: fldo1 {
};
reg_fldo2: fldo2 {
};
reg_fldo3: fldo3 {
};
reg_ldo_io0: ldo-io0 {
pinctrl-names = "default";
pinctrl-0 = <&gpio0_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
reg_ldo_io1: ldo-io1 {
pinctrl-names = "default";
pinctrl-0 = <&gpio1_ldo>;
/* Disable by default to avoid conflicts with GPIO */
status = "disabled";
};
reg_rtc_ldo: rtc-ldo {
/* RTC_LDO is a fixed, always-on regulator */
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_sw: sw {
};
reg_drivevbus: drivevbus {
status = "disabled";
};
};
};

195
arch/arm/dts/sun8i-a83t-allwinner-h8homlet-v2.dts
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@ -44,6 +44,8 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
compatible = "allwinner,h8homlet-v2", "allwinner,sun8i-a83t";
@ -55,22 +57,213 @@
chosen {
stdout-path = "serial0:115200n8";
};
reg_usb0_vbus: reg-usb0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
};
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
};
};
&ehci0 {
status = "okay";
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
bus-width = <4>;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&ohci0 {
status = "okay";
};
&r_rsb {
status = "okay";
axp81x: pmic@3a3 {
compatible = "x-powers,axp818", "x-powers,axp813";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
swin-supply = <&reg_dcdc1>;
};
ac100: codec@e89 {
compatible = "x-powers,ac100";
reg = <0xe89>;
ac100_codec: codec {
compatible = "x-powers,ac100-codec";
interrupt-parent = <&r_pio>;
interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
#clock-cells = <0>;
clock-output-names = "4M_adda";
};
ac100_rtc: rtc {
compatible = "x-powers,ac100-rtc";
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
clocks = <&ac100_codec>;
#clock-cells = <1>;
clock-output-names = "cko1_rtc",
"cko2_rtc",
"cko3_rtc";
};
};
};
#include "axp81x.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dram-pll";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpua";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd-sys";
};
&reg_dldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-mipi";
};
&reg_dldo4 {
/*
* The PHY requires 20ms after all voltages are applied until core
* logic is ready and 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-ephy";
};
&reg_fldo1 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd12-hsic";
};
&reg_fldo2 {
/*
* Despite the embedded CPUs core not being used in any way,
* this must remain on or the system will hang.
*/
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&reg_sw {
regulator-name = "vcc-wifi";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usbphy {
usb0_vbus-supply = <&reg_usb0_vbus>;
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usb_otg {
dr_mode = "host";
status = "okay";
};

298
arch/arm/dts/sun8i-a83t-bananapi-m3.dts
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@ -1,6 +1,7 @@
/*
* Copyright 2015 Vishnu Patekar
* Vishnu Patekar <vishnupatekar0510@gmail.com>
* Copyright 2017 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -44,29 +45,316 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Allwinner A83T BananaPi M3 Board v1.2";
compatible = "bananapi,m3v1.2", "allwinner,sun8i-a83t";
model = "Banana Pi BPI-M3";
compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
connector {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con_in: endpoint {
remote-endpoint = <&hdmi_out_con>;
};
};
};
leds {
compatible = "gpio-leds";
blue {
label = "bananapi-m3:blue:usr";
gpios = <&axp_gpio 1 GPIO_ACTIVE_HIGH>;
};
green {
label = "bananapi-m3:green:usr";
gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>;
};
};
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
/* The WiFi low power clock must be 32768 Hz */
assigned-clocks = <&ac100_rtc 1>;
assigned-clock-rates = <32768>;
/* enables internal regulator and de-asserts reset */
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
};
};
&de {
status = "okay";
};
&ehci0 {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
/* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_sw>;
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii";
allwinner,rx-delay-ps = <700>;
allwinner,tx-delay-ps = <700>;
status = "okay";
};
&hdmi {
status = "okay";
};
&hdmi_out {
hdmi_out_con: endpoint {
remote-endpoint = <&hdmi_con_in>;
};
};
&mdio {
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&r_rsb {
status = "okay";
axp81x: pmic@3a3 {
compatible = "x-powers,axp813";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
fldoin-supply = <&reg_dcdc5>;
swin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
ac100: codec@e89 {
compatible = "x-powers,ac100";
reg = <0xe89>;
ac100_codec: codec {
compatible = "x-powers,ac100-codec";
interrupt-parent = <&r_pio>;
interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
#clock-cells = <0>;
clock-output-names = "4M_adda";
};
ac100_rtc: rtc {
compatible = "x-powers,ac100-rtc";
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
clocks = <&ac100_codec>;
#clock-cells = <1>;
clock-output-names = "cko1_rtc",
"cko2_rtc",
"cko3_rtc";
};
};
};
#include "axp81x.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dram-pll";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_dcdc1 {
/* schematics says 3.1V but FEX file says 3.3V */
regulator-always-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-3v3";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpua";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
/*
* This powers both the WiFi/BT module's main power, I/O supply,
* and external pull-ups on all the data lines. It should be set
* to the same voltage as the I/O supply (DCDC1 in this case) to
* avoid any leakage or mismatch.
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
&reg_dldo3 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-pd";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_fldo1 {
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd12-hsic";
};
&reg_fldo2 {
/*
* Despite the embedded CPUs core not being used in any way,
* this must remain on or the system will hang.
*/
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&reg_sw {
/*
* The PHY requires 20ms after all voltages
* are applied until core logic is ready and
* 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC
* ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-ephy";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};

322
arch/arm/dts/sun8i-a83t-cubietruck-plus.dts
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@ -45,33 +45,353 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Cubietech Cubietruck Plus";
compatible = "cubietech,cubietruck-plus", "allwinner,sun8i-a83t";
aliases {
ethernet0 = &emac;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
blue {
label = "cubietruck-plus:blue:usr";
gpios = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
};
orange {
label = "cubietruck-plus:orange:usr";
gpios = <&pio 3 26 GPIO_ACTIVE_HIGH>; /* PD26 */
};
white {
label = "cubietruck-plus:white:usr";
gpios = <&pio 3 27 GPIO_ACTIVE_HIGH>; /* PD27 */
};
green {
label = "cubietruck-plus:green:usr";
gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */
};
};
usb-hub {
/* I2C is not connected */
compatible = "smsc,usb3503";
initial-mode = <1>; /* initialize in HUB mode */
disabled-ports = <1>;
intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
refclk-frequency = <19200000>;
};
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&pio 3 29 GPIO_ACTIVE_HIGH>; /* PD29 */
};
reg_usb2_vbus: reg-usb2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb2-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
enable-active-high;
gpio = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "On-board SPDIF";
simple-audio-card,cpu {
sound-dai = <&spdif>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
/* The WiFi low power clock must be 32768 Hz */
assigned-clocks = <&ac100_rtc 1>;
assigned-clock-rates = <32768>;
/* enables internal regulator and de-asserts reset */
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
};
};
&ehci0 {
/* GL830 USB-to-SATA bridge here */
status = "okay";
};
&ehci1 {
/* USB3503 HSIC USB 2.0 hub here */
status = "okay";
};
&emac {
pinctrl-names = "default";
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_dldo4>;
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii";
status = "okay";
};
&mdio {
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
status = "okay";
};
&mmc1 {
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_sw>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&mmc2 {
pinctrl-names = "default";
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
vmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&r_rsb {
status = "okay";
axp81x: pmic@3a3 {
compatible = "x-powers,axp818", "x-powers,axp813";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
eldoin-supply = <&reg_dcdc1>;
swin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
ac100: codec@e89 {
compatible = "x-powers,ac100";
reg = <0xe89>;
ac100_codec: codec {
compatible = "x-powers,ac100-codec";
interrupt-parent = <&r_pio>;
interrupts = <0 11 IRQ_TYPE_LEVEL_LOW>; /* PL11 */
#clock-cells = <0>;
clock-output-names = "4M_adda";
};
ac100_rtc: rtc {
compatible = "x-powers,ac100-rtc";
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
clocks = <&ac100_codec>;
#clock-cells = <1>;
clock-output-names = "cko1_rtc",
"cko2_rtc",
"cko3_rtc";
};
};
};
#include "axp81x.dtsi"
&reg_aldo1 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1v8";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dram-pll";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "avcc";
};
&reg_dcdc1 {
/*
* The schematics say this should be 3.3V, but the FEX file says
* it should be 3V. The latter makes sense, as the WiFi module's
* I/O is indirectly powered from DCDC1, through SW. It is rated
* at 2.98V maximum.
*/
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-3v";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpua";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpub";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-always-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-name = "vdd-sys";
};
&reg_dldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "dp-pwr";
};
&reg_dldo3 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "ephy-io";
};
&reg_dldo4 {
/*
* The PHY requires 20ms after all voltages are applied until core
* logic is ready and 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "ephy";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "dp-bridge-1";
};
&reg_eldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "dp-bridge-2";
};
&reg_fldo1 {
/* TODO should be handled by USB PHY */
regulator-always-on;
regulator-min-microvolt = <1080000>;
regulator-max-microvolt = <1320000>;
regulator-name = "vdd12-hsic";
};
&reg_fldo2 {
/*
* Despite the embedded CPUs core not being used in any way,
* this must remain on or the system will hang.
*/
regulator-always-on;
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-cpus";
};
&reg_rtc_ldo {
regulator-name = "vcc-rtc";
};
&reg_sw {
regulator-name = "vcc-wifi-io";
};
&spdif {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usb_otg {
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_usb1_vbus>;
usb2_vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};

355
arch/arm/dts/sun8i-a83t-tbs-a711.dts
View File

@ -1,6 +1,6 @@
/*
* Copyright 2017 Ondřej Jirman
* Ondřej Jirman <megous@megous.com>
* Copyright (C) 2017 Touchless Biometric Systems AG
* Tomas Novotny <tomas@novotny.cz>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -44,33 +44,380 @@
/dts-v1/;
#include "sun8i-a83t.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "TBS A711 Tablet";
compatible = "tbs-biometrics,a711", "allwinner,sun8i-a83t";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
enable-gpios = <&pio 3 29 GPIO_ACTIVE_HIGH>;
brightness-levels = <0 1 2 4 8 16 32 64 128 255>;
default-brightness-level = <9>;
};
panel {
compatible = "tbs,a711-panel", "panel-lvds";
backlight = <&backlight>;
power-supply = <&reg_sw>;
width-mm = <153>;
height-mm = <90>;
data-mapping = "vesa-24";
panel-timing {
/* 1024x600 @60Hz */
clock-frequency = <52000000>;
hactive = <1024>;
vactive = <600>;
hsync-len = <20>;
hfront-porch = <180>;
hback-porch = <160>;
vfront-porch = <12>;
vback-porch = <23>;
vsync-len = <5>;
};
port {
panel_input: endpoint {
remote-endpoint = <&tcon0_out_lcd>;
};
};
};
reg_vbat: reg-vbat {
compatible = "regulator-fixed";
regulator-name = "vbat";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
reg_vmain: reg-vmain {
compatible = "regulator-fixed";
regulator-name = "vmain";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_vbat>;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
/*
* This is actually Bluetooth's clock, but we have to
* hook it up somewheere
*/
clocks = <&ac100_rtc 1>;
clock-names = "ext_clock";
};
};
&cpu0 {
cpu-supply = <&reg_dcdc2>;
};
&cpu100 {
cpu-supply = <&reg_dcdc3>;
};
&de {
status = "okay";
};
/*
* An USB-2 hub is connected here, which also means we don't need to
* enable the OHCI controller.
*/
&ehci0 {
status = "okay";
};
&ohci0 {
/*
* There's a modem connected here that needs to be initialised before
* being able to be enumerated.
*/
&ehci1 {
status = "okay";
};
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
&mmc1 {
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
vmmc-supply = <&reg_dldo1>;
vqmmc-supply = <&reg_dldo1>;
non-removable;
wakeup-source;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&r_pio>;
interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 WL_WAKE_UP */
interrupt-names = "host-wake";
};
};
&mmc2 {
pinctrl-0 = <&mmc2_8bit_emmc_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
cap-mmc-hw-reset;
status = "okay";
};
&pwm {
pinctrl-names = "default";
pinctrl-0 = <&pwm_pin>;
status = "okay";
};
&r_rsb {
status = "okay";
axp81x: pmic@3a3 {
compatible = "x-powers,axp813";
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
swin-supply = <&reg_dcdc1>;
x-powers,drive-vbus-en;
};
ac100: codec@e89 {
compatible = "x-powers,ac100";
reg = <0xe89>;
ac100_codec: codec {
compatible = "x-powers,ac100-codec";
interrupt-parent = <&r_pio>;
interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */
#clock-cells = <0>;
clock-output-names = "4M_adda";
};
ac100_rtc: rtc {
compatible = "x-powers,ac100-rtc";
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
clocks = <&ac100_codec>;
#clock-cells = <1>;
clock-output-names = "cko1_rtc",
"cko2_rtc",
"cko3_rtc";
};
};
};
#include "axp81x.dtsi"
&battery_power_supply {
status = "okay";
};
&reg_aldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-1.8";
};
&reg_aldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-name = "vdd-drampll";
};
&reg_aldo3 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
regulator-name = "avcc";
};
&reg_dcdc1 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-always-on;
regulator-name = "vcc-io";
};
&reg_dcdc2 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-name = "vdd-cpu-A";
};
&reg_dcdc3 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-name = "vdd-cpu-B";
};
&reg_dcdc4 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-name = "vdd-gpu";
};
&reg_dcdc5 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-name = "vcc-dram";
};
&reg_dcdc6 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-always-on;
regulator-name = "vdd-sys";
};
&reg_dldo1 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-wifi-io";
};
&reg_dldo2 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <4200000>;
regulator-name = "vcc-mipi";
};
&reg_dldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "vdd-csi";
};
&reg_dldo4 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-name = "avdd-csi";
};
&reg_drivevbus {
regulator-name = "usb0-vbus";
status = "okay";
};
&reg_eldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-r";
};
&reg_eldo2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc-dsi";
};
&reg_eldo3 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1800000>;
regulator-name = "dvdd-csi-f";
};
&reg_fldo1 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-name = "vcc-hsic";
};
&reg_fldo2 {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-name = "vdd-cpus";
};
&reg_ldo_io0 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-ctp";
status = "okay";
};
&reg_ldo_io1 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-vb";
status = "okay";
};
&reg_sw {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3100000>;
regulator-name = "vcc-lcd";
};
&tcon0 {
pinctrl-names = "default";
pinctrl-0 = <&lcd_lvds_pins>;
};
&tcon0_out {
tcon0_out_lcd: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_input>;
};
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_b>;
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
/* There's the BT part of the AP6210 connected to that UART */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
status = "okay";
};
&usb_otg {
dr_mode = "otg";
status = "okay";
};
&usbphy {
usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
usb0_vbus-supply = <&reg_drivevbus>;
usb1_vbus_supply = <&reg_vmain>;
usb2_vbus_supply = <&reg_vmain>;
status = "okay";
};

891
arch/arm/dts/sun8i-a83t.dtsi
View File

File diff suppressed because it is too large Load Diff

168
arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts
View File

@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
* Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -43,6 +44,8 @@
/dts-v1/;
#include "sun8i-r40.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Banana Pi BPI-M2-Ultra";
compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40";
@ -55,17 +58,47 @@
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pwr-led {
label = "bananapi:red:pwr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
user-led-green {
label = "bananapi:green:user";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
};
user-led-blue {
label = "bananapi:blue:user";
gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>;
};
};
reg_vcc5v0: vcc5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
enable-active-high;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
&ehci1 {
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
&ehci2 {
status = "okay";
};
@ -74,6 +107,7 @@
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_dc1sw>;
status = "okay";
};
@ -83,3 +117,123 @@
reg = <1>;
};
};
&i2c0 {
status = "okay";
axp22x: pmic@34 {
compatible = "x-powers,axp221";
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
};
#include "axp22x.dtsi"
&mmc0 {
vmmc-supply = <&reg_dcdc1>;
bus-width = <4>;
cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
cd-inverted;
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <&reg_dldo2>;
vqmmc-supply = <&reg_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&mmc2 {
vmmc-supply = <&reg_dcdc1>;
vqmmc-supply = <&reg_dcdc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
&ohci1 {
status = "okay";
};
&ohci2 {
status = "okay";
};
&reg_aldo2 {
regulator-always-on;
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-name = "vcc-pa";
};
&reg_aldo3 {
regulator-always-on;
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3300000>;
regulator-name = "avcc";
};
&reg_dc1sw {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-gmac-phy";
};
&reg_dcdc1 {
regulator-always-on;
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-name = "vcc-3v0";
};
&reg_dcdc2 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-cpu";
};
&reg_dcdc3 {
regulator-always-on;
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1300000>;
regulator-name = "vdd-sys";
};
&reg_dcdc5 {
regulator-always-on;
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-name = "vcc-dram";
};
&reg_dldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi-io";
};
&reg_dldo2 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc-wifi";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_vcc5v0>;
usb2_vbus-supply = <&reg_vcc5v0>;
status = "okay";
};

305
arch/arm/dts/sun8i-r40.dtsi
View File

@ -1,7 +1,6 @@
/*
* Copyright 2016 Chen-Yu Tsai
*
* Chen-Yu Tsai <wens@csie.org>
* Copyright 2017 Chen-Yu Tsai <wens@csie.org>
* Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -51,24 +50,19 @@
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
};
chosen {
};
clocks {
#address-cells = <1>;
#size-cells = <1>;
ranges;
osc24M: osc24M_clk {
osc24M: osc24M {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "osc24M";
};
osc32k: osc32k_clk {
osc32k: osc32k {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
@ -80,7 +74,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
cpu@0 {
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
@ -105,11 +99,6 @@
};
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x80000000>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
@ -140,6 +129,122 @@
#size-cells = <0>;
};
mmc1: mmc@1c10000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
reg = <0x01c10000 0x1000>;
clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc2: mmc@1c11000 {
compatible = "allwinner,sun8i-r40-emmc",
"allwinner,sun50i-a64-emmc";
reg = <0x01c11000 0x1000>;
clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC2>;
reset-names = "ahb";
pinctrl-0 = <&mmc2_pins>;
pinctrl-names = "default";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
mmc3: mmc@1c12000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
reg = <0x01c12000 0x1000>;
clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC3>;
reset-names = "ahb";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
usbphy: phy@1c13400 {
compatible = "allwinner,sun8i-r40-usb-phy";
reg = <0x01c13400 0x14>,
<0x01c14800 0x4>,
<0x01c19800 0x4>,
<0x01c1c800 0x4>;
reg-names = "phy_ctrl",
"pmu0",
"pmu1",
"pmu2";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>,
<&ccu CLK_USB_PHY2>;
clock-names = "usb0_phy",
"usb1_phy",
"usb2_phy";
resets = <&ccu RST_USB_PHY0>,
<&ccu RST_USB_PHY1>,
<&ccu RST_USB_PHY2>;
reset-names = "usb0_reset",
"usb1_reset",
"usb2_reset";
status = "disabled";
#phy-cells = <1>;
};
ehci1: usb@1c19000 {
compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
reg = <0x01c19000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI1>;
resets = <&ccu RST_BUS_EHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ohci1: usb@1c19400 {
compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
reg = <0x01c19400 0x100>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI1>,
<&ccu CLK_USB_OHCI1>;
resets = <&ccu RST_BUS_OHCI1>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
};
ehci2: usb@1c1c000 {
compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
reg = <0x01c1c000 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_EHCI2>;
resets = <&ccu RST_BUS_EHCI2>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ohci2: usb@1c1c400 {
compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
reg = <0x01c1c400 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_OHCI2>,
<&ccu CLK_USB_OHCI2>;
resets = <&ccu RST_BUS_OHCI2>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
};
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
@ -153,8 +258,7 @@
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
/* apb should be replaced once CCU is implemented */
clocks = <&osc24M>, <&osc24M>, <&osc32k>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -174,10 +278,9 @@
drive-strength = <40>;
};
i2c0_pins: i2c0_pins {
i2c0_pins: i2c0-pins {
pins = "PB0", "PB1";
function = "i2c0";
bias-pull-up;
};
mmc0_pins: mmc0-pins {
@ -188,11 +291,32 @@
bias-pull-up;
};
uart0_pb_pins: uart0_pb_pins {
pins = "PB22", "PB23";
function = "uart0";
mmc1_pg_pins: mmc1-pg-pins {
pins = "PG0", "PG1", "PG2",
"PG3", "PG4", "PG5";
function = "mmc1";
drive-strength = <30>;
bias-pull-up;
};
mmc2_pins: mmc2-pins {
pins = "PC5", "PC6", "PC7", "PC8", "PC9",
"PC10", "PC11", "PC12", "PC13", "PC14",
"PC15", "PC24";
function = "mmc2";
drive-strength = <30>;
bias-pull-up;
};
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
};
};
wdt: watchdog@1c20c90 {
compatible = "allwinner,sun4i-a10-wdt";
reg = <0x01c20c90 0x10>;
};
uart0: serial@1c28000 {
@ -201,7 +325,85 @@
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&osc24M>;
clocks = <&ccu CLK_BUS_UART0>;
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
uart1: serial@1c28400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28400 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
uart2: serial@1c28800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28800 0x400>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
uart3: serial@1c28c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28c00 0x400>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART3>;
resets = <&ccu RST_BUS_UART3>;
status = "disabled";
};
uart4: serial@1c29000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29000 0x400>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART4>;
resets = <&ccu RST_BUS_UART4>;
status = "disabled";
};
uart5: serial@1c29400 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29400 0x400>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART5>;
resets = <&ccu RST_BUS_UART5>;
status = "disabled";
};
uart6: serial@1c29800 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29800 0x400>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART6>;
resets = <&ccu RST_BUS_UART6>;
status = "disabled";
};
uart7: serial@1c29c00 {
compatible = "snps,dw-apb-uart";
reg = <0x01c29c00 0x400>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART7>;
resets = <&ccu RST_BUS_UART7>;
status = "disabled";
};
@ -209,7 +411,54 @@
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2ac00 0x400>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
clocks = <&ccu CLK_BUS_I2C0>;
resets = <&ccu RST_BUS_I2C0>;
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c1: i2c@1c2b000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b000 0x400>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C1>;
resets = <&ccu RST_BUS_I2C1>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c2: i2c@1c2b400 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b400 0x400>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C2>;
resets = <&ccu RST_BUS_I2C2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c3: i2c@1c2b800 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2b800 0x400>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C3>;
resets = <&ccu RST_BUS_I2C3>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
i2c4: i2c@1c2c000 {
compatible = "allwinner,sun6i-a31-i2c";
reg = <0x01c2c000 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_I2C4>;
resets = <&ccu RST_BUS_I2C4>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@ -237,7 +486,7 @@
};
gic: interrupt-controller@1c81000 {
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,
<0x01c82000 0x1000>,
<0x01c84000 0x2000>,
@ -254,7 +503,5 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
arm,cpu-registers-not-fw-configured;
};
};

50
arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts
View File

@ -56,6 +56,40 @@
chosen {
stdout-path = "serial0:115200n8";
};
leds {
compatible = "gpio-leds";
pwr-led {
label = "bananapi:red:pwr";
gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
user-led {
label = "bananapi:green:user";
gpios = <&pio 7 21 GPIO_ACTIVE_HIGH>;
};
};
reg_vcc5v0: vcc5v0 {
compatible = "regulator-fixed";
regulator-name = "vcc5v0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */
enable-active-high;
};
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */
};
};
&ehci1 {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
};
&i2c0 {
@ -125,8 +159,24 @@
status = "okay";
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pg_pins>;
vmmc-supply = <&reg_dldo2>;
vqmmc-supply = <&reg_dldo1>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
status = "okay";
};
&usbphy {
usb1_vbus-supply = <&reg_vcc5v0>;
status = "okay";
};

2
arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h
View File

@ -20,7 +20,7 @@
#define SUNXI_DMA_BASE 0x03002000
/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
#define SUNXI_SIDC_BASE 0x03006000
#define SNUXI_SID_BASE 0x03006200
#define SUNXI_SID_BASE 0x03006200
#define SUNXI_TIMER_BASE 0x03009000
#define SUNXI_PIO_BASE 0x0300B000
#define SUNXI_PSI_BASE 0x0300C000

1
arch/arm/mach-sunxi/Kconfig
View File

@ -417,7 +417,6 @@ config DRAM_ZQ
config DRAM_ODT_EN
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_R40
default y if MACH_SUN50I

2
board/sunxi/board.c
View File

@ -503,7 +503,6 @@ static void mmc_pinmux_setup(int sdc)
int board_mmc_init(bd_t *bis)
{
__maybe_unused struct mmc *mmc0, *mmc1;
__maybe_unused char buf[512];
mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
@ -759,7 +758,6 @@ static void setup_environment(const void *fdt)
int misc_init_r(void)
{
__maybe_unused int ret;
uint boot;
env_set("fel_booted", NULL);

2
configs/A20-OLinuXino_MICRO-eMMC_defconfig
View File

@ -8,7 +8,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_I2C1_ENABLE=y
CONFIG_VIDEO_VGA=y
CONFIG_SATAPWR="PB8"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro"
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olinuxino-micro-emmc"
CONFIG_AHCI=y
CONFIG_NR_DRAM_BANKS=1
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

1
configs/Bananapi_M2_Ultra_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MACPWR="PA17"
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_MMC_SUNXI_SLOT_EXTRA=2

1
configs/amarula_a64_relic_defconfig
View File

@ -3,7 +3,6 @@ CONFIG_ARCH_SUNXI=y
CONFIG_SPL=y
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
# CONFIG_VIDEO_DE2 is not set
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-amarula-relic"

1
configs/bananapi_m2_berry_defconfig
View File

@ -4,7 +4,6 @@ CONFIG_SPL=y
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_DRAM_ZQ=3881979
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"
CONFIG_AHCI=y

1
configs/sopine_baseboard_defconfig
View File

@ -6,7 +6,6 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=3881949
CONFIG_DRAM_ODT_EN=y
CONFIG_MMC0_CD_PIN=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y

8
drivers/clk/Kconfig
View File

@ -83,13 +83,13 @@ config CLK_STM32MP1
Enable the STM32 clock (RCC) driver. Enable support for
manipulating STM32MP1's on-SoC clocks.
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
config ICS8N3QV01
bool "Enable ICS8N3QV01 VCXO driver"

140
include/dt-bindings/clock/sun8i-a83t-ccu.h Normal file
View File

@ -0,0 +1,140 @@
/*
* Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_
#define CLK_PLL_PERIPH 6
#define CLK_PLL_DE 9
#define CLK_C0CPUX 11
#define CLK_C1CPUX 12
#define CLK_BUS_MIPI_DSI 19
#define CLK_BUS_SS 20
#define CLK_BUS_DMA 21
#define CLK_BUS_MMC0 22
#define CLK_BUS_MMC1 23
#define CLK_BUS_MMC2 24
#define CLK_BUS_NAND 25
#define CLK_BUS_DRAM 26
#define CLK_BUS_EMAC 27
#define CLK_BUS_HSTIMER 28
#define CLK_BUS_SPI0 29
#define CLK_BUS_SPI1 30
#define CLK_BUS_OTG 31
#define CLK_BUS_EHCI0 32
#define CLK_BUS_EHCI1 33
#define CLK_BUS_OHCI0 34
#define CLK_BUS_VE 35
#define CLK_BUS_TCON0 36
#define CLK_BUS_TCON1 37
#define CLK_BUS_CSI 38
#define CLK_BUS_HDMI 39
#define CLK_BUS_DE 40
#define CLK_BUS_GPU 41
#define CLK_BUS_MSGBOX 42
#define CLK_BUS_SPINLOCK 43
#define CLK_BUS_SPDIF 44
#define CLK_BUS_PIO 45
#define CLK_BUS_I2S0 46
#define CLK_BUS_I2S1 47
#define CLK_BUS_I2S2 48
#define CLK_BUS_TDM 49
#define CLK_BUS_I2C0 50
#define CLK_BUS_I2C1 51
#define CLK_BUS_I2C2 52
#define CLK_BUS_UART0 53
#define CLK_BUS_UART1 54
#define CLK_BUS_UART2 55
#define CLK_BUS_UART3 56
#define CLK_BUS_UART4 57
#define CLK_NAND 59
#define CLK_MMC0 60
#define CLK_MMC0_SAMPLE 61
#define CLK_MMC0_OUTPUT 62
#define CLK_MMC1 63
#define CLK_MMC1_SAMPLE 64
#define CLK_MMC1_OUTPUT 65
#define CLK_MMC2 66
#define CLK_MMC2_SAMPLE 67
#define CLK_MMC2_OUTPUT 68
#define CLK_SS 69
#define CLK_SPI0 70
#define CLK_SPI1 71
#define CLK_I2S0 72
#define CLK_I2S1 73
#define CLK_I2S2 74
#define CLK_TDM 75
#define CLK_SPDIF 76
#define CLK_USB_PHY0 77
#define CLK_USB_PHY1 78
#define CLK_USB_HSIC 79
#define CLK_USB_HSIC_12M 80
#define CLK_USB_OHCI0 81
#define CLK_DRAM_VE 83
#define CLK_DRAM_CSI 84
#define CLK_TCON0 85
#define CLK_TCON1 86
#define CLK_CSI_MISC 87
#define CLK_MIPI_CSI 88
#define CLK_CSI_MCLK 89
#define CLK_CSI_SCLK 90
#define CLK_VE 91
#define CLK_AVS 92
#define CLK_HDMI 93
#define CLK_HDMI_SLOW 94
#define CLK_MIPI_DSI0 96
#define CLK_MIPI_DSI1 97
#define CLK_GPU_CORE 98
#define CLK_GPU_MEMORY 99
#define CLK_GPU_HYD 100
#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */

98
include/dt-bindings/reset/sun8i-a83t-ccu.h Normal file
View File

@ -0,0 +1,98 @@
/*
* Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_
#define RST_USB_PHY0 0
#define RST_USB_PHY1 1
#define RST_USB_HSIC 2
#define RST_DRAM 3
#define RST_MBUS 4
#define RST_BUS_MIPI_DSI 5
#define RST_BUS_SS 6
#define RST_BUS_DMA 7
#define RST_BUS_MMC0 8
#define RST_BUS_MMC1 9
#define RST_BUS_MMC2 10
#define RST_BUS_NAND 11
#define RST_BUS_DRAM 12
#define RST_BUS_EMAC 13
#define RST_BUS_HSTIMER 14
#define RST_BUS_SPI0 15
#define RST_BUS_SPI1 16
#define RST_BUS_OTG 17
#define RST_BUS_EHCI0 18
#define RST_BUS_EHCI1 19
#define RST_BUS_OHCI0 20
#define RST_BUS_VE 21
#define RST_BUS_TCON0 22
#define RST_BUS_TCON1 23
#define RST_BUS_CSI 24
#define RST_BUS_HDMI0 25
#define RST_BUS_HDMI1 26
#define RST_BUS_DE 27
#define RST_BUS_GPU 28
#define RST_BUS_MSGBOX 29
#define RST_BUS_SPINLOCK 30
#define RST_BUS_LVDS 31
#define RST_BUS_SPDIF 32
#define RST_BUS_I2S0 33
#define RST_BUS_I2S1 34
#define RST_BUS_I2S2 35
#define RST_BUS_TDM 36
#define RST_BUS_I2C0 37
#define RST_BUS_I2C1 38
#define RST_BUS_I2C2 39
#define RST_BUS_UART0 40
#define RST_BUS_UART1 41
#define RST_BUS_UART2 42
#define RST_BUS_UART3 43
#define RST_BUS_UART4 44
#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */