ppc4xx: Remove lcd4_lwmon5 support
This platform has not gone into production. So lets remove it. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Stefan Roese
Tom Rini
parent
c0c7a55428
commit
b6b5e394db
@ -10,7 +10,6 @@ choice
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config TARGET_LWMON5
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bool "Support lwmon5"
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select SUPPORT_SPL
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config TARGET_T3CORP
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bool "Support t3corp"
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@ -3,5 +3,4 @@ M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/lwmon5/
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F: include/configs/lwmon5.h
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F: configs/lcd4_lwmon5_defconfig
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F: configs/lwmon5_defconfig
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@ -187,11 +187,9 @@ int misc_init_r(void)
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u32 pbcr;
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int size_val = 0;
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u32 reg;
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#ifndef CONFIG_LCD4_LWMON5
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1, sdr0_srst;
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#endif
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/*
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* FLASH stuff...
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@ -222,7 +220,6 @@ int misc_init_r(void)
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CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[cfi_flash_num_flash_banks - 1]);
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#ifndef CONFIG_LCD4_LWMON5
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/*
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* USB suff...
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*/
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@ -296,7 +293,6 @@ int misc_init_r(void)
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/* 7. Reassert internal PHY reset: */
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mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
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udelay(1000);
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#endif
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/*
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* Clear resets
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@ -304,9 +300,7 @@ int misc_init_r(void)
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mtsdr(SDR0_SRST1, 0x00000000);
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mtsdr(SDR0_SRST0, 0x00000000);
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#ifndef CONFIG_LCD4_LWMON5
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printf("USB: Host(int phy) Device(ext phy)\n");
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#endif
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/*
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* Clear PLB4A0_ACR[WRP]
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@ -316,12 +310,10 @@ int misc_init_r(void)
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reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
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mtdcr(PLB4A0_ACR, reg);
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#ifndef CONFIG_LCD4_LWMON5
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/*
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* Init matrix keyboard
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*/
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misc_init_r_kbd();
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#endif
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return 0;
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}
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@ -147,7 +147,6 @@ static void program_ecc(u32 start_address,
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************************************************************************/
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phys_size_t initdram (int board_type)
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{
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5)
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/* CL=4 */
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mtsdram(DDR0_02, 0x00000000);
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@ -241,7 +240,6 @@ phys_size_t initdram (int board_type)
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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#endif /* CONFIG_SPL_BUILD */
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return (CONFIG_SYS_MBYTES_SDRAM << 20);
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}
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@ -1,6 +0,0 @@
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CONFIG_PPC=y
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CONFIG_4xx=y
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CONFIG_TARGET_LWMON5=y
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CONFIG_SPL=y
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CONFIG_SYS_EXTRA_OPTIONS="LCD4_LWMON5"
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# CONFIG_CMD_SETEXPR is not set
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@ -25,13 +25,8 @@
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#define CONFIG_SYS_GENERIC_BOARD
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#ifdef CONFIG_LCD4_LWMON5
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#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
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#define CONFIG_HOSTNAME lcd4_lwmon5
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#else
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#define CONFIG_SYS_TEXT_BASE 0xFFF80000
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#define CONFIG_HOSTNAME lwmon5
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#endif
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#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
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@ -67,11 +62,9 @@
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#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
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#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
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#ifndef CONFIG_LCD4_LWMON5
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#define CONFIG_SYS_USB2D0_BASE 0xe0000100
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#define CONFIG_SYS_USB_DEVICE 0xe0000000
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#define CONFIG_SYS_USB_HOST 0xe0000400
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#endif
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/*
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* Initial RAM & stack pointer
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@ -81,20 +74,13 @@
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* content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
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* for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
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*/
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#ifndef CONFIG_LCD4_LWMON5
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#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
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#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#else
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
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#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
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#endif
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/* unused GPT0 COMP reg */
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#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
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#define CONFIG_SYS_OCM_SIZE (16 << 10)
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@ -168,11 +154,8 @@
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#define CONFIG_SYS_MBYTES_SDRAM 256
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#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#ifndef CONFIG_LCD4_LWMON5
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#define CONFIG_DDR_ECC /* enable ECC */
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#endif
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#ifndef CONFIG_LCD4_LWMON5
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/* POST support */
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#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
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CONFIG_SYS_POST_CPU | \
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@ -281,7 +264,6 @@
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#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
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#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
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#endif
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/*
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* I2C
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@ -401,7 +383,6 @@
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#define CONFIG_VIDEO_SW_CURSOR
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#define CONFIG_SPLASH_SCREEN
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#ifndef CONFIG_LCD4_LWMON5
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/*
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* USB/EHCI
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*/
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@ -417,7 +398,6 @@
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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#endif
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/*
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* BOOTP options
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@ -448,11 +428,9 @@
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#define CONFIG_CMD_BMP
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#endif
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#ifndef CONFIG_LCD4_LWMON5
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#ifdef CONFIG_440EPX
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#define CONFIG_CMD_USB
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#endif
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#endif
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/*
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* Miscellaneous configurable options
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@ -485,13 +463,11 @@
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#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
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#ifndef CONFIG_LCD4_LWMON5
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#ifndef DEBUG
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#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
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#endif
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#define CONFIG_WD_PERIOD 40000 /* in usec */
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#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
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#endif
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/*
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* For booting Linux, the board info and command line data
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@ -572,12 +548,7 @@
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#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
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#define CONFIG_SYS_GPIO_WATCHDOG 63
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/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
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#ifdef CONFIG_LCD4_LWMON5
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#define GPIO49_VAL 0
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#else
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#define GPIO49_VAL 1
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#endif
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/*
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* PPC440 GPIO Configuration
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@ -659,36 +630,4 @@
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* SPL related defines
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*/
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#ifdef CONFIG_LCD4_LWMON5
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SPL_NOR_SUPPORT
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#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
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#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
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#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
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#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
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#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
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#define CONFIG_SPL_SERIAL_SUPPORT
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/* Place BSS for SPL near end of SDRAM */
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#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
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#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
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#define CONFIG_SPL_OS_BOOT
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/* Place patched DT blob (fdt) at this address */
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#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
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#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
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/* Settings for real U-Boot to be loaded from NOR flash */
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#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_SYS_UBOOT_START 0x01002100
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#define CONFIG_SYS_OS_BASE 0xf8000000
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#define CONFIG_SYS_FDT_BASE 0xf87c0000
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#endif
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#endif /* __CONFIG_H */
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