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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Tom Rini 2014-02-04 10:22:23 -05:00
commit b66af14dc9
34 changed files with 1229 additions and 360 deletions
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6
README
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@ -472,6 +472,12 @@ The following options need to be configured:
Board config to use DDR3. It can be enabled for SoCs with Board config to use DDR3. It can be enabled for SoCs with
Freescale DDR3 controllers. Freescale DDR3 controllers.
CONFIG_SYS_FSL_IFC_BE
Defines the IFC controller register space as Big Endian
CONFIG_SYS_FSL_IFC_LE
Defines the IFC controller register space as Little Endian
CONFIG_SYS_FSL_PBL_PBI CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in built image. It enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details Please refer doc/README.pblimage for more details

2
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
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@ -75,6 +75,8 @@ static const char *serdes_prtcl_str[] = {
[XFI_FM2_MAC9] = "XFI_FM2_MAC9", [XFI_FM2_MAC9] = "XFI_FM2_MAC9",
[XFI_FM2_MAC10] = "XFI_FM2_MAC10", [XFI_FM2_MAC10] = "XFI_FM2_MAC10",
[INTERLAKEN] = "INTERLAKEN", [INTERLAKEN] = "INTERLAKEN",
[QSGMII_SW1_A] = "QSGMII_SW1_A",
[QSGMII_SW1_B] = "QSGMII_SW1_B",
}; };
#endif #endif

36
arch/powerpc/cpu/mpc85xx/t1040_ids.c
View File

@ -21,21 +21,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
SET_QP_INFO(8, 34, 1, 3), SET_QP_INFO(8, 34, 1, 3),
SET_QP_INFO(9, 35, 1, 0), SET_QP_INFO(9, 35, 1, 0),
SET_QP_INFO(10, 36, 1, 0), SET_QP_INFO(10, 36, 1, 0),
SET_QP_INFO(11, 37, 1, 1),
SET_QP_INFO(12, 38, 1, 1),
SET_QP_INFO(13, 39, 1, 2),
SET_QP_INFO(14, 40, 1, 2),
SET_QP_INFO(15, 41, 1, 3),
SET_QP_INFO(16, 42, 1, 3),
SET_QP_INFO(17, 43, 1, 0),
SET_QP_INFO(18, 44, 1, 0),
SET_QP_INFO(19, 45, 1, 1),
SET_QP_INFO(20, 46, 1, 1),
SET_QP_INFO(21, 47, 1, 2),
SET_QP_INFO(22, 48, 1, 2),
SET_QP_INFO(23, 49, 1, 3),
SET_QP_INFO(24, 50, 1, 3),
SET_QP_INFO(25, 51, 1, 0),
}; };
#endif #endif
@ -60,11 +45,6 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(1, 147), SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227), SET_DMA_LIODN(2, 227),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
/* SET_NEXUS_LIODN(557), -- not yet implemented */ /* SET_NEXUS_LIODN(557), -- not yet implemented */
}; };
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
@ -77,8 +57,6 @@ struct liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 3, 91), SET_FMAN_RX_1G_LIODN(1, 3, 91),
SET_FMAN_RX_1G_LIODN(1, 4, 92), SET_FMAN_RX_1G_LIODN(1, 4, 92),
SET_FMAN_RX_1G_LIODN(1, 5, 93), SET_FMAN_RX_1G_LIODN(1, 5, 93),
SET_FMAN_RX_10G_LIODN(1, 0, 94),
SET_FMAN_RX_10G_LIODN(1, 1, 95),
}; };
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif #endif
@ -97,23 +75,9 @@ struct liodn_id_table sec_liodn_tbl[] = {
}; };
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
#ifdef CONFIG_SYS_DPAA_RMAN
struct liodn_id_table rman_liodn_tbl[] = {
/* Set RMan block 0-3 liodn offset */
SET_RMAN_LIODN(0, 678),
SET_RMAN_LIODN(1, 679),
SET_RMAN_LIODN(2, 680),
SET_RMAN_LIODN(3, 681),
};
int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
#endif
struct liodn_id_table liodn_bases[] = { struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
#endif #endif
#ifdef CONFIG_SYS_DPAA_RMAN
[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
#endif
}; };

69
arch/powerpc/cpu/mpc85xx/t1040_serdes.c
View File

@ -8,68 +8,59 @@
#include <asm/fsl_serdes.h> #include <asm/fsl_serdes.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h> #include <asm/io.h>
#include "fsl_corenet2_serdes.h"
static u8 serdes_cfg_tbl[MAX_SERDES][0xC4][SRDS_MAX_LANES] = {
{ /* SerDes 1 */ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
[0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B, [0x00] = {PCIE1, PCIE1, PCIE1, PCIE1,
PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
[0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE3, PCIE4, SATA1},
[0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE2, PCIE2, PCIE2},
[0x8D] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
PCIE2, SGMII_SW1_DTSEC6, SGMII_SW1_DTSEC4, SGMII_SW1_DTSEC5},
[0x89] = {PCIE1, SGMII_SW1_DTSEC3, SGMII_SW1_DTSEC1, SGMII_SW1_DTSEC2,
PCIE2, PCIE3, SGMII_SW1_DTSEC4, SATA1},
[0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SATA1},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE2, PCIE2, PCIE2}, PCIE2, PCIE2, PCIE2, PCIE2},
[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, [0x06] = {PCIE1, PCIE1, PCIE1, PCIE1,
PCIE2, PCIE3, PCIE4, SATA1}, PCIE2, PCIE3, PCIE4, SATA1},
[0x08] = {PCIE1, PCIE1, PCIE1, PCIE1, [0x08] = {PCIE1, PCIE1, PCIE1, PCIE1,
PCIE2, PCIE3, SATA2, SATA1}, PCIE2, PCIE3, SATA2, SATA1},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, [0x40] = {PCIE1, PCIE1, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, PCIE2, PCIE2, PCIE2, PCIE2},
[0x60] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE2, PCIE2, PCIE2},
[0x66] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE3, PCIE4, SATA1},
[0x67] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0x69] = {PCIE1, SGMII_FM1_DTSEC3, QSGMII_SW1_A, QSGMII_SW1_B,
PCIE2, PCIE3, SGMII_FM1_DTSEC4, SATA1},
[0x86] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SATA1},
[0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, [0x85] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, [0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5}, PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, [0xA7] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE2, PCIE2, PCIE2}, PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
}, [0xAA] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
{ PCIE2, PCIE3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
},
{
},
{
},
}; };
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{ {
return serdes_cfg_tbl[serdes][cfg][lane]; return serdes_cfg_tbl[cfg][lane];
} }
int is_serdes_prtcl_valid(int serdes, u32 prtcl) int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{ {
int i; int i;
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl[serdes])) if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0; return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) { for (i = 0; i < SRDS_MAX_LANES; i++) {
if (serdes_cfg_tbl[serdes][prtcl][i] != NONE) if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1; return 1;
} }

6
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -22,6 +22,9 @@
#define FSL_DDR_VER_4_7 47 #define FSL_DDR_VER_4_7 47
#define FSL_DDR_VER_5_0 50 #define FSL_DDR_VER_5_0 50
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
/* Number of TLB CAM entries we have on FSL Book-E chips */ /* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC) #if defined(CONFIG_E500MC)
#define CONFIG_SYS_NUM_TLBCAMS 64 #define CONFIG_SYS_NUM_TLBCAMS 64
@ -717,8 +720,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000

8
arch/powerpc/include/asm/fsl_serdes.h
View File

@ -69,13 +69,7 @@ enum srds_prtcl {
XFI_FM2_MAC9, XFI_FM2_MAC9,
XFI_FM2_MAC10, XFI_FM2_MAC10,
INTERLAKEN, INTERLAKEN,
SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */ QSGMII_SW1_A, /* Indicates ports on L2 Switch */
SGMII_SW1_DTSEC2,
SGMII_SW1_DTSEC3,
SGMII_SW1_DTSEC4,
SGMII_SW1_DTSEC5,
SGMII_SW1_DTSEC6,
QSGMII_SW1_A, /* SW indicates on L2 swtich */
QSGMII_SW1_B, QSGMII_SW1_B,
}; };

11
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1759,6 +1759,17 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24

1
board/freescale/t1040qds/Makefile
View File

@ -9,3 +9,4 @@ obj-y += ddr.o
obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_PCI) += pci.o
obj-y += law.o obj-y += law.o
obj-y += tlb.o obj-y += tlb.o
obj-y += eth.o

6
board/freescale/t1040qds/README
View File

@ -121,14 +121,14 @@ NOR Flash memory Map on T1040QDS
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB

492
board/freescale/t1040qds/eth.c Normal file
View File

@ -0,0 +1,492 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* The RGMII PHYs are provided by the two on-board PHY connected to
* dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
* PHY or by the standard four-port SGMII riser card (VSC).
*/
#include <common.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <asm/immap_85xx.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/fsl_dtsec.h>
#include "../common/fman.h"
#include "../common/qixis.h"
#include "t1040qds_qixis.h"
#ifdef CONFIG_FMAN_ENET
/* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D
* Bank 2 -> Lanes E, F, G, H
*/
/* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
* means that the mapping must be determined dynamically, or that the lane
* maps to something other than a board slot.
*/
static u8 lane_to_slot[] = {
0, 0, 0, 0, 0, 0, 0, 0
};
/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
* housed.
*/
static int riser_phy_addr[] = {
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
};
/* Slot2 does not have EMI connections */
#define EMI_NONE 0xFFFFFFFF
#define EMI1_RGMII0 0
#define EMI1_RGMII1 1
#define EMI1_SLOT1 2
#define EMI1_SLOT3 3
#define EMI1_SLOT4 4
#define EMI1_SLOT5 5
#define EMI1_SLOT6 6
#define EMI1_SLOT7 7
#define EMI2 8
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
"T1040_QDS_MDIO0",
"T1040_QDS_MDIO1",
"T1040_QDS_MDIO2",
"T1040_QDS_MDIO3",
"T1040_QDS_MDIO4",
"T1040_QDS_MDIO5",
"T1040_QDS_MDIO6",
"T1040_QDS_MDIO7",
};
struct t1040_qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
const char *name = t1040_qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
static void t1040_qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
if (muxval <= 7) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
QIXIS_WRITE(brdcfg[4], brdcfg4);
}
}
static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct t1040_qds_mdio *priv = bus->priv;
t1040_qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct t1040_qds_mdio *priv = bus->priv;
t1040_qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int t1040_qds_mdio_reset(struct mii_dev *bus)
{
struct t1040_qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
{
struct t1040_qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate t1040_qds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate t1040_qds private data\n");
free(bus);
return -1;
}
bus->read = t1040_qds_mdio_read;
bus->write = t1040_qds_mdio_write;
bus->reset = t1040_qds_mdio_reset;
sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
/*
* Initialize the lane_to_slot[] array.
*
* On the T1040QDS board the mapping is controlled by ?? register.
*/
static void initialize_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
>> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
QIXIS_WRITE(cms[0], 0x07);
switch (serdes1_prtcl) {
case 0x60:
case 0x66:
case 0x67:
case 0x69:
lane_to_slot[1] = 7;
lane_to_slot[2] = 6;
lane_to_slot[3] = 5;
break;
case 0x86:
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
break;
case 0x87:
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
lane_to_slot[7] = 7;
break;
case 0x89:
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
lane_to_slot[7] = 7;
break;
case 0x8d:
lane_to_slot[1] = 7;
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
lane_to_slot[5] = 3;
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
case 0x8F:
case 0x85:
lane_to_slot[1] = 7;
lane_to_slot[2] = 6;
lane_to_slot[3] = 5;
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
case 0xA5:
lane_to_slot[1] = 7;
lane_to_slot[6] = 3;
lane_to_slot[7] = 3;
break;
case 0xA7:
lane_to_slot[1] = 7;
lane_to_slot[7] = 7;
break;
case 0xAA:
lane_to_slot[1] = 7;
lane_to_slot[6] = 7;
lane_to_slot[7] = 7;
break;
case 0x40:
lane_to_slot[2] = 7;
lane_to_slot[3] = 7;
break;
default:
printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
}
/*
* Given the following ...
*
* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
* compatible string and 'addr' physical address)
*
* 2) An Fman port
*
* ... update the phy-handle property of the Ethernet node to point to the
* right PHY. This assumes that we already know the PHY for each port.
*
* The offset of the Fman Ethernet node is also passed in for convenience, but
* it is not used, and we recalculate the offset anyway.
*
* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
* Inside the Fman, "ports" are things that connect to MACs. We only call them
* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
* and ports are the same thing.
*
*/
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
phy_interface_t intf = fm_info_get_enet_if(port);
char phy[16];
/* The RGMII PHY is identified by the MAC connected to it */
if (intf == PHY_INTERFACE_MODE_RGMII) {
sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
fdt_set_phy_handle(fdt, compat, addr, phy);
}
/* The SGMII PHY is identified by the MAC connected to it */
if (intf == PHY_INTERFACE_MODE_SGMII) {
int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
+ port);
u8 slot;
if (lane < 0)
return;
slot = lane_to_slot[lane];
if (slot) {
/* Slot housing a SGMII riser card */
sprintf(phy, "phy_s%x_%02x", slot,
(fm_info_get_phy_address(port - FM1_DTSEC1)-
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
fdt_set_phy_handle(fdt, compat, addr, phy);
}
}
}
void fdt_fixup_board_enet(void *fdt)
{
int i, lane, idx;
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
switch (mdio_mux[i]) {
case EMI1_SLOT3:
fdt_status_okay_by_alias(fdt, "emi1_slot3");
break;
case EMI1_SLOT5:
fdt_status_okay_by_alias(fdt, "emi1_slot5");
break;
case EMI1_SLOT6:
fdt_status_okay_by_alias(fdt, "emi1_slot6");
break;
case EMI1_SLOT7:
fdt_status_okay_by_alias(fdt, "emi1_slot7");
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC4)
fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
if (i == FM1_DTSEC5)
fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
break;
default:
break;
}
}
}
#endif /* #ifdef CONFIG_FMAN_ENET */
static void set_brdcfg9_for_gtx_clk(void)
{
u8 brdcfg9;
brdcfg9 = QIXIS_READ(brdcfg[9]);
brdcfg9 |= (1 << 5);
QIXIS_WRITE(brdcfg[9], brdcfg9);
}
void t1040_handle_phy_interface_sgmii(int i)
{
int lane, idx, slot;
idx = i - FM1_DTSEC1;
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
return;
slot = lane_to_slot[lane];
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
case 3:
if (FM1_DTSEC4 == i)
fm_info_set_phy_address(i, riser_phy_addr[0]);
if (FM1_DTSEC5 == i)
fm_info_set_phy_address(i, riser_phy_addr[1]);
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
case 5:
/* Slot housing a SGMII riser card? */
fm_info_set_phy_address(i, riser_phy_addr[0]);
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
case 6:
/* Slot housing a SGMII riser card? */
fm_info_set_phy_address(i, riser_phy_addr[0]);
mdio_mux[i] = EMI1_SLOT6;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
case 7:
if (FM1_DTSEC1 == i)
fm_info_set_phy_address(i, riser_phy_addr[0]);
if (FM1_DTSEC2 == i)
fm_info_set_phy_address(i, riser_phy_addr[1]);
if (FM1_DTSEC3 == i)
fm_info_set_phy_address(i, riser_phy_addr[2]);
mdio_mux[i] = EMI1_SLOT7;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
}
void t1040_handle_phy_interface_rgmii(int i)
{
fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
EMI1_RGMII0;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
printf("Initializing Fman\n");
set_brdcfg9_for_gtx_clk();
initialize_lane_to_slot();
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
/*
* Program on board RGMII PHY addresses. If the SGMII Riser
* card used, we'll override the PHY address later. For any DTSEC that
* is RGMII, we'll also override its PHY address later. We assume that
* DTSEC4 and DTSEC5 are used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
break;
case PHY_INTERFACE_MODE_SGMII:
t1040_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_RGMII:
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
t1040_handle_phy_interface_rgmii(i);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}

1
board/freescale/t1040qds/t1040qds.c
View File

@ -223,6 +223,7 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob); fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif #endif
} }

1
board/freescale/t104xrdb/Makefile
View File

@ -7,6 +7,7 @@
obj-y += t104xrdb.o obj-y += t104xrdb.o
obj-y += ddr.o obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_PCI) += pci.o
obj-y += law.o obj-y += law.o
obj-y += tlb.o obj-y += tlb.o

6
board/freescale/t104xrdb/README
View File

@ -164,14 +164,14 @@ NOR Flash memory Map
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB 0xE8000000 0xE801FFFF RCW (current bank) 128KB

72
board/freescale/t104xrdb/eth.c Normal file
View File

@ -0,0 +1,72 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/immap_85xx.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <asm/fsl_dtsec.h>
#include "../common/fman.h"
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
int phy_addr = 0;
printf("Initializing Fman\n");
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
/*
* Program on board RGMII, SGMII PHY addresses.
*/
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
#ifdef CONFIG_T1040RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1040RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
#endif
case PHY_INTERFACE_MODE_RGMII:
if (FM1_DTSEC4 == i)
phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
if (FM1_DTSEC5 == i)
phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
fm_info_set_phy_address(i, phy_addr);
break;
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_phy_address(i, 0);
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
}
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}

2
board/keymile/kmp204x/Makefile
View File

@ -8,5 +8,5 @@
# SPDX-License-Identifier: GPL-2.0+ # SPDX-License-Identifier: GPL-2.0+
# #
obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \ obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o qrio.o \
../common/common.o ../common/ivm.o ../common/common.o ../common/ivm.o

128
board/keymile/kmp204x/kmp204x.c
View File

@ -33,12 +33,51 @@ int checkboard(void)
return 0; return 0;
} }
/* TODO: implement the I2C deblocking function */ /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
int i2c_make_abort(void) * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
* For I2C only the low state is activly driven and high state is pulled-up
* by a resistor. Therefore the deblock GPIOs are used
* -> as an active output to drive a low state
* -> as an open-drain input to have a pulled-up high state
*/
/* QRIO GPIOs used for deblocking */
#define DEBLOCK_PORT1 GPIO_A
#define DEBLOCK_SCL1 20
#define DEBLOCK_SDA1 21
/* By default deblock GPIOs are floating */
static void i2c_deblock_gpio_cfg(void)
{ {
return 1; /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
} }
void set_sda(int state)
{
qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
}
void set_scl(int state)
{
qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
}
int get_sda(void)
{
return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
}
int get_scl(void)
{
return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
}
#define ZL30158_RST 8 #define ZL30158_RST 8
#define ZL30343_RST 9 #define ZL30343_RST 9
@ -62,6 +101,7 @@ int board_early_init_f(void)
int board_early_init_r(void) int board_early_init_r(void)
{ {
int ret = 0;
/* Flush d-cache and invalidate i-cache of any FLASH data */ /* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache(); flush_dcache();
invalidate_icache(); invalidate_icache();
@ -69,7 +109,11 @@ int board_early_init_r(void)
set_liodns(); set_liodns();
setup_portals(); setup_portals();
return 0; ret = trigger_fpga_config();
if (ret)
printf("error triggering PCIe FPGA config\n");
return ret;
} }
unsigned long get_board_sys_clk(unsigned long dummy) unsigned long get_board_sys_clk(unsigned long dummy)
@ -77,80 +121,12 @@ unsigned long get_board_sys_clk(unsigned long dummy)
return 66666666; return 66666666;
} }
#define WDMASK_OFF 0x16 int misc_init_f(void)
static void qrio_wdmask(u8 bit, bool wden)
{ {
u16 wdmask; /* configure QRIO pis for i2c deblocking */
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; i2c_deblock_gpio_cfg();
wdmask = in_be16(qrio_base + WDMASK_OFF); return 0;
if (wden)
wdmask |= (1 << bit);
else
wdmask &= ~(1 << bit);
out_be16(qrio_base + WDMASK_OFF, wdmask);
}
#define PRST_OFF 0x1a
void qrio_prst(u8 bit, bool en, bool wden)
{
u16 prst;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
qrio_wdmask(bit, wden);
prst = in_be16(qrio_base + PRST_OFF);
if (en)
prst &= ~(1 << bit);
else
prst |= (1 << bit);
out_be16(qrio_base + PRST_OFF, prst);
}
#define PRSTCFG_OFF 0x1c
void qrio_prstcfg(u8 bit, u8 mode)
{
u32 prstcfg;
u8 i;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
for (i = 0; i < 2; i++) {
if (mode & (1<<i))
set_bit(2*bit+i, &prstcfg);
else
clear_bit(2*bit+i, &prstcfg);
}
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
}
#define BOOTCOUNT_OFF 0x12
void bootcount_store(ulong counter)
{
u8 val;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
val = (counter <= 255) ? (u8)counter : 255;
out_8(qrio_base + BOOTCOUNT_OFF, val);
}
ulong bootcount_load(void)
{
u8 val;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
val = in_8(qrio_base + BOOTCOUNT_OFF);
return val;
} }
#define NUM_SRDS_BANKS 2 #define NUM_SRDS_BANKS 2

10
board/keymile/kmp204x/kmp204x.h
View File

@ -5,6 +5,16 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
/* QRIO GPIO ports */
#define GPIO_A 0x40
#define GPIO_B 0x60
int qrio_get_gpio(u8 port_off, u8 gpio_nr);
void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val);
void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value);
void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value);
void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr);
#define PRSTCFG_POWUP_UNIT_CORE_RST 0x0 #define PRSTCFG_POWUP_UNIT_CORE_RST 0x0
#define PRSTCFG_POWUP_UNIT_RST 0x1 #define PRSTCFG_POWUP_UNIT_RST 0x1
#define PRSTCFG_POWUP_RST 0x3 #define PRSTCFG_POWUP_RST 0x3

10
board/keymile/kmp204x/pbi.cfg
View File

@ -8,6 +8,16 @@
# #
#PBI commands #PBI commands
#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
#Freescale's errarta sheet suggests it may be done with PBI
09000010 00000000
09000014 00000000
09000018 81d00000
09021008 0000f000
09021028 0000f000
09021048 0000f000
09021068 0000f000
09000018 00000000
#Initialize CPC1 as 1MB SRAM #Initialize CPC1 as 1MB SRAM
09010000 00200400 09010000 00200400
09138000 00000000 09138000 00000000

85
board/keymile/kmp204x/pci.c
View File

@ -14,18 +14,103 @@
#include <libfdt.h> #include <libfdt.h>
#include <fdt_support.h> #include <fdt_support.h>
#include <asm/fsl_serdes.h> #include <asm/fsl_serdes.h>
#include <asm/errno.h>
#include "kmp204x.h" #include "kmp204x.h"
#define PROM_SEL_L 11
/* control the PROM_SEL_L signal*/
static void toggle_fpga_eeprom_bus(bool cpu_own)
{
qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
}
#define CONF_SEL_L 10
#define FPGA_PROG_L 19
#define FPGA_DONE 18
#define FPGA_INIT_L 17
int trigger_fpga_config(void)
{
int ret = 0, init_l;
/* approx 10ms */
u32 timeout = 10000;
/* make sure the FPGA_can access the EEPROM */
toggle_fpga_eeprom_bus(false);
/* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
/* trigger the config start */
qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
/* small delay for INIT_L line */
udelay(10);
/* wait for FPGA_INIT to be asserted */
do {
init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
if (timeout-- == 0) {
printf("FPGA_INIT timeout\n");
ret = -EFAULT;
break;
}
udelay(10);
} while (init_l);
/* deassert FPGA_PROG, config should start */
qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
return ret;
}
/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
static int wait_for_fpga_config(void)
{
int ret = 0, done;
/* approx 5 s */
u32 timeout = 500000;
printf("PCIe FPGA config:");
do {
done = qrio_get_gpio(GPIO_A, FPGA_DONE);
if (timeout-- == 0) {
printf(" FPGA_DONE timeout\n");
ret = -EFAULT;
goto err_out;
}
udelay(10);
} while (!done);
printf(" done\n");
err_out:
/* deactive CONF_SEL and give the CPU conf EEPROM access */
qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
toggle_fpga_eeprom_bus(true);
return ret;
}
#define PCIE_SW_RST 14 #define PCIE_SW_RST 14
#define PEXHC_SW_RST 13
#define HOOPER_SW_RST 12 #define HOOPER_SW_RST 12
void pci_init_board(void) void pci_init_board(void)
{ {
/* first wait for the PCIe FPGA to be configured
* it has been triggered earlier in board_early_init_r */
int ret = wait_for_fpga_config();
if (ret)
printf("error finishing PCIe FPGA config\n");
qrio_prst(PCIE_SW_RST, false, false); qrio_prst(PCIE_SW_RST, false, false);
qrio_prst(PEXHC_SW_RST, false, false);
qrio_prst(HOOPER_SW_RST, false, false); qrio_prst(HOOPER_SW_RST, false, false);
/* Hooper is not direcly PCIe capable */ /* Hooper is not direcly PCIe capable */
mdelay(50); mdelay(50);
fsl_pcie_init_board(0); fsl_pcie_init_board(0);
} }

146
board/keymile/kmp204x/qrio.c Normal file
View File

@ -0,0 +1,146 @@
/*
* (C) Copyright 2013 Keymile AG
* Valentin Longchamp <valentin.longchamp@keymile.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include "../common/common.h"
#include "kmp204x.h"
/* QRIO GPIO register offsets */
#define DIRECT_OFF 0x18
#define GPRT_OFF 0x1c
int qrio_get_gpio(u8 port_off, u8 gpio_nr)
{
u32 gprt;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
gprt = in_be32(qrio_base + port_off + GPRT_OFF);
return (gprt >> gpio_nr) & 1U;
}
void qrio_set_gpio(u8 port_off, u8 gpio_nr, bool value)
{
u32 gprt, mask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
gprt = in_be32(qrio_base + port_off + GPRT_OFF);
if (value)
gprt |= mask;
else
gprt &= ~mask;
out_be32(qrio_base + port_off + GPRT_OFF, gprt);
}
void qrio_gpio_direction_output(u8 port_off, u8 gpio_nr, bool value)
{
u32 direct, mask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
direct = in_be32(qrio_base + port_off + DIRECT_OFF);
direct |= mask;
out_be32(qrio_base + port_off + DIRECT_OFF, direct);
qrio_set_gpio(port_off, gpio_nr, value);
}
void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr)
{
u32 direct, mask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
direct = in_be32(qrio_base + port_off + DIRECT_OFF);
direct &= ~mask;
out_be32(qrio_base + port_off + DIRECT_OFF, direct);
}
void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
{
u32 direct, mask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
mask = 1U << gpio_nr;
direct = in_be32(qrio_base + port_off + DIRECT_OFF);
if (val == 0)
/* set to output -> GPIO drives low */
direct |= mask;
else
/* set to input -> GPIO floating */
direct &= ~mask;
out_be32(qrio_base + port_off + DIRECT_OFF, direct);
}
#define WDMASK_OFF 0x16
static void qrio_wdmask(u8 bit, bool wden)
{
u16 wdmask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
wdmask = in_be16(qrio_base + WDMASK_OFF);
if (wden)
wdmask |= (1 << bit);
else
wdmask &= ~(1 << bit);
out_be16(qrio_base + WDMASK_OFF, wdmask);
}
#define PRST_OFF 0x1a
void qrio_prst(u8 bit, bool en, bool wden)
{
u16 prst;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
qrio_wdmask(bit, wden);
prst = in_be16(qrio_base + PRST_OFF);
if (en)
prst &= ~(1 << bit);
else
prst |= (1 << bit);
out_be16(qrio_base + PRST_OFF, prst);
}
#define PRSTCFG_OFF 0x1c
void qrio_prstcfg(u8 bit, u8 mode)
{
u32 prstcfg;
u8 i;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
prstcfg = in_be32(qrio_base + PRSTCFG_OFF);
for (i = 0; i < 2; i++) {
if (mode & (1<<i))
set_bit(2*bit+i, &prstcfg);
else
clear_bit(2*bit+i, &prstcfg);
}
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
}

2
board/keymile/kmp204x/rcw_kmp204x.cfg
View File

@ -7,5 +7,5 @@ aa55aa55 010e0100
#64 bytes RCW data #64 bytes RCW data
14600000 00000000 28200000 00000000 14600000 00000000 28200000 00000000
148E70CF CFC02000 58000000 41000000 148E70CF CFC02000 58000000 41000000
00000000 00000000 00000000 F4428002 00000000 00000000 00000000 F0428002
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

1
boards.cfg
View File

@ -990,6 +990,7 @@ Active powerpc mpc85xx - gdsys p1022
Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com> Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com> Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek <dan@embeddedalley.com> Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek <dan@embeddedalley.com>

4
doc/README.b4860qds
View File

@ -230,14 +230,14 @@ NOR Flash memory Map on B4860 and B4420QDS
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB 0xEF300000 0xEFEFFFFF rootfs (alternate bank) 12MB
0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB 0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB
0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB 0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB
0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB 0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB
0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB 0xEDF40000 0xEDFFFFFF u-boot (alternate bank) 768KB
0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB 0xEDF20000 0xEDF3FFFF u-boot env (alternate bank) 128KB
0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB 0xEDF00000 0xEDF1FFFF FMAN ucode (alternate bank) 128KB
0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB 0xED300000 0xEDEFFFFF rootfs (current bank) 12MB
0xEC800000 0xEC8FFFFF device tree (current bank) 1MB 0xEC800000 0xEC8FFFFF device tree (current bank) 1MB
0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB 0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB
0xEC000000 0xEC01FFFF RCW (current bank) 128KB 0xEC000000 0xEC01FFFF RCW (current bank) 128KB

241
drivers/mtd/nand/fsl_ifc_nand.c
View File

@ -230,8 +230,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
ctrl->page = page_addr; ctrl->page = page_addr;
/* Program ROW0/COL0 */ /* Program ROW0/COL0 */
out_be32(&ifc->ifc_nand.row0, page_addr); ifc_out32(&ifc->ifc_nand.row0, page_addr);
out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
buf_num = page_addr & priv->bufnum_mask; buf_num = page_addr & priv->bufnum_mask;
@ -294,23 +294,23 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
int i; int i;
/* set the chip select for NAND Transaction */ /* set the chip select for NAND Transaction */
out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
/* start read/write seq */ /* start read/write seq */
out_be32(&ifc->ifc_nand.nandseq_strt, ifc_out32(&ifc->ifc_nand.nandseq_strt,
IFC_NAND_SEQ_STRT_FIR_STRT); IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for NAND Machine complete flag or timeout */ /* wait for NAND Machine complete flag or timeout */
end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
while (end_tick > get_ticks()) { while (end_tick > get_ticks()) {
ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
break; break;
} }
out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
printf("%s: Flash Time Out Error\n", __func__); printf("%s: Flash Time Out Error\n", __func__);
@ -324,7 +324,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
int sector_end = sector + chip->ecc.steps - 1; int sector_end = sector + chip->ecc.steps - 1;
for (i = sector / 4; i <= sector_end / 4; i++) for (i = sector / 4; i <= sector_end / 4; i++)
eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
for (i = sector; i <= sector_end; i++) { for (i = sector; i <= sector_end; i++) {
errors = check_read_ecc(mtd, ctrl, eccstat, i); errors = check_read_ecc(mtd, ctrl, eccstat, i);
@ -364,30 +364,30 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
/* Program FIR/IFC_NAND_FCR0 for Small/Large page */ /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
if (mtd->writesize > 512) { if (mtd->writesize > 512) {
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir1, 0x0); ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
} else { } else {
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
if (oob) if (oob)
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
else else
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
} }
} }
@ -408,7 +408,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
switch (command) { switch (command) {
/* READ0 read the entire buffer to use hardware ECC. */ /* READ0 read the entire buffer to use hardware ECC. */
case NAND_CMD_READ0: { case NAND_CMD_READ0: {
out_be32(&ifc->ifc_nand.nand_fbcr, 0); ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
set_addr(mtd, 0, page_addr, 0); set_addr(mtd, 0, page_addr, 0);
ctrl->read_bytes = mtd->writesize + mtd->oobsize; ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@ -424,7 +424,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
/* READOOB reads only the OOB because no ECC is performed. */ /* READOOB reads only the OOB because no ECC is performed. */
case NAND_CMD_READOOB: case NAND_CMD_READOOB:
out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
set_addr(mtd, column, page_addr, 1); set_addr(mtd, column, page_addr, 1);
ctrl->read_bytes = mtd->writesize + mtd->oobsize; ctrl->read_bytes = mtd->writesize + mtd->oobsize;
@ -441,19 +441,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
if (command == NAND_CMD_PARAM) if (command == NAND_CMD_PARAM)
timing = IFC_FIR_OP_RBCD; timing = IFC_FIR_OP_RBCD;
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(timing << IFC_NAND_FIR0_OP2_SHIFT)); (timing << IFC_NAND_FIR0_OP2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
command << IFC_NAND_FCR0_CMD0_SHIFT); command << IFC_NAND_FCR0_CMD0_SHIFT);
out_be32(&ifc->ifc_nand.row3, column); ifc_out32(&ifc->ifc_nand.row3, column);
/* /*
* although currently it's 8 bytes for READID, we always read * although currently it's 8 bytes for READID, we always read
* the maximum 256 bytes(for PARAM) * the maximum 256 bytes(for PARAM)
*/ */
out_be32(&ifc->ifc_nand.nand_fbcr, 256); ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
ctrl->read_bytes = 256; ctrl->read_bytes = 256;
set_addr(mtd, 0, 0, 0); set_addr(mtd, 0, 0, 0);
@ -468,16 +468,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
/* ERASE2 uses the block and page address from ERASE1 */ /* ERASE2 uses the block and page address from ERASE1 */
case NAND_CMD_ERASE2: case NAND_CMD_ERASE2:
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
(NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
out_be32(&ifc->ifc_nand.nand_fbcr, 0); ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
ctrl->read_bytes = 0; ctrl->read_bytes = 0;
fsl_ifc_run_command(mtd); fsl_ifc_run_command(mtd);
return; return;
@ -494,17 +494,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_WBCD <<
(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); IFC_NAND_FIR0_OP3_SHIFT) |
out_be32(&ifc->ifc_nand.nand_fir1, (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | ifc_out32(&ifc->ifc_nand.nand_fir1,
(IFC_FIR_OP_RDSTAT << (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
(IFC_FIR_OP_RDSTAT <<
IFC_NAND_FIR1_OP6_SHIFT) | IFC_NAND_FIR1_OP6_SHIFT) |
(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
} else { } else {
nand_fcr0 = ((NAND_CMD_PAGEPROG << nand_fcr0 = ((NAND_CMD_PAGEPROG <<
IFC_NAND_FCR0_CMD1_SHIFT) | IFC_NAND_FCR0_CMD1_SHIFT) |
@ -513,18 +514,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
(NAND_CMD_STATUS << (NAND_CMD_STATUS <<
IFC_NAND_FCR0_CMD3_SHIFT)); IFC_NAND_FCR0_CMD3_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir1, ifc_out32(&ifc->ifc_nand.nand_fir1,
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
(IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
(IFC_FIR_OP_RDSTAT << (IFC_FIR_OP_RDSTAT <<
IFC_NAND_FIR1_OP7_SHIFT) | IFC_NAND_FIR1_OP7_SHIFT) |
(IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
if (column >= mtd->writesize) if (column >= mtd->writesize)
nand_fcr0 |= nand_fcr0 |=
@ -539,7 +540,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
column -= mtd->writesize; column -= mtd->writesize;
ctrl->oob = 1; ctrl->oob = 1;
} }
out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
set_addr(mtd, column, page_addr, ctrl->oob); set_addr(mtd, column, page_addr, ctrl->oob);
return; return;
} }
@ -547,21 +548,21 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
/* PAGEPROG reuses all of the setup from SEQIN and adds the length */ /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
case NAND_CMD_PAGEPROG: case NAND_CMD_PAGEPROG:
if (ctrl->oob) if (ctrl->oob)
out_be32(&ifc->ifc_nand.nand_fbcr, ifc_out32(&ifc->ifc_nand.nand_fbcr,
ctrl->index - ctrl->column); ctrl->index - ctrl->column);
else else
out_be32(&ifc->ifc_nand.nand_fbcr, 0); ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
fsl_ifc_run_command(mtd); fsl_ifc_run_command(mtd);
return; return;
case NAND_CMD_STATUS: case NAND_CMD_STATUS:
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
out_be32(&ifc->ifc_nand.nand_fbcr, 1); ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
set_addr(mtd, 0, 0, 0); set_addr(mtd, 0, 0, 0);
ctrl->read_bytes = 1; ctrl->read_bytes = 1;
@ -572,10 +573,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
return; return;
case NAND_CMD_RESET: case NAND_CMD_RESET:
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
fsl_ifc_run_command(mtd); fsl_ifc_run_command(mtd);
return; return;
@ -647,8 +648,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
* next byte. * next byte.
*/ */
if (ctrl->index < ctrl->read_bytes) { if (ctrl->index < ctrl->read_bytes) {
data = in_be16((uint16_t *)&ctrl-> data = ifc_in16((uint16_t *)&ctrl->
addr[ctrl->index]); addr[ctrl->index]);
ctrl->index += 2; ctrl->index += 2;
return (uint8_t)data; return (uint8_t)data;
} }
@ -727,12 +728,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
return NAND_STATUS_FAIL; return NAND_STATUS_FAIL;
/* Use READ_STATUS command, but wait for the device to be ready */ /* Use READ_STATUS command, but wait for the device to be ready */
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
IFC_NAND_FCR0_CMD0_SHIFT); IFC_NAND_FCR0_CMD0_SHIFT);
out_be32(&ifc->ifc_nand.nand_fbcr, 1); ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
set_addr(mtd, 0, 0, 0); set_addr(mtd, 0, 0, 0);
ctrl->read_bytes = 1; ctrl->read_bytes = 1;
@ -741,7 +742,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
return NAND_STATUS_FAIL; return NAND_STATUS_FAIL;
nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
/* Chip sometimes reporting write protect even when it's not */ /* Chip sometimes reporting write protect even when it's not */
nand_fsr = nand_fsr | NAND_STATUS_WP; nand_fsr = nand_fsr | NAND_STATUS_WP;
@ -784,17 +785,17 @@ static void fsl_ifc_ctrl_init(void)
ifc_ctrl->regs = IFC_BASE_ADDR; ifc_ctrl->regs = IFC_BASE_ADDR;
/* clear event registers */ /* clear event registers */
out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
/* Enable error and event for any detected errors */ /* Enable error and event for any detected errors */
out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
IFC_NAND_EVTER_EN_OPC_EN | IFC_NAND_EVTER_EN_OPC_EN |
IFC_NAND_EVTER_EN_PGRDCMPL_EN | IFC_NAND_EVTER_EN_PGRDCMPL_EN |
IFC_NAND_EVTER_EN_FTOER_EN | IFC_NAND_EVTER_EN_FTOER_EN |
IFC_NAND_EVTER_EN_WPER_EN); IFC_NAND_EVTER_EN_WPER_EN);
out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
} }
static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
@ -810,50 +811,50 @@ static void fsl_ifc_sram_init(void)
cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
/* Save CSOR and CSOR_ext */ /* Save CSOR and CSOR_ext */
csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor);
csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
/* chage PageSize 8K and SpareSize 1K*/ /* chage PageSize 8K and SpareSize 1K*/
csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
/* READID */ /* READID */
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
out_be32(&ifc->ifc_nand.row3, 0x0); ifc_out32(&ifc->ifc_nand.row3, 0x0);
out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
/* Program ROW0/COL0 */ /* Program ROW0/COL0 */
out_be32(&ifc->ifc_nand.row0, 0x0); ifc_out32(&ifc->ifc_nand.row0, 0x0);
out_be32(&ifc->ifc_nand.col0, 0x0); ifc_out32(&ifc->ifc_nand.col0, 0x0);
/* set the chip select for NAND Transaction */ /* set the chip select for NAND Transaction */
out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
/* start read seq */ /* start read seq */
out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for NAND Machine complete flag or timeout */ /* wait for NAND Machine complete flag or timeout */
end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
while (end_tick > get_ticks()) { while (end_tick > get_ticks()) {
ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
break; break;
} }
out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
/* Restore CSOR and CSOR_ext */ /* Restore CSOR and CSOR_ext */
out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
} }
static int fsl_ifc_chip_init(int devnum, u8 *addr) static int fsl_ifc_chip_init(int devnum, u8 *addr)
@ -883,8 +884,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
phys_addr_t phys_addr = virt_to_phys(addr); phys_addr_t phys_addr = virt_to_phys(addr);
cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
(cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
@ -1004,7 +1005,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr)
nand->ecc.mode = NAND_ECC_SOFT; nand->ecc.mode = NAND_ECC_SOFT;
} }
ver = in_be32(&ifc_ctrl->regs->ifc_rev); ver = ifc_in32(&ifc_ctrl->regs->ifc_rev);
if (ver == FSL_IFC_V1_1_0) if (ver == FSL_IFC_V1_1_0)
fsl_ifc_sram_init(); fsl_ifc_sram_init();

56
drivers/mtd/nand/fsl_ifc_spl.c
View File

@ -60,7 +60,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size)
bufnum_end = bufnum + bufperpage - 1; bufnum_end = bufnum + bufperpage - 1;
do { do {
status = in_be32(&ifc->ifc_nand.nand_evter_stat); status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
} while (!(status & IFC_NAND_EVTER_STAT_OPC)); } while (!(status & IFC_NAND_EVTER_STAT_OPC));
if (status & IFC_NAND_EVTER_STAT_FTOER) { if (status & IFC_NAND_EVTER_STAT_FTOER) {
@ -70,14 +70,14 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size)
} }
for (i = bufnum / 4; i <= bufnum_end / 4; i++) for (i = bufnum / 4; i <= bufnum_end / 4; i++)
eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
for (i = bufnum; i <= bufnum_end; i++) { for (i = bufnum; i <= bufnum_end; i++) {
if (check_read_ecc(buf, eccstat, i, page_size)) if (check_read_ecc(buf, eccstat, i, page_size))
break; break;
} }
out_be32(&ifc->ifc_nand.nand_evter_stat, status); ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
} }
static inline int bad_block(uchar *marker, int port_size) static inline int bad_block(uchar *marker, int port_size)
@ -140,38 +140,38 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
blk_size = pages_per_blk * page_size; blk_size = pages_per_blk * page_size;
/* Open Full SRAM mapping for spare are access */ /* Open Full SRAM mapping for spare are access */
out_be32(&ifc->ifc_nand.ncfgr, 0x0); ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
/* Clear Boot events */ /* Clear Boot events */
out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
/* Program FIR/FCR for Large/Small page */ /* Program FIR/FCR for Large/Small page */
if (page_size > 512) { if (page_size > 512) {
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir1, 0x0); ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
} else { } else {
out_be32(&ifc->ifc_nand.nand_fir0, ifc_out32(&ifc->ifc_nand.nand_fir0,
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
out_be32(&ifc->ifc_nand.nand_fir1, 0x0); ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
out_be32(&ifc->ifc_nand.nand_fcr0, ifc_out32(&ifc->ifc_nand.nand_fcr0,
NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
} }
/* Program FBCR = 0 for full page read */ /* Program FBCR = 0 for full page read */
out_be32(&ifc->ifc_nand.nand_fbcr, 0); ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
/* Read and copy u-boot on SDRAM from NAND device, In parallel /* Read and copy u-boot on SDRAM from NAND device, In parallel
* check for Bad block if found skip it and read continue to * check for Bad block if found skip it and read continue to
@ -184,11 +184,11 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst)
bufnum = pg_no & bufnum_mask; bufnum = pg_no & bufnum_mask;
sram_addr = bufnum * page_size * 2; sram_addr = bufnum * page_size * 2;
out_be32(&ifc->ifc_nand.row0, pg_no); ifc_out32(&ifc->ifc_nand.row0, pg_no);
out_be32(&ifc->ifc_nand.col0, 0); ifc_out32(&ifc->ifc_nand.col0, 0);
/* start read */ /* start read */
out_be32(&ifc->ifc_nand.nandseq_strt, ifc_out32(&ifc->ifc_nand.nandseq_strt,
IFC_NAND_SEQ_STRT_FIR_STRT); IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for read to complete */ /* wait for read to complete */
nand_wait(&buf[sram_addr], bufnum, page_size); nand_wait(&buf[sram_addr], bufnum, page_size);

56
drivers/net/fm/t1040.c
View File

@ -12,5 +12,61 @@
phy_interface_t fman_port_enet_if(enum fm_port port) phy_interface_t fman_port_enet_if(enum fm_port port)
{ {
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
/* handle RGMII first */
if ((port == FM1_DTSEC2) &&
((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) {
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
return PHY_INTERFACE_MODE_RGMII;
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
else
return PHY_INTERFACE_MODE_NONE;
}
if ((port == FM1_DTSEC4) &&
((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) ==
FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) {
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII)
return PHY_INTERFACE_MODE_RGMII;
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
else
return PHY_INTERFACE_MODE_NONE;
}
if (port == FM1_DTSEC5) {
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
return PHY_INTERFACE_MODE_RGMII;
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
return PHY_INTERFACE_MODE_MII;
else
return PHY_INTERFACE_MODE_NONE;
}
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_QSGMII;
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE; return PHY_INTERFACE_MODE_NONE;
} }

4
drivers/pci/fsl_pci_init.c
View File

@ -510,8 +510,8 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
/* Print the negotiated PCIe link width */ /* Print the negotiated PCIe link width */
pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
pci_info->regs); (temp16 & 0xf), pci_info->regs);
hose->current_busno++; /* Start scan with secondary */ hose->current_busno++; /* Start scan with secondary */
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);

5
include/configs/T1040QDS.h
View File

@ -611,9 +611,8 @@ unsigned long get_board_ddr_clk(void);
#endif #endif
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d

24
include/configs/T1040RDB.h
View File

@ -79,10 +79,6 @@
#if defined(CONFIG_SPIFLASH) #if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SECT_SIZE 0x10000
@ -202,6 +198,7 @@
/* CPLD on IFC */ /* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \ | CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \ | CSPR_MSEL_GPCM \
@ -386,6 +383,10 @@
#define CONFIG_CMD_SF #define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0 #define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
/* /*
* General PCI * General PCI
@ -543,13 +544,12 @@
#endif #endif
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
#define CONFIG_MII /* MII PHY management */ #define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC1" #define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif #endif
@ -627,9 +627,9 @@
#define __USB_PHY_TYPE utmi #define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \ "netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \

20
include/configs/T1042RDB_PI.h
View File

@ -79,10 +79,6 @@
#if defined(CONFIG_SPIFLASH) #if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SECT_SIZE 0x10000
@ -202,6 +198,7 @@
/* CPLD on IFC */ /* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \ | CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \ | CSPR_MSEL_GPCM \
@ -394,6 +391,10 @@
#define CONFIG_CMD_SF #define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000 #define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0 #define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
/* /*
* General PCI * General PCI
@ -551,8 +552,11 @@
#endif #endif
#ifdef CONFIG_FMAN_ENET #ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#define CONFIG_MII /* MII PHY management */ #define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC1" #define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif #endif
@ -631,9 +635,9 @@
#define __USB_PHY_TYPE utmi #define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \ "netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \

10
include/configs/km/keymile-common.h
View File

@ -99,11 +99,16 @@
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
#define CONFIG_KM_UBI_PART_BOOT_OPTS ""
#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
/* one flash chip only called boot */ /* one flash chip only called boot */
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
# define CONFIG_KM_UBI_LINUX_MTD \ # define CONFIG_KM_UBI_LINUX_MTD \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \
CONFIG_KM_UBI_PART_BOOT_OPTS
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
@ -111,7 +116,8 @@
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ /* app: CONFIG_KM_UBI_PARTITION_NAME_APP */
# define CONFIG_KM_UBI_LINUX_MTD \ # define CONFIG_KM_UBI_LINUX_MTD \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \
CONFIG_KM_UBI_PART_BOOT_OPTS " " \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
"ubiattach=if test ${boot_bank} -eq 0; then; " \ "ubiattach=if test ${boot_bank} -eq 0; then; " \

21
include/configs/km/kmp204x-common.h
View File

@ -15,6 +15,10 @@
#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
/* an additionnal option is required for UBI as subpage access is
* supported in u-boot */
#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
#define CONFIG_NAND_ECC_BCH #define CONFIG_NAND_ECC_BCH
/* common KM defines */ /* common KM defines */
@ -148,8 +152,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
#define CONFIG_BOOTCOUNT_LIMIT
/* /*
* Local Bus Definitions * Local Bus Definitions
*/ */
@ -206,8 +208,13 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
/* bootcounter in QRIO */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R #define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT #define CONFIG_LAST_STAGE_INIT
@ -263,7 +270,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */ /* I2C */
#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
#define CONFIG_SYS_NUM_I2C_BUSES 3 #define CONFIG_SYS_NUM_I2C_BUSES 3
#define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
@ -276,6 +286,12 @@ unsigned long get_board_sys_clk(unsigned long dummy);
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
} }
#ifndef __ASSEMBLY__
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
#endif
#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ #define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
@ -286,6 +302,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */ #define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
#define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF #define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 20000000 #define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE 0 #define CONFIG_SF_DEFAULT_MODE 0

7
include/configs/kmp204x.h
View File

@ -13,6 +13,11 @@
#define CONFIG_HOSTNAME kmlion1 #define CONFIG_HOSTNAME kmlion1
#define CONFIG_KM_BOARD_NAME "kmlion1" #define CONFIG_KM_BOARD_NAME "kmlion1"
/* KMCOGE4 */
#elif defined(CONFIG_KMCOGE4)
#define CONFIG_HOSTNAME kmcoge4
#define CONFIG_KM_BOARD_NAME "kmcoge4"
#else #else
#error ("Board not supported") #error ("Board not supported")
#endif #endif
@ -42,6 +47,7 @@
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM
/* Local bus app1 Options */ /* Local bus app1 Options */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM
#endif
/* App2 Local bus */ /* App2 Local bus */
#define CONFIG_SYS_LBAPP2_BASE 0xE0000000 #define CONFIG_SYS_LBAPP2_BASE 0xE0000000
@ -63,6 +69,5 @@
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
/* Local bus app2 Options */ /* Local bus app2 Options */
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
#endif
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

40
include/fsl_ifc.h
View File

@ -12,6 +12,20 @@
#include <config.h> #include <config.h>
#include <common.h> #include <common.h>
#ifdef CONFIG_SYS_FSL_IFC_LE
#define ifc_in32(a) in_le32(a)
#define ifc_out32(a, v) out_le32(a, v)
#define ifc_in16(a) in_le16(a)
#elif defined(CONFIG_SYS_FSL_IFC_BE)
#define ifc_in32(a) in_be32(a)
#define ifc_out32(a, v) out_be32(a, v)
#define ifc_in16(a) in_be16(a)
#else
#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined
#endif
/* /*
* CSPR - Chip Select Property Register * CSPR - Chip Select Property Register
*/ */
@ -773,20 +787,22 @@ extern void init_early_memctl_regs(void);
#define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR)
#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) #define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext))
#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) #define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr))
#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) #define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext))
#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) #define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor))
#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) #define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask))
#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) #define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j]))
#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) #define set_ifc_cspr_ext(i, v) \
#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v))
#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) #define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v))
#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) #define set_ifc_csor_ext(i, v) \
#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v))
#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v))
#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v))
#define set_ifc_ftim(i, j, v) \ #define set_ifc_ftim(i, j, v) \
(out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v))
enum ifc_chip_sel { enum ifc_chip_sel {
IFC_CS0, IFC_CS0,