arm: rmobile: Add HopeRun HiHope RZ/G2M board support
The HiHope RZ/G2M board from HopeRun consists of main board (HopeRun HiHope RZ/G2M main board) and sub board(HopeRun HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits below the HiHope RZ/G2M main board. This patch adds the required board support to boot HopeRun HiHope RZ/G2M board. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
This commit is contained in:
Biju Das
Marek Vasut
parent
40ac794524
commit
b650c83825
@ -822,6 +822,7 @@ dtb-$(CONFIG_RCAR_GEN3) += \
|
||||
r8a774a1-beacon-rzg2m-kit.dtb \
|
||||
r8a774b1-beacon-rzg2n-kit.dtb \
|
||||
r8a774e1-beacon-rzg2h-kit.dtb \
|
||||
r8a774a1-hihope-rzg2m-u-boot.dtb \
|
||||
r8a77950-ulcb-u-boot.dtb \
|
||||
r8a77950-salvator-x-u-boot.dtb \
|
||||
r8a77960-ulcb-u-boot.dtb \
|
||||
|
||||
@ -4,6 +4,8 @@ menu "Select Target SoC"
|
||||
|
||||
config R8A774A1
|
||||
bool "Renesas SoC R8A774A1"
|
||||
imply CLK_R8A774A1
|
||||
imply PINCTRL_PFC_R8A774A1
|
||||
|
||||
config R8A774B1
|
||||
bool "Renesas SoC R8A774B1"
|
||||
@ -99,6 +101,15 @@ config TARGET_EBISU
|
||||
help
|
||||
Support for Renesas R-Car Gen3 Ebisu platform
|
||||
|
||||
config TARGET_HIHOPE_RZG2
|
||||
bool "HiHope RZ/G2 board"
|
||||
imply R8A774A1
|
||||
imply SYS_MALLOC_F
|
||||
imply MULTI_DTB_FIT
|
||||
imply MULTI_DTB_FIT_USER_DEFINED_AREA
|
||||
help
|
||||
Support for RZG2 HiHope platform
|
||||
|
||||
config TARGET_SALVATOR_X
|
||||
bool "Salvator-X board"
|
||||
imply R8A7795
|
||||
@ -133,12 +144,15 @@ source "board/renesas/ebisu/Kconfig"
|
||||
source "board/renesas/salvator-x/Kconfig"
|
||||
source "board/renesas/ulcb/Kconfig"
|
||||
source "board/beacon/beacon-rzg2m/Kconfig"
|
||||
source "board/hoperun/hihope-rzg2/Kconfig"
|
||||
|
||||
config MULTI_DTB_FIT_UNCOMPRESS_SZ
|
||||
default 0x80000 if TARGET_HIHOPE_RZG2
|
||||
default 0x80000 if TARGET_SALVATOR_X
|
||||
default 0x80000 if TARGET_ULCB
|
||||
|
||||
config MULTI_DTB_FIT_USER_DEF_ADDR
|
||||
default 0x49000000 if TARGET_HIHOPE_RZG2
|
||||
default 0x49000000 if TARGET_SALVATOR_X
|
||||
default 0x49000000 if TARGET_ULCB
|
||||
|
||||
|
||||
15
board/hoperun/hihope-rzg2/Kconfig
Normal file
15
board/hoperun/hihope-rzg2/Kconfig
Normal file
@ -0,0 +1,15 @@
|
||||
if TARGET_HIHOPE_RZG2
|
||||
|
||||
config SYS_SOC
|
||||
default "rmobile"
|
||||
|
||||
config SYS_BOARD
|
||||
default "hihope-rzg2"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "hoperun"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "hihope-rzg2"
|
||||
|
||||
endif
|
||||
6
board/hoperun/hihope-rzg2/MAINTAINERS
Normal file
6
board/hoperun/hihope-rzg2/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
|
||||
HIHOPE_RZG2 BOARD
|
||||
M: Biju Das <biju.das.jz@bp.renesas.com>
|
||||
S: Maintained
|
||||
F: board/hoperun/hihope-rzg2/
|
||||
F: include/configs/hihope-rzg2.h
|
||||
F: configs/hihope_rzg2_defconfig
|
||||
9
board/hoperun/hihope-rzg2/Makefile
Normal file
9
board/hoperun/hihope-rzg2/Makefile
Normal file
@ -0,0 +1,9 @@
|
||||
#
|
||||
# board/hoperun/hihope-rzg2/Makefile
|
||||
#
|
||||
# Copyright (C) 2021 Renesas Electronics Corporation
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := hihope-rzg2.o ../../renesas/rcar-common/common.o
|
||||
105
board/hoperun/hihope-rzg2/hihope-rzg2.c
Normal file
105
board/hoperun/hihope-rzg2/hihope-rzg2.c
Normal file
@ -0,0 +1,105 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* board/hoperun/hihope-rzg2/hihope-rzg2.c
|
||||
* This file is HiHope RZ/G2M board support.
|
||||
*
|
||||
* Copyright (C) 2021 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/arch/rmobile.h>
|
||||
#include <asm/arch/rcar-mstp.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
#define RST_BASE 0xE6160000
|
||||
#define RST_CA57RESCNT (RST_BASE + 0x40)
|
||||
#define RST_CA53RESCNT (RST_BASE + 0x44)
|
||||
#define RST_CA57_CODE 0xA5A5000F
|
||||
#define RST_CA53_CODE 0x5A5A000F
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#define HSUSB_MSTP704 BIT(4) /* HSUSB */
|
||||
|
||||
/* HSUSB block registers */
|
||||
#define HSUSB_REG_LPSTS 0xE6590102
|
||||
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
|
||||
#define HSUSB_REG_UGCTRL2 0xE6590184
|
||||
#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10
|
||||
#define HSUSB_REG_UGCTRL2_RESERVED_3 0x1 /* bit[3:0] should be B'0001 */
|
||||
|
||||
#define PRR_REGISTER (0xFFF00044)
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
|
||||
|
||||
/* Configure the HSUSB block */
|
||||
mstp_clrbits_le32(SMSTPCR7, SMSTPCR7, HSUSB_MSTP704);
|
||||
/*
|
||||
* We need to add a barrier instruction after HSUSB module stop release.
|
||||
* This barrier instruction can be either reading back the same MSTP
|
||||
* register or any other register in the same IP block. So like linux
|
||||
* adding check for MSTPSR register, which indicates the clock has been
|
||||
* started.
|
||||
*/
|
||||
for (i = 1000; i > 0; --i) {
|
||||
if (!(readl(MSTPSR7) & HSUSB_MSTP704))
|
||||
break;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
/* Select EHCI/OHCI host module for USB2.0 ch0 */
|
||||
writel(HSUSB_REG_UGCTRL2_USB0SEL_EHCI | HSUSB_REG_UGCTRL2_RESERVED_3,
|
||||
HSUSB_REG_UGCTRL2);
|
||||
/* low power status */
|
||||
setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
unsigned long midr, cputype;
|
||||
|
||||
asm volatile("mrs %0, midr_el1" : "=r" (midr));
|
||||
cputype = (midr >> 4) & 0xfff;
|
||||
|
||||
if (cputype == 0xd03)
|
||||
writel(RST_CA53_CODE, RST_CA53RESCNT);
|
||||
else
|
||||
writel(RST_CA57_CODE, RST_CA57RESCNT);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MULTI_DTB_FIT)
|
||||
/* If the firmware passed a device tree, use it for board identification. */
|
||||
extern u64 rcar_atf_boot_args[];
|
||||
|
||||
static bool is_hoperun_hihope_rzg2_board(const char *board_name)
|
||||
{
|
||||
void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
|
||||
bool ret = false;
|
||||
|
||||
if ((fdt_magic(atf_fdt_blob) == FDT_MAGIC) &&
|
||||
(fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0))
|
||||
ret = true;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int board_fit_config_name_match(const char *name)
|
||||
{
|
||||
if (is_hoperun_hihope_rzg2_board("hoperun,hihope-rzg2m") &&
|
||||
!strcmp(name, "r8a774a1-hihope-rzg2m-u-boot"))
|
||||
return 0;
|
||||
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
82
configs/hihope_rzg2_defconfig
Normal file
82
configs/hihope_rzg2_defconfig
Normal file
@ -0,0 +1,82 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_ARCH_RMOBILE=y
|
||||
CONFIG_SYS_TEXT_BASE=0x50000000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0xFFFE0000
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_HIHOPE_RZG2=y
|
||||
# CONFIG_SPL is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-hihope-rzg2m-u-boot"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
|
||||
CONFIG_DEFAULT_FDT_FILE="r8a774a1-hihope-rzg2m.dtb"
|
||||
# CONFIG_BOARD_EARLY_INIT_F is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_OF_LIST="r8a774a1-hihope-rzg2m-u-boot"
|
||||
CONFIG_MULTI_DTB_FIT_LZO=y
|
||||
CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_MMC_ENV_DEV=1
|
||||
CONFIG_SYS_MMC_ENV_PART=2
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_CLK=y
|
||||
CONFIG_CLK_RENESAS=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_RCAR_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_I2C=y
|
||||
CONFIG_SYS_I2C_RCAR_IIC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_IO_VOLTAGE=y
|
||||
CONFIG_MMC_UHS_SUPPORT=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
CONFIG_RENESAS_SDHI=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_BAR=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_SPI_FLASH_USE_4K_SECTORS=y
|
||||
CONFIG_BITBANGMII=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_RENESAS_RAVB=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
20
include/configs/hihope-rzg2.h
Normal file
20
include/configs/hihope-rzg2.h
Normal file
@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* include/configs/hihope-rzg2.h
|
||||
* This file is HOPERUN HiHope RZ/G2 board configuration.
|
||||
*
|
||||
* Copyright (C) 2020 Renesas Electronics Corporation
|
||||
*/
|
||||
|
||||
#ifndef __HIHOPE_RZG2_H
|
||||
#define __HIHOPE_RZG2_H
|
||||
|
||||
#include "rcar-gen3-common.h"
|
||||
|
||||
/* Ethernet RAVB */
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Generic Timer Definitions (use in assembler source) */
|
||||
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
|
||||
|
||||
#endif /* __HIHOPE_RZG2_H */
|
||||
Loading…
Reference in New Issue
Block a user