exynos: update tzpc to make it common for exynos4 and exynos5
This requires that cpu_is_exynos4/5 should be made available before tzpc_init. Hence this patch also makes necessary changes to have cpu_info in spl and invokes arch_cpu_init before tzpc_init in low_level_init.S for smdk5250. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -22,6 +22,7 @@
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/tzpc.h>
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#include <asm/io.h>
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@ -29,20 +30,28 @@
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void tzpc_init(void)
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{
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struct exynos_tzpc *tzpc;
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unsigned int addr;
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unsigned int addr, start = 0, end = 0;
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for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) {
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start = samsung_get_base_tzpc();
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if (cpu_is_exynos5())
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end = start + ((EXYNOS5_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
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else if (cpu_is_exynos4())
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end = start + ((EXYNOS4_NR_TZPC_BANKS - 1) * TZPC_BASE_OFFSET);
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for (addr = start; addr <= end; addr += TZPC_BASE_OFFSET) {
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tzpc = (struct exynos_tzpc *)addr;
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if (addr == TZPC0_BASE)
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if (addr == start)
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writel(R0SIZE, &tzpc->r0size);
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writel(DECPROTXSET, &tzpc->decprot0set);
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writel(DECPROTXSET, &tzpc->decprot1set);
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if (addr != TZPC9_BASE) {
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writel(DECPROTXSET, &tzpc->decprot2set);
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writel(DECPROTXSET, &tzpc->decprot3set);
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}
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if (cpu_is_exynos5() && (addr == end))
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break;
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writel(DECPROTXSET, &tzpc->decprot2set);
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writel(DECPROTXSET, &tzpc->decprot3set);
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}
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}
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@ -26,9 +26,11 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)libs5p-common.o
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COBJS-y += cpu_info.o
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ifndef CONFIG_SPL_BUILD
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COBJS-y += timer.o
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COBJS-y += sromc.o
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COBJS-$(CONFIG_PWM) += pwm.o
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endif
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS))
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@ -38,6 +38,7 @@
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#define EXYNOS4_CLOCK_BASE 0x10030000
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#define EXYNOS4_SYSTIMER_BASE 0x10050000
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#define EXYNOS4_WATCHDOG_BASE 0x10060000
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#define EXYNOS4_TZPC_BASE 0x10110000
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#define EXYNOS4_MIU_BASE 0x10600000
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#define EXYNOS4_DMC0_BASE 0x10400000
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#define EXYNOS4_DMC1_BASE 0x10410000
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@ -74,6 +75,7 @@
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#define EXYNOS4X12_CLOCK_BASE 0x10030000
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#define EXYNOS4X12_SYSTIMER_BASE 0x10050000
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#define EXYNOS4X12_WATCHDOG_BASE 0x10060000
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#define EXYNOS4X12_TZPC_BASE 0x10110000
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#define EXYNOS4X12_DMC0_BASE 0x10600000
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#define EXYNOS4X12_DMC1_BASE 0x10610000
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#define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
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@ -107,6 +109,7 @@
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#define EXYNOS5_POWER_BASE 0x10040000
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#define EXYNOS5_SWRESET 0x10040400
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#define EXYNOS5_SYSREG_BASE 0x10050000
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#define EXYNOS5_TZPC_BASE 0x10100000
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#define EXYNOS5_WATCHDOG_BASE 0x101D0000
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#define EXYNOS5_ACE_SFR_BASE 0x10830000
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#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
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@ -233,6 +236,7 @@ SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
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SAMSUNG_BASE(power, POWER_BASE)
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SAMSUNG_BASE(spi, SPI_BASE)
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SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
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SAMSUNG_BASE(tzpc, TZPC_BASE)
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#endif
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#endif /* _EXYNOS4_CPU_H */
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@ -48,18 +48,10 @@ struct exynos_tzpc {
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unsigned int pcellid3;
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};
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/* TZPC : Register Offsets */
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#define TZPC0_BASE 0x10100000
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#define TZPC1_BASE 0x10110000
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#define TZPC2_BASE 0x10120000
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#define TZPC3_BASE 0x10130000
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#define TZPC4_BASE 0x10140000
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#define TZPC5_BASE 0x10150000
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#define TZPC6_BASE 0x10160000
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#define TZPC7_BASE 0x10170000
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#define TZPC8_BASE 0x10180000
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#define TZPC9_BASE 0x10190000
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#define EXYNOS4_NR_TZPC_BANKS 6
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#define EXYNOS5_NR_TZPC_BANKS 10
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/* TZPC : Register Offsets */
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#define TZPC_BASE_OFFSET 0x10000
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/*
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@ -75,12 +75,14 @@ lowlevel_init:
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bl mem_ctrl_init
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1:
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bl arch_cpu_init
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bl tzpc_init
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ldmia r13!, {ip,pc}
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wakeup_reset:
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bl system_clock_init
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bl mem_ctrl_init
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bl arch_cpu_init
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bl tzpc_init
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exit_wakeup:
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@ -102,6 +102,10 @@ ifneq ($(CONFIG_MX23)$(CONFIG_MX35),)
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LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
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endif
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ifeq ($(SOC),exynos)
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LIBS-y += $(CPUDIR)/s5p-common/libs5p-common.o
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endif
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# Add GCC lib
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ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
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PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
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