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nand: Try to align the default buffers

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The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
This commit is contained in:
Simon Glass 2012-07-29 20:53:25 +00:00 committed by Tom Warren
parent 057df193b4
commit b572595ee9
2 changed files with 6 additions and 4 deletions
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3
drivers/mtd/nand/nand_base.c
View File

@ -2936,7 +2936,8 @@ int nand_scan_tail(struct mtd_info *mtd)
struct nand_chip *chip = mtd->priv;
if (!(chip->options & NAND_OWN_BUFFERS))
chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
chip->buffers = memalign(ARCH_DMA_MINALIGN,
sizeof(*chip->buffers));
if (!chip->buffers)
return -ENOMEM;

7
include/linux/mtd/nand.h
View File

@ -391,9 +391,10 @@ struct nand_ecc_ctrl {
* consecutive order.
*/
struct nand_buffers {
uint8_t ecccalc[NAND_MAX_OOBSIZE];
uint8_t ecccode[NAND_MAX_OOBSIZE];
uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
ARCH_DMA_MINALIGN)];
};
/**