fpga: zynqmp: support loading encrypted bitfiles
Add supporting new compatible string "u-boot,zynqmp-fpga-enc" to handle loading encrypted bitfiles. This feature requires encrypted FSBL, as according to UG1085: "The CSU automatically locks out the AES key, stored in either BBRAM or eFUSEs, as a key source to the AES engine if the FSBL is not encrypted. This prevents using the BBRAM or eFUSE as the key source to the AES engine during run-time applications." Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io> Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com> Link: https://lore.kernel.org/r/20220722141614.297383-14-oleksandr.suvorov@foundries.io Signed-off-by: Michal Simek <michal.simek@amd.com>
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@ -188,6 +188,8 @@ the '/images' node should have the following layout:
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"u-boot,fpga-legacy" - the generic fpga loading routine.
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"u-boot,zynqmp-fpga-ddrauth" - signed non-encrypted FPGA bitstream for
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Xilinx Zynq UltraScale+ (ZymqMP) device.
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"u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq
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UltraScale+ (ZynqMP) device.
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Optional nodes:
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- hash-1 : Each hash sub-node represents separate hash or checksum
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@ -257,6 +257,11 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
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info.authflag = ZYNQMP_FPGA_AUTH_DDR;
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info.encflag = FPGA_NO_ENC_OR_NO_AUTH;
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return desc->operations->loads(desc, buf, bsize, &info);
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case FPGA_XILINX_ZYNQMP_ENC:
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/* Encryption using device key */
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info.authflag = FPGA_NO_ENC_OR_NO_AUTH;
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info.encflag = FPGA_ENC_DEV_KEY;
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return desc->operations->loads(desc, buf, bsize, &info);
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#endif
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default:
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printf("Unsupported bitstream type %d\n", flags);
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@ -360,6 +365,9 @@ static int __maybe_unused zynqmp_str2flag(xilinx_desc *desc, const char *str)
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#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
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if (!strncmp(str, "u-boot,zynqmp-fpga-ddrauth", 26))
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return FPGA_XILINX_ZYNQMP_DDRAUTH;
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if (!strncmp(str, "u-boot,zynqmp-fpga-enc", 22))
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return FPGA_XILINX_ZYNQMP_ENC;
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#endif
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return 0;
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}
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@ -20,6 +20,7 @@
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/* device numbers must be non-negative */
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#define FPGA_INVALID_DEVICE -1
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#define FPGA_ENC_DEV_KEY 0
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#define FPGA_ENC_USR_KEY 1
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#define FPGA_NO_ENC_OR_NO_AUTH 2
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@ -40,6 +40,7 @@ typedef enum { /* typedef xilinx_family */
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/* FPGA bitstream supported types */
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#define FPGA_LEGACY BIT(0)
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#define FPGA_XILINX_ZYNQMP_DDRAUTH BIT(1)
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#define FPGA_XILINX_ZYNQMP_ENC BIT(2)
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typedef struct { /* typedef xilinx_desc */
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xilinx_family family; /* part type */
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@ -26,7 +26,9 @@
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extern struct xilinx_fpga_op zynqmp_op;
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#if CONFIG_IS_ENABLED(FPGA_LOAD_SECURE)
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#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | FPGA_XILINX_ZYNQMP_DDRAUTH)
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#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY | \
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FPGA_XILINX_ZYNQMP_DDRAUTH | \
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FPGA_XILINX_ZYNQMP_ENC)
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#else
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#define ZYNQMP_FPGA_FLAGS (FPGA_LEGACY)
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#endif
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