From 55ad6123067d1f4158c4b011672a354038bca373 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:30 +0200 Subject: [PATCH 01/42] arm: imxrt: soc: make mpu regions generic This mpu handling works for every i.MXRT SoC that we have, so let's generalize imxrt1050_region_config to imxrt_region_config. Signed-off-by: Giulio Benetti --- arch/arm/mach-imx/imxrt/soc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index 8e7d15160d..c533f3554a 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -14,7 +14,7 @@ int arch_cpu_init(void) { int i; - struct mpu_region_config imxrt1050_region_config[] = { + struct mpu_region_config imxrt_region_config[] = { { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, STRONG_ORDER, REGION_4GB }, { PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW, @@ -29,8 +29,8 @@ int arch_cpu_init(void) * the whole 4GB address space. */ disable_mpu(); - for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++) - mpu_config(&imxrt1050_region_config[i]); + for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++) + mpu_config(&imxrt_region_config[i]); enable_mpu(); return 0; From f8c8573b85765f60d4c4ef022a1fc57bbb2dd704 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:31 +0200 Subject: [PATCH 02/42] timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] --- drivers/timer/Kconfig | 7 ++ drivers/timer/Makefile | 1 + drivers/timer/imx-gpt-timer.c | 162 ++++++++++++++++++++++++++++++++++ 3 files changed, 170 insertions(+) create mode 100644 drivers/timer/imx-gpt-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 80743a2551..ee81dfa776 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -227,4 +227,11 @@ config MCHP_PIT64B_TIMER Select this to enable support for Microchip 64-bit periodic interval timer. +config IMX_GPT_TIMER + bool "NXP i.MX GPT timer support" + depends on TIMER + help + Select this to enable support for the timer found on + NXP i.MX devices. + endmenu diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 2ebdeab0ce..e2bd530eb0 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -25,3 +25,4 @@ obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o +obj-$(CONFIG_IMX_GPT_TIMER) += imx-gpt-timer.o diff --git a/drivers/timer/imx-gpt-timer.c b/drivers/timer/imx-gpt-timer.c new file mode 100644 index 0000000000..72be297754 --- /dev/null +++ b/drivers/timer/imx-gpt-timer.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * Author(s): Giulio Benetti + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define GPT_CR_EN BIT(0) +#define GPT_CR_FRR BIT(9) +#define GPT_CR_EN_24M BIT(10) +#define GPT_CR_SWR BIT(15) + +#define GPT_PR_PRESCALER24M_MASK 0x0000F000 +#define GPT_PR_PRESCALER24M_SHIFT 12 +#define GPT_PR_PRESCALER24M_MAX (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT) +#define GPT_PR_PRESCALER_MASK 0x00000FFF +#define GPT_PR_PRESCALER_SHIFT 0 +#define GPT_PR_PRESCALER_MAX (GPT_PR_PRESCALER_MASK >> GPT_PR_PRESCALER_SHIFT) + +#define GPT_CLKSRC_IPG_CLK (1 << 6) +#define GPT_CLKSRC_IPG_CLK_24M (5 << 6) + +/* If CONFIG_SYS_HZ_CLOCK not specified et's default to 3Mhz */ +#ifndef CONFIG_SYS_HZ_CLOCK +#define CONFIG_SYS_HZ_CLOCK 3000000 +#endif + +struct imx_gpt_timer_regs { + u32 cr; + u32 pr; + u32 sr; + u32 ir; + u32 ocr1; + u32 ocr2; + u32 ocr3; + u32 icr1; + u32 icr2; + u32 cnt; +}; + +struct imx_gpt_timer_priv { + struct imx_gpt_timer_regs *base; +}; + +static u64 imx_gpt_timer_get_count(struct udevice *dev) +{ + struct imx_gpt_timer_priv *priv = dev_get_priv(dev); + struct imx_gpt_timer_regs *regs = priv->base; + + return timer_conv_64(readl(®s->cnt)); +} + +static int imx_gpt_setup(struct imx_gpt_timer_regs *regs, u32 rate) +{ + u32 prescaler = (rate / CONFIG_SYS_HZ_CLOCK) - 1; + + /* Reset the timer */ + setbits_le32(®s->cr, GPT_CR_SWR); + + /* Wait for timer to finish reset */ + while (readl(®s->cr) & GPT_CR_SWR) + ; + + if (rate == 24000000UL) { + /* Set timer frequency if using 24M clock source */ + if (prescaler > GPT_PR_PRESCALER24M_MAX) + return -EINVAL; + + /* Set 24M prescaler */ + writel((prescaler << GPT_PR_PRESCALER24M_SHIFT), ®s->pr); + /* Set Oscillator as clock source, enable 24M input and set gpt + * in free-running mode + */ + writel(GPT_CLKSRC_IPG_CLK_24M | GPT_CR_EN_24M | GPT_CR_FRR, ®s->cr); + } else { + if (prescaler > GPT_PR_PRESCALER_MAX) + return -EINVAL; + + /* Set prescaler */ + writel((prescaler << GPT_PR_PRESCALER_SHIFT), ®s->pr); + /* Set Peripheral as clock source and set gpt in free-running + * mode + */ + writel(GPT_CLKSRC_IPG_CLK | GPT_CR_FRR, ®s->cr); + } + + /* Start timer */ + setbits_le32(®s->cr, GPT_CR_EN); + + return 0; +} + +static int imx_gpt_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct imx_gpt_timer_priv *priv = dev_get_priv(dev); + struct imx_gpt_timer_regs *regs; + struct clk clk; + fdt_addr_t addr; + u32 clk_rate; + int ret; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct imx_gpt_timer_regs *)addr; + regs = priv->base; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "Failed to enable clock\n"); + return ret; + } + + /* Get timer clock rate */ + clk_rate = clk_get_rate(&clk); + if (clk_rate <= 0) { + dev_err(dev, "Could not get clock rate...\n"); + return -EINVAL; + } + + ret = imx_gpt_setup(regs, clk_rate); + if (ret) { + dev_err(dev, "Could not setup timer\n"); + return ret; + } + + uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; + + return 0; +} + +static const struct timer_ops imx_gpt_timer_ops = { + .get_count = imx_gpt_timer_get_count, +}; + +static const struct udevice_id imx_gpt_timer_ids[] = { + { .compatible = "fsl,imxrt-gpt" }, + {} +}; + +U_BOOT_DRIVER(imx_gpt_timer) = { + .name = "imx_gpt_timer", + .id = UCLASS_TIMER, + .of_match = imx_gpt_timer_ids, + .priv_auto = sizeof(struct imx_gpt_timer_priv), + .probe = imx_gpt_timer_probe, + .ops = &imx_gpt_timer_ops, +}; From bfdbe871a0e1bce36ec816b4ae2b2504fb2a895b Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:32 +0200 Subject: [PATCH 03/42] ARM: dts: imxrt1020: add node label to osc Let's add node label to osc to be used as clock source for other nodes. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi index 97f3cec9f3..0a3a3b451a 100644 --- a/arch/arm/dts/imxrt1020.dtsi +++ b/arch/arm/dts/imxrt1020.dtsi @@ -36,7 +36,7 @@ clock-frequency = <0>; }; - osc { + osc: osc { u-boot,dm-spl; compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; From df243c93d3094b658766ab73386e788be5ecfc08 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:33 +0200 Subject: [PATCH 04/42] ARM: dts: imxrt1020: add gpt1 node Add gpt1 node for using it as timer. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi index 0a3a3b451a..cab608c644 100644 --- a/arch/arm/dts/imxrt1020.dtsi +++ b/arch/arm/dts/imxrt1020.dtsi @@ -129,5 +129,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + gpt1: gpt1@401ec000 { + compatible = "fsl,imxrt-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc>; + status = "disabled"; + }; }; }; From bc4944051ed832e36234de39ba641870b839c70e Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:34 +0200 Subject: [PATCH 05/42] ARM: dts: imxrt1020-evk: enable gpt1 timer Enable gpt1 timer. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts index ece13601bd..a471ff3838 100644 --- a/arch/arm/dts/imxrt1020-evk.dts +++ b/arch/arm/dts/imxrt1020-evk.dts @@ -186,6 +186,10 @@ }; }; +&gpt1 { + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; From e5d10f4442598f83c77a983bc136c84a9199e8e5 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:35 +0200 Subject: [PATCH 06/42] ARM: dts: imxrt1020-evk: set gpt1 as tick-timer for u-boot Let's set gpt1 as u-boot timer. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts index a471ff3838..b527206fcf 100644 --- a/arch/arm/dts/imxrt1020-evk.dts +++ b/arch/arm/dts/imxrt1020-evk.dts @@ -16,6 +16,7 @@ chosen { bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; + tick-timer = &gpt1; }; memory { From faa4e95b5cda060e5c5449038d38b727fee7e5a7 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:36 +0200 Subject: [PATCH 07/42] ARM: dts: imxrt1020-evk-u-boot: make gpt1 present for SPL Timer needs to be already enabled in spl, so let's add its node to spl dtb. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi index d32c98de9c..34d19e06c5 100644 --- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi @@ -10,6 +10,10 @@ }; }; +&gpt1 { + u-boot,dm-spl; +}; + &lpuart1 { /* console */ u-boot,dm-spl; }; From d956990c69dd1664c6c577d8d81e459606961991 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:37 +0200 Subject: [PATCH 08/42] ARM: dts: imxrt1020-evk: add device_type = "memory" to memory node Now device_type = "memory" is mandatory to allow u-boot to read memory node, so let's add it to memory node. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts index b527206fcf..2da79e5c20 100644 --- a/arch/arm/dts/imxrt1020-evk.dts +++ b/arch/arm/dts/imxrt1020-evk.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x2000000>; }; }; From a2d89cce7c21925ac77ccfaa201d1d2a65fdbf5d Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:38 +0200 Subject: [PATCH 09/42] configs: imxrt1020-evk: enable imx gpt timer as tick-timer Let's enable imx-gpt-timer in imx1020-evk defconfig. Signed-off-by: Giulio Benetti --- configs/imxrt1020-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig index ad408ebef8..f0b05b7165 100644 --- a/configs/imxrt1020-evk_defconfig +++ b/configs/imxrt1020-evk_defconfig @@ -61,6 +61,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_SHA1=y CONFIG_SHA256=y CONFIG_HEXDUMP=y From 6cd7a9b8506af170bc5f44f06db03d4dfed0d962 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:39 +0200 Subject: [PATCH 10/42] ARM: dts: imxrt1050: add node label to osc Let's add node label to osc to be used as clock source for other nodes. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index a9281001e5..b7cc3fbc2a 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -28,7 +28,7 @@ clocks { u-boot,dm-spl; - osc { + osc: osc { u-boot,dm-spl; compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; From 5790db9283c905205546c33c94f272f6d4ac03bf Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:40 +0200 Subject: [PATCH 11/42] ARM: dts: imxrt1050: add gpt1 node Add gpt1 node for using it as timer. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index b7cc3fbc2a..6f9da3fe8a 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -154,5 +154,13 @@ clock-names = "per"; status = "disabled"; }; + + gpt1: gpt1@401ec000 { + compatible = "fsl,imxrt-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc>; + status = "disabled"; + }; }; }; From 7eacc427bbf3dcd767823fc4ab70ea5a428f1e48 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:41 +0200 Subject: [PATCH 12/42] ARM: dts: imxrt1050-evk: enable gpt1 timer Enable gpt1 timer. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index b5e781275e..e592330332 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -215,6 +215,10 @@ }; }; +&gpt1 { + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; From 7892f3eba1d93d6da1432781bcebb7ee65bf4742 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:42 +0200 Subject: [PATCH 13/42] ARM: dts: imxrt1050-evk: set gpt1 as tick-timer for u-boot Let's set gpt1 as u-boot timer. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index e592330332..6d21f2b738 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -16,6 +16,7 @@ chosen { bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; + tick-timer = &gpt1; }; memory { From 0684ec8a9dbbd8cde518e45b651393f3669b0a03 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:43 +0200 Subject: [PATCH 14/42] ARM: dts: imxrt1050-evk-u-boot: make gpt1 present for SPL Timer needs to be already enabled in spl, so let's add its node to spl dtb. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi index fb4f7f6f9d..a4b50f0bb2 100644 --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi @@ -10,6 +10,10 @@ }; }; +&gpt1 { + u-boot,dm-spl; +}; + &lpuart1 { /* console */ u-boot,dm-spl; }; From 6f6f03af0efe02d68f65b0b475184f654d9d2126 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:44 +0200 Subject: [PATCH 15/42] ARM: dts: imxrt1050-evk: add device_type = "memory" to memory node Now device_type = "memory" is mandatory to allow u-boot to read memory node, so let's add it to memory node. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index 6d21f2b738..2052d4eb4e 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x2000000>; }; }; From 72d65bdf35fa36af952ecb61adfb410576b82df9 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:45 +0200 Subject: [PATCH 16/42] configs: imxrt1050-evk: enable imx gpt timer as tick-timer Let's enable imx-gpt-timer in imx1050-evk defconfig. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index d03572e7db..9c8bdb07dc 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -64,6 +64,7 @@ CONFIG_IMXRT_SDRAM=y CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y +CONFIG_IMX_GPT_TIMER=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y From ee62a053447ec7f204d086d8c072a601056f10d0 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:46 +0200 Subject: [PATCH 17/42] video: mxsfb: add enabling of "axi" clock other than "per" clock On some SoC mxsfb needs more than one clock gate(actual "per" clock). So let's introduce "axi" clock that can be provided but it's not mandatory. This is inspired from linux mxsfb driver. Also let's rename "per" clock to "pix" clock for compatibility with already existing .dts lcdif nodes implementation. Signed-off-by: Giulio Benetti --- drivers/video/mxsfb.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index e1fd36a62d..147bd668fe 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -67,26 +67,37 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, uint32_t vdctrl0; #if CONFIG_IS_ENABLED(CLK) - struct clk per_clk; + struct clk clk; int ret; - ret = clk_get_by_name(dev, "per", &per_clk); + ret = clk_get_by_name(dev, "pix", &clk); if (ret) { - dev_err(dev, "Failed to get mxs clk: %d\n", ret); + dev_err(dev, "Failed to get mxs pix clk: %d\n", ret); return; } - ret = clk_set_rate(&per_clk, timings->pixelclock.typ); + ret = clk_set_rate(&clk, timings->pixelclock.typ); if (ret < 0) { - dev_err(dev, "Failed to set mxs clk: %d\n", ret); + dev_err(dev, "Failed to set mxs pix clk: %d\n", ret); return; } - ret = clk_enable(&per_clk); + ret = clk_enable(&clk); if (ret < 0) { - dev_err(dev, "Failed to enable mxs clk: %d\n", ret); + dev_err(dev, "Failed to enable mxs pix clk: %d\n", ret); return; } + + ret = clk_get_by_name(dev, "axi", &clk); + if (!ret) { + debug("%s: Failed to get mxs axi clk: %d\n", __func__, ret); + } else { + ret = clk_enable(&clk); + if (ret < 0) { + dev_err(dev, "Failed to enable mxs axi clk: %d\n", ret); + return; + } + } #else /* Kick in the LCDIF clock */ mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000); From 006f0dfb1d6dfa2bf7b1a08d2abcaf40eee6ae96 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:18:47 +0200 Subject: [PATCH 18/42] video: mxsfb: add enabling of "disp_axi" clock Some SoC needs "disp_axi" clock to be enabled, so let's try to retrieve it and enabling. If it fails it gives only a debug(), but this clock as well as "axi" clock is not mandatory. Signed-off-by: Giulio Benetti --- drivers/video/mxsfb.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 147bd668fe..523d8a8d98 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -98,6 +98,17 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, return; } } + + ret = clk_get_by_name(dev, "disp_axi", &clk); + if (!ret) { + debug("%s: Failed to get mxs disp_axi clk: %d\n", __func__, ret); + } else { + ret = clk_enable(&clk); + if (ret < 0) { + dev_err(dev, "Failed to enable mxs disp_axi clk: %d\n", ret); + return; + } + } #else /* Kick in the LCDIF clock */ mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000); From f544dfecd2801489ad7efe24bf3e3452b48f2c40 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:19:33 +0200 Subject: [PATCH 19/42] clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB Lcd peripheral needs 2 different gates to be enable to work, so let's introduce the missing one(LCDIF_PIX) and rename the existing one (LCDIF_APB). Signed-off-by: Giulio Benetti --- drivers/clk/imx/clk-imxrt1050.c | 6 ++++-- include/dt-bindings/clock/imxrt1050-clock.h | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index 594093ee5f..eb6847f865 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -255,8 +255,10 @@ static int imxrt1050_clk_probe(struct udevice *dev) imx_clk_gate2("lpuart1", "lpuart_podf", base + 0x7c, 24)); clk_dm(IMXRT1050_CLK_SEMC, imx_clk_gate2("semc", "semc_podf", base + 0x74, 4)); - clk_dm(IMXRT1050_CLK_LCDIF, - imx_clk_gate2("lcdif", "lcdif_podf", base + 0x74, 10)); + clk_dm(IMXRT1050_CLK_LCDIF_APB, + imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28)); + clk_dm(IMXRT1050_CLK_LCDIF_PIX, + imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10)); struct clk *clk, *clk1; diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h index c174f90c1a..09b65e5df2 100644 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -52,7 +52,7 @@ #define IMXRT1050_CLK_USDHC2 43 #define IMXRT1050_CLK_LPUART1 44 #define IMXRT1050_CLK_SEMC 45 -#define IMXRT1050_CLK_LCDIF 46 +#define IMXRT1050_CLK_LCDIF_APB 46 #define IMXRT1050_CLK_PLL1_ARM 47 #define IMXRT1050_CLK_PLL2_SYS 48 #define IMXRT1050_CLK_PLL3_USB_OTG 49 @@ -60,6 +60,7 @@ #define IMXRT1050_CLK_PLL5_VIDEO 51 #define IMXRT1050_CLK_PLL6_ENET 52 #define IMXRT1050_CLK_PLL7_USB_HOST 53 -#define IMXRT1050_CLK_END 54 +#define IMXRT1050_CLK_LCDIF_PIX 54 +#define IMXRT1050_CLK_END 55 #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ From f2d91e606b7b903dbe7577954fa8e454a2d6e38c Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:19:34 +0200 Subject: [PATCH 20/42] ARM: dts: imxrt1050: move lcdif assigned clock to dtsi Since we assume pll5 is the default lcdif clock source let's move assigned-clocks(-parents) properties to .dtsi file. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk.dts | 3 --- arch/arm/dts/imxrt1050.dtsi | 2 ++ 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index 2052d4eb4e..dc66fc9c37 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -238,9 +238,6 @@ display = <&display0>; status = "okay"; - assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; - display0: display0 { bits-per-pixel = <16>; bus-width = <16>; diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index 6f9da3fe8a..eb5e09e971 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -152,6 +152,8 @@ interrupts = ; clocks = <&clks IMXRT1050_CLK_LCDIF>; clock-names = "per"; + assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; status = "disabled"; }; From a9a5c33d579c1f754092993dc4917ca7f774af32 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:19:35 +0200 Subject: [PATCH 21/42] ARM: dts: imxrt1050: set lcdif clocks according to mxsfb driver Lcdif needs both "pix" and "axi" clocks to be enabled so let's add them to lcdif node. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index eb5e09e971..ec1eb88e45 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -150,8 +150,9 @@ compatible = "fsl,imxrt-lcdif"; reg = <0x402b8000 0x4000>; interrupts = ; - clocks = <&clks IMXRT1050_CLK_LCDIF>; - clock-names = "per"; + clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>, + <&clks IMXRT1050_CLK_LCDIF_APB>; + clock-names = "pix", "axi"; assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; status = "disabled"; From 31f0e585271291252deb1c809c6e710cbf54dec9 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 13 May 2021 12:19:36 +0200 Subject: [PATCH 22/42] ARM: dts: imxrt1050-evk: remove u-boot,dm-spl We don't need lcdif to be enable in SPL, so let's remove u-boot,dm-spl. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index dc66fc9c37..81db1a446d 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -189,7 +189,6 @@ }; pinctrl_lcdif: lcdifgrp { - u-boot,dm-spl; fsl,pins = < MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1 MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1 From 1f3555d906442b3899660c9120a89cee12ab1d06 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sun, 16 May 2021 23:57:00 +0200 Subject: [PATCH 23/42] ARM: dts: imxrt1050-evk: move all u-boot, dm-spl to imxrt1050-evk-u-boot.dtsi file At the moment a lot of u-boot,dm-spl properties are present in board .dts file but this is not correct since u-boot,dm-spl property is u-boot specific and must be listed into the separate imrt1050-evk-u-boot.dtsi file. So let's move every u-boot,dm-spl property present in imxrt1050-evk.dts to imxrt1050-evk-u-boot.dtsi file. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk-u-boot.dtsi | 38 ++++++++++++++++++++++++++ arch/arm/dts/imxrt1050.dtsi | 13 --------- 2 files changed, 38 insertions(+), 13 deletions(-) diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi index a4b50f0bb2..3168c2df2c 100644 --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi @@ -8,6 +8,42 @@ chosen { u-boot,dm-spl; }; + + clocks { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + }; +}; + +&osc { + u-boot,dm-spl; +}; + +&clks { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; }; &gpt1 { @@ -19,6 +55,8 @@ }; &semc { + u-boot,dm-spl; + bank1: bank@0 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index ec1eb88e45..1f28304981 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -26,10 +26,7 @@ }; clocks { - u-boot,dm-spl; - osc: osc { - u-boot,dm-spl; compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; @@ -37,10 +34,7 @@ }; soc { - u-boot,dm-spl; - semc: semc@402f0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-semc"; reg = <0x402f0000 0x4000>; clocks = <&clks IMXRT1050_CLK_SEMC>; @@ -65,7 +59,6 @@ }; clks: ccm@400fc000 { - u-boot,dm-spl; compatible = "fsl,imxrt1050-ccm"; reg = <0x400fc000 0x4000>; interrupts = , @@ -74,7 +67,6 @@ }; usdhc1: usdhc@402c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-usdhc"; reg = <0x402c0000 0x10000>; interrupts = ; @@ -87,7 +79,6 @@ }; gpio1: gpio@401b8000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401b8000 0x4000>; interrupts = , @@ -99,7 +90,6 @@ }; gpio2: gpio@401bc000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401bc000 0x4000>; interrupts = , @@ -111,7 +101,6 @@ }; gpio3: gpio@401c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401c0000 0x4000>; interrupts = , @@ -123,7 +112,6 @@ }; gpio4: gpio@401c4000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401c4000 0x4000>; interrupts = , @@ -135,7 +123,6 @@ }; gpio5: gpio@400c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x400c0000 0x4000>; interrupts = , From dc54f8290150ebf9d54ece7b6ece188dc616b6db Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sun, 16 May 2021 23:57:01 +0200 Subject: [PATCH 24/42] ARM: dts: imxrt1020-evk: move all u-boot, dm-spl to imxrt1020-evk-u-boot.dtsi file At the moment a lot of u-boot,dm-spl properties are present in board .dts file but this is not correct since u-boot,dm-spl property is u-boot specific and must be listed into the separate imrt1020-evk-u-boot.dtsi file. So let's move every u-boot,dm-spl property present in imxrt1020-evk.dts to imxrt1020-evk-u-boot.dtsi file. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020-evk-u-boot.dtsi | 34 ++++++++++++++++++++++++++ arch/arm/dts/imxrt1020.dtsi | 10 -------- 2 files changed, 34 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi index 34d19e06c5..121665a2d2 100644 --- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi @@ -8,6 +8,38 @@ chosen { u-boot,dm-spl; }; + + clocks { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + }; +}; + +&osc { + u-boot,dm-spl; +}; + +&clks { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; }; &gpt1 { @@ -19,6 +51,8 @@ }; &semc { + u-boot,dm-spl; + bank1: bank@0 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi index cab608c644..884d57f614 100644 --- a/arch/arm/dts/imxrt1020.dtsi +++ b/arch/arm/dts/imxrt1020.dtsi @@ -23,7 +23,6 @@ }; clocks { - u-boot,dm-spl; ckil { compatible = "fsl,imx-ckil", "fixed-clock"; #clock-cells = <0>; @@ -37,7 +36,6 @@ }; osc: osc { - u-boot,dm-spl; compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; @@ -45,10 +43,7 @@ }; soc { - u-boot,dm-spl; - semc: semc@402f0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-semc"; reg = <0x402f0000 0x4000>; clocks = <&clks IMXRT1020_CLK_SEMC>; @@ -73,7 +68,6 @@ }; clks: ccm@400fc000 { - u-boot,dm-spl; compatible = "fsl,imxrt1020-ccm"; reg = <0x400fc000 0x4000>; interrupts = , @@ -82,7 +76,6 @@ }; usdhc1: usdhc@402c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-usdhc"; reg = <0x402c0000 0x10000>; interrupts = ; @@ -95,7 +88,6 @@ }; gpio1: gpio@401b8000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401b8000 0x4000>; interrupts = , @@ -107,7 +99,6 @@ }; gpio2: gpio@401bc000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401bc000 0x4000>; interrupts = , @@ -119,7 +110,6 @@ }; gpio3: gpio@401c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401c0000 0x4000>; interrupts = , From d7308dbd864c1d0447bfe62cc42a6ff470369d66 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sun, 16 May 2021 23:57:02 +0200 Subject: [PATCH 25/42] ARM: dts: imxrt1020: add gpio5 node to this SoC i.MXRT1020 supports gpio5, so let's add a node for it. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1020.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi index 884d57f614..5ba314f995 100644 --- a/arch/arm/dts/imxrt1020.dtsi +++ b/arch/arm/dts/imxrt1020.dtsi @@ -120,6 +120,17 @@ #interrupt-cells = <2>; }; + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpt1: gpt1@401ec000 { compatible = "fsl,imxrt-gpt"; reg = <0x401ec000 0x4000>; From 0d90dec18222871d6884aa7ed483169cd016e399 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 20 May 2021 16:10:13 +0200 Subject: [PATCH 26/42] ARM: IMXRT: introduce is_imxrt*() macros and get_cpu_rev() We need those macros to instruct drivers on how to behave for SoC specific quirks, so let's add it as done for other i.MX SoCs. Signed-off-by: Giulio Benetti --- arch/arm/include/asm/arch-imx/cpu.h | 3 +++ arch/arm/include/asm/mach-imx/sys_proto.h | 4 ++++ arch/arm/mach-imx/imxrt/soc.c | 12 ++++++++++++ 3 files changed, 19 insertions(+) diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index bb13e07b66..267a094e5a 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -50,6 +50,8 @@ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ +#define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ +#define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ @@ -57,6 +59,7 @@ #define MXC_SOC_MX7 0x70 #define MXC_SOC_IMX8M 0x80 #define MXC_SOC_IMX8 0x90 /* dummy */ +#define MXC_SOC_IMXRT 0xB0 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_0 0x10 diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index c7668ffc4d..b612189849 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -31,6 +31,7 @@ struct bd_info; #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) @@ -78,6 +79,9 @@ struct bd_info; #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) +#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) +#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) + #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index c533f3554a..ba015992ee 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include int arch_cpu_init(void) @@ -35,3 +36,14 @@ int arch_cpu_init(void) return 0; } + +u32 get_cpu_rev(void) +{ +#if defined(CONFIG_IMXRT1020) + return MXC_CPU_IMXRT1020 << 12; +#elif defined(CONFIG_IMXRT1050) + return MXC_CPU_IMXRT1050 << 12; +#else +#error This IMXRT SoC is not supported +#endif +} From 45a5f76cfcf59e4965075bf17663e2e0b1b3ab7f Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 20 May 2021 16:10:14 +0200 Subject: [PATCH 27/42] clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3 Usb needs IMXRT1050_CLK_USBOH3 clock to be enabled, so let's add it to clock driver. Signed-off-by: Giulio Benetti --- drivers/clk/imx/clk-imxrt1050.c | 2 ++ include/dt-bindings/clock/imxrt1050-clock.h | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c index eb6847f865..3e17161002 100644 --- a/drivers/clk/imx/clk-imxrt1050.c +++ b/drivers/clk/imx/clk-imxrt1050.c @@ -259,6 +259,8 @@ static int imxrt1050_clk_probe(struct udevice *dev) imx_clk_gate2("lcdif", "lcdif_podf", base + 0x70, 28)); clk_dm(IMXRT1050_CLK_LCDIF_PIX, imx_clk_gate2("lcdif_pix", "lcdif", base + 0x74, 10)); + clk_dm(IMXRT1050_CLK_USBOH3, + imx_clk_gate2("usboh3", "pll3_usb_otg", base + 0x80, 0)); struct clk *clk, *clk1; diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h index 09b65e5df2..f74dbbcf93 100644 --- a/include/dt-bindings/clock/imxrt1050-clock.h +++ b/include/dt-bindings/clock/imxrt1050-clock.h @@ -61,6 +61,7 @@ #define IMXRT1050_CLK_PLL6_ENET 52 #define IMXRT1050_CLK_PLL7_USB_HOST 53 #define IMXRT1050_CLK_LCDIF_PIX 54 -#define IMXRT1050_CLK_END 55 +#define IMXRT1050_CLK_USBOH3 55 +#define IMXRT1050_CLK_END 56 #endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */ From e7e81e8959ebc3d5031eae3d5ff03990656f5c36 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 20 May 2021 16:10:15 +0200 Subject: [PATCH 28/42] usb: ehci-mx6: add support for i.MXRT Add support for usb1 and usb2 present on i.IMXRT. Signed-off-by: Giulio Benetti --- arch/arm/include/asm/arch-imxrt/imx-regs.h | 4 ++++ drivers/usb/host/Kconfig | 2 +- drivers/usb/host/ehci-mx6.c | 13 +++++++------ 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h index 44c95dcd11..d01e6ca2e0 100644 --- a/arch/arm/include/asm/arch-imxrt/imx-regs.h +++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h @@ -23,4 +23,8 @@ #include #endif +#define USB_BASE_ADDR 0x402E0000 +#define USB_PHY0_BASE_ADDR 0x400D9000 +#define USB_PHY1_BASE_ADDR 0x400DA000 + #endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index bf5d82f035..f34cba2395 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -149,7 +149,7 @@ config USB_EHCI_MX5 config USB_EHCI_MX6 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" - depends on ARCH_MX6 || ARCH_MX7ULP + depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT default y ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 06be9deaaa..238c93183b 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -177,7 +177,7 @@ static void __maybe_unused usb_power_config_mx7ulp(void *usbphy) { } #endif -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT) static const unsigned phy_bases[] = { USB_PHY0_BASE_ADDR, #if defined(USB_PHY1_BASE_ADDR) @@ -340,7 +340,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { enum usb_init_type type; -#if defined(CONFIG_MX6) +#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT) u32 controller_spacing = 0x200; struct anatop_regs __iomem *anatop = (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; @@ -382,7 +382,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, return ret; } -#if defined(CONFIG_MX6) +#if defined(CONFIG_MX6) || defined(CONFIG_IMXRT) usb_power_config_mx6(anatop, index); #elif defined (CONFIG_MX7) usb_power_config_mx7(usbnc); @@ -392,7 +392,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, usb_oc_config(usbnc, index); -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT) if (index < ARRAY_SIZE(phy_bases)) { usb_internal_phy_clock_gate((void __iomem *)phy_bases[index], 1); usb_phy_enable(ehci, (void __iomem *)phy_bases[index]); @@ -504,7 +504,7 @@ static int ehci_usb_phy_mode(struct udevice *dev) * About fsl,usbphy, Refer to * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt. */ - if (is_mx6() || is_mx7ulp()) { + if (is_mx6() || is_mx7ulp() || is_imxrt()) { phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy"); @@ -671,7 +671,7 @@ static int ehci_usb_probe(struct udevice *dev) usb_oc_config(priv->misc_addr, priv->portnr); -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMXRT) usb_internal_phy_clock_gate(priv->phy_addr, 1); usb_phy_enable(ehci, priv->phy_addr); #endif @@ -757,6 +757,7 @@ int ehci_usb_remove(struct udevice *dev) static const struct udevice_id mx6_usb_ids[] = { { .compatible = "fsl,imx27-usb" }, { .compatible = "fsl,imx7d-usb" }, + { .compatible = "fsl,imxrt-usb" }, { } }; From 9b91484a892e48fa4ca7cb91137baa277e2f3908 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 20 May 2021 16:10:16 +0200 Subject: [PATCH 29/42] ARM: dts: imxrt1050: add usbotg1, usbphy1 and usbmisc nodes Usb is now supported so add all required nodes for it in imxrt1050. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index 1f28304981..6560a3827f 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -23,6 +23,7 @@ gpio4 = &gpio5; mmc0 = &usdhc1; serial0 = &lpuart1; + usbphy0 = &usbphy1; }; clocks { @@ -152,5 +153,31 @@ clocks = <&osc>; status = "disabled"; }; + + usbphy1: usbphy@400d9000 { + compatible = "fsl,imxrt-usbphy"; + reg = <0x400d9000 0x1000>; + interrupts = ; + }; + + usbmisc: usbmisc@402e0800 { + #index-cells = <1>; + compatible = "fsl,imxrt-usbmisc"; + reg = <0x402e0800 0x200>; + clocks = <&clks IMXRT1050_CLK_USBOH3>; + }; + + usbotg1: usb@402e0000 { + compatible = "fsl,imxrt-usb", "fsl,imx27-usb"; + reg = <0x402e0000 0x200>; + interrupts = ; + clocks = <&clks IMXRT1050_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; }; }; From 42b967216ed7e575f640ccfed38abb2ec27de3cd Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 20 May 2021 16:10:17 +0200 Subject: [PATCH 30/42] ARM: dts: imxrt1050-evk: enable usbotg1 node as host Enable usbotg1 port node as host usb. Signed-off-by: Giulio Benetti --- arch/arm/dts/imxrt1050-evk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index 81db1a446d..324cf7af96 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -260,3 +260,8 @@ }; }; }; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; From cb87278cf63cbc968004e77a277378adf2db2058 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Thu, 20 May 2021 16:10:18 +0200 Subject: [PATCH 31/42] configs: imxrt1050-evk: enable host usb support and its command Now that usb host is supported let's enable it on this board. Signed-off-by: Giulio Benetti --- configs/imxrt1050-evk_defconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index 9c8bdb07dc..9f509f3b9f 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -32,8 +32,9 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x100 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_MII is not set -# CONFIG_DOS_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_OF_CONTROL=y @@ -65,6 +66,10 @@ CONFIG_FSL_LPUART=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_IMX_GPT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y CONFIG_DM_VIDEO=y CONFIG_BACKLIGHT_GPIO=y CONFIG_SYS_WHITE_ON_BLACK=y From e2017ef6edcbab4d644579fb59429259d33b815a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 18 May 2021 00:40:30 +0200 Subject: [PATCH 32/42] ARM: imx8m: verdin-imx8mm: Increase bootm size to 64 MiB Uncompressed aarch64 kernel Image are rather large, increase the bootm size limit to 64 MiB to cater for that. Signed-off-by: Marek Vasut Cc: Marcel Ziswiler Cc: Max Krummenacher Cc: Oleksandr Suvorov Reviewed-by: Oleksandr Suvorov --- include/configs/verdin-imx8mm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index e2a817891c..7be5e5ddf1 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -16,6 +16,8 @@ #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) +#define CONFIG_SYS_BOOTM_LEN SZ_64M + #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_STACK 0x920000 #define CONFIG_SPL_BSS_START_ADDR 0x910000 From 3675ac081ad5129cbcb22b06fb6d8e3264a30d20 Mon Sep 17 00:00:00 2001 From: Oleh Kravchenko Date: Sat, 15 May 2021 00:18:31 +0300 Subject: [PATCH 33/42] Add out4.ru O4-iMX-NANO board Board designed for quick prototyping and has one microSD port, 2 Ethernet ports, 2 USB ports, I2C, SPI, CAN, RS-485, GPIO, UART interfaces, and 2 RGB LEDs. Signed-off-by: Oleh Kravchenko Cc: Stefano Babic --- MAINTAINERS | 10 + arch/arm/dts/Makefile | 3 + arch/arm/dts/o4-imx-nano.dts | 241 ++++++++++++++++++ arch/arm/dts/o4-imx6ull-nano.dtsi | 87 +++++++ arch/arm/mach-imx/mx6/Kconfig | 13 + .../out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg | 91 +++++++ board/out4/o4-imx6ull-nano/Kconfig | 57 +++++ .../o4-imx6ull-nano/MT41K256M16HA-125E.cfg | 91 +++++++ board/out4/o4-imx6ull-nano/Makefile | 4 + board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c | 86 +++++++ configs/o4-imx6ull-nano_defconfig | 103 ++++++++ include/configs/o4-imx6ull-nano.h | 33 +++ 12 files changed, 819 insertions(+) create mode 100644 arch/arm/dts/o4-imx-nano.dts create mode 100644 arch/arm/dts/o4-imx6ull-nano.dtsi create mode 100644 board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg create mode 100644 board/out4/o4-imx6ull-nano/Kconfig create mode 100644 board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg create mode 100644 board/out4/o4-imx6ull-nano/Makefile create mode 100644 board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c create mode 100644 configs/o4-imx6ull-nano_defconfig create mode 100644 include/configs/o4-imx6ull-nano.h diff --git a/MAINTAINERS b/MAINTAINERS index 86ff5e04a6..875eb5dfa4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -919,6 +919,16 @@ S: Orphaned (Since 2017-01) T: git https://source.denx.de/u-boot/custodians/u-boot-onenand.git F: drivers/mtd/onenand/ +OUT4-IMX6ULL-NANO BOARD +M: Oleh Kravchenko +S: Maintained +T: git https://github.com/Oleh-Kravchenko/u-boot-out4.git +F: arch/arm/dts/o4-imx-nano.dts +F: arch/arm/dts/o4-imx6ull-nano.dtsi +F: board/out4 +F: configs/o4-imx6ull-nano_defconfig +F: include/configs/o4-imx6ull-nano.h + PATMAN M: Simon Glass S: Maintained diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 096068261d..b944778c1a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -819,6 +819,9 @@ dtb-$(CONFIG_ARCH_MX6) += \ imx6-apalis.dtb \ imx6-colibri.dtb +dtb-$(CONFIG_O4_IMX_NANO) += \ + o4-imx-nano.dtb + dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ imx7-cm.dtb \ diff --git a/arch/arm/dts/o4-imx-nano.dts b/arch/arm/dts/o4-imx-nano.dts new file mode 100644 index 0000000000..d1785b7dc7 --- /dev/null +++ b/arch/arm/dts/o4-imx-nano.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko + +/dts-v1/; + +#include + +#include "o4-imx6ull-nano.dtsi" + +/ { + model = "O4-iMX-NANO"; + compatible = "out4,o4-imx-nano", + "out4,o4-imx6ull-nano", + "fsl,imx6ull"; + + aliases { + mmc1 = &usdhc1; + }; + + chosen { + stdout-path = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + led@0 { + color = ; + gpios = <&pcf8574a 0 GPIO_ACTIVE_LOW>; + reg = <0>; + }; + + led@1 { + color = ; + gpios = <&pcf8574a 1 GPIO_ACTIVE_LOW>; + reg = <1>; + }; + + led@2 { + gpios = <&pcf8574a 2 GPIO_ACTIVE_LOW>; + color = ; + reg = <2>; + }; + + led@3 { + color = ; + gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>; + reg = <3>; + }; + + led@4 { + color = ; + gpios = <&pcf8574a 4 GPIO_ACTIVE_LOW>; + reg = <4>; + }; + + led@5 { + color = ; + gpios = <&pcf8574a 5 GPIO_ACTIVE_LOW>; + reg = <5>; + }; + }; + + usbotg1_vbus: reg_usbotg1_vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pcf8574a 6 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb0"; + }; + + usbotg2_vbus: reg_usbotg2_vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pcf8574a 7 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1"; + }; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b8b0 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b8b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usdhc1 { + bus-width = <4>; + no-1-8-v; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; + status = "okay"; + wakeup-source; +}; + +&fec1 { + phy-handle = <&phy0>; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fec2 { + phy-handle = <&phy1>; + phy-mode = "rmii"; + phy-reset-duration = <250>; + phy-reset-post-delay = <100>; + phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_fec2 &pinctrl_mdio>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_phy0_irq>; + pinctrl-names = "default"; + reg = <0>; + }; + + phy1: ethernet-phy@1 { + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_phy1_irq>; + pinctrl-names = "default"; + reg = <1>; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; + vbus-supply = <&usbotg1_vbus>; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; + vbus-supply = <&usbotg2_vbus>; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio4 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pcf8574a: gpio@38 { + compatible = "nxp,pcf8574a"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x38>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&uart2 { + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + status = "okay"; + uart-has-rtscts; +}; diff --git a/arch/arm/dts/o4-imx6ull-nano.dtsi b/arch/arm/dts/o4-imx6ull-nano.dtsi new file mode 100644 index 0000000000..3fefa80eae --- /dev/null +++ b/arch/arm/dts/o4-imx6ull-nano.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko + +/dts-v1/; + +#include "imx6ull.dtsi" + +/ { + model = "O4-iMX6ULL-NANO"; + compatible = "out4,o4-imx6ull-nano", "fsl,imx6ull"; + + aliases { + mmc0 = &usdhc2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + >; + }; + + pinctrl_phy0_irq: phy0grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79 + >; + }; + + pinctrl_phy1_irq: phy1grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9450e6a683..0f274c41a1 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -619,6 +619,18 @@ config TARGET_BRPPT2 Support B&R BRPPT2 platform based on Freescale's iMX6 SoC + +config TARGET_O4_IMX6ULL_NANO + bool "O4-iMX6ULL-NANO" + depends on MX6ULL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + imply CMD_DM + help + Support for www.out4.ru O4-iMX6UL-NANO platform + based on Freescale's i.MX6UL/i.MX6ULL SoC. + endchoice config SYS_SOC @@ -668,5 +680,6 @@ source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" source "board/BuR/brppt2/Kconfig" +source "board/out4/o4-imx6ull-nano/Kconfig" endif diff --git a/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg b/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg new file mode 100644 index 0000000000..c0dcfe9a0c --- /dev/null +++ b/board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2016 Freescale Semiconductor, Inc. +// Copyright (C) 2021 Oleh Kravchenko + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 +BOOT_FROM sd + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +/* Samsung K4B4G1646D-BCMA */ +DATA 4 0x020e04b4 0x000c0000 +DATA 4 0x020e04ac 0x00000000 +DATA 4 0x020e027c 0x00000030 +DATA 4 0x020e0250 0x00000030 +DATA 4 0x020e024c 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e0288 0x000c0030 +DATA 4 0x020e0270 0x00000000 +DATA 4 0x020e0260 0x00000030 +DATA 4 0x020e0264 0x00000030 +DATA 4 0x020e04a0 0x00000030 +DATA 4 0x020e0494 0x00020000 +DATA 4 0x020e0280 0x00000030 +DATA 4 0x020e0284 0x00000030 +DATA 4 0x020e04b0 0x00020000 +DATA 4 0x020e0498 0x00000030 +DATA 4 0x020e04a4 0x00000030 +DATA 4 0x020e0244 0x00000030 +DATA 4 0x020e0248 0x00000030 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x00030009 +DATA 4 0x021b083c 0x01440148 +DATA 4 0x021b0848 0x40403640 +DATA 4 0x021b0850 0x4040322a +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b08c0 0x00944009 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x1b333030 +DATA 4 0x021b000c 0x676b52f2 +DATA 4 0x021b0010 0x926d0b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00211740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0x84180000 +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b001c 0x02008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x15108030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00007800 +DATA 4 0x021b0818 0x00000227 +DATA 4 0x021b0004 0x0002552d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig new file mode 100644 index 0000000000..c2497d521f --- /dev/null +++ b/board/out4/o4-imx6ull-nano/Kconfig @@ -0,0 +1,57 @@ +if TARGET_O4_IMX6ULL_NANO + +config SYS_BOARD + default "o4-imx6ull-nano" + +config SYS_VENDOR + default "out4" + +config SYS_CONFIG_NAME + default "o4-imx6ull-nano" + +choice + prompt "Memory model" + default K4B4G1646D_BCMA + help + Memory type setup. + + Please choose correct memory model here. + +config K4B4G1646D_BCMA + bool "K4B4G1646D-BCMA 256Mx16 (512 MiB/chip)" + help + Samsung DDR3 SDRAM + K4B4G1646D-BCMA + +config MT41K256M16HA_125E + bool "MT41K256M16HA-125:E 256Mx16 (512 MiB/chip)" + help + Micron DDR3L SDRAM + MT41K256M16HA-125:E + +endchoice + +choice + prompt "Mainboard model" + default O4_IMX_NANO + help + Mainboard setup. + + Please choose correct main board model here. + +config O4_IMX_NANO + bool "O4-iMX-NANO" + help + A baseboard for EV-iMX280-NANO module: + https://out4.ru/products/board/18-o4-imx-nano.html + +endchoice + +config IMX_CONFIG + default "board/out4/o4-imx6ull-nano/K4B4G1646D-BCMA.cfg" if K4B4G1646D_BCMA + default "board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg" if MT41K256M16HA_125E + +config DEFAULT_DEVICE_TREE + default "o4-imx-nano" if O4_IMX_NANO + +endif diff --git a/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg b/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg new file mode 100644 index 0000000000..6f823a7272 --- /dev/null +++ b/board/out4/o4-imx6ull-nano/MT41K256M16HA-125E.cfg @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2016 Freescale Semiconductor, Inc. +// Copyright (C) 2021 Oleh Kravchenko + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 +BOOT_FROM sd + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +/* Micron MT41K256M16HA-125:E */ +DATA 4 0x020e04b4 0x000c0000 +DATA 4 0x020e04ac 0x00000000 +DATA 4 0x020e027c 0x00000030 +DATA 4 0x020e0250 0x00000030 +DATA 4 0x020e024c 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e0288 0x000c0030 +DATA 4 0x020e0270 0x00000000 +DATA 4 0x020e0260 0x00000030 +DATA 4 0x020e0264 0x00000030 +DATA 4 0x020e04a0 0x00000030 +DATA 4 0x020e0494 0x00020000 +DATA 4 0x020e0280 0x00000030 +DATA 4 0x020e0284 0x00000030 +DATA 4 0x020e04b0 0x00020000 +DATA 4 0x020e0498 0x00000030 +DATA 4 0x020e04a4 0x00000030 +DATA 4 0x020e0244 0x00000030 +DATA 4 0x020e0248 0x00000030 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x0005000b +DATA 4 0x021b083c 0x01400144 +DATA 4 0x021b0848 0x4040343a +DATA 4 0x021b0850 0x4040342a +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b08c0 0x00944009 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x1b333030 +DATA 4 0x021b000c 0x676b52f2 +DATA 4 0x021b0010 0x91eb0b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00211740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0x84180000 +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b001c 0x02008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x15108030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00007800 +DATA 4 0x021b0818 0x00000227 +DATA 4 0x021b0004 0x0002552d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/out4/o4-imx6ull-nano/Makefile b/board/out4/o4-imx6ull-nano/Makefile new file mode 100644 index 0000000000..a3f4646d9e --- /dev/null +++ b/board/out4/o4-imx6ull-nano/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2021 Oleh Kravchenko + +obj-y := o4-imx6ull-nano.o diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c new file mode 100644 index 0000000000..fec1755c32 --- /dev/null +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +static int setup_fec_clock(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC) && !IS_ENABLED(CONFIG_CLK_IMX6Q)) { + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + return ret; + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + } + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return setup_fec_clock(); +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_CMD_BMODE)) + add_board_boot_modes(NULL); + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + const char *model; + + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (model) + env_set("board_name", model); + } + + if (is_boot_from_usb()) { + env_set("bootcmd", "run bootcmd_mfg"); + env_set("bootdelay", "0"); + } + + return 0; +} diff --git a/configs/o4-imx6ull-nano_defconfig b/configs/o4-imx6ull-nano_defconfig new file mode 100644 index 0000000000..906a3afe5d --- /dev/null +++ b/configs/o4-imx6ull-nano_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARCH_MX6=y +CONFIG_ARM=y +CONFIG_DEFAULT_DEVICE_TREE="o4-imx-nano" +CONFIG_HUSH_PARSER=y +CONFIG_IMX_MODULE_FUSE=y +CONFIG_MX6ULL=y +CONFIG_O4_IMX_NANO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_O4_IMX6ULL_NANO=y + +# CONFIG_K4B4G1646D_BCMA is not set +CONFIG_MT41K256M16HA_125E=y + +# Device Tree +CONFIG_OF_CONTROL=y +CONFIG_OF_LIBFDT_OVERLAY=y + +# Environment +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + +# Clock driver for imx6ull is not implemented +# CONFIG_CLK_IMX6Q=y + +# Thermal +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y + +# Serial +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y + +# eMMC support +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUPPORT_EMMC_RPMB=y + +# GPIO support +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y + +# USB support +CONFIG_CI_UDC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y + +# Fastboot support +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_USB_FUNCTION_FASTBOOT=y + +# Ethernet support +CONFIG_CMD_DHCP=y +CONFIG_CMD_MDIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_FEC_MXC_MDIO_BASE=0x020b4000 +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_MII=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y + +# I2C +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y + +# Watchdog support is broken +# CONFIG_CMD_WDT=y +# CONFIG_IMX_WATCHDOG=y +# CONFIG_SYSRESET_WATCHDOG=y +# CONFIG_WATCHDOG_RESET_DISABLE=y +# CONFIG_WDT=y + +# VBUS +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y + +# misc +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_PART=y diff --git a/include/configs/o4-imx6ull-nano.h b/include/configs/o4-imx6ull-nano.h new file mode 100644 index 0000000000..b9746b9b1c --- /dev/null +++ b/include/configs/o4-imx6ull-nano.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (C) 2021 Oleh Kravchenko */ + +#ifndef __O4_IMX6ULL_NANO_CONFIG_H +#define __O4_IMX6ULL_NANO_CONFIG_H + +#include "mx6_common.h" + +#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#if IS_ENABLED(CONFIG_CMD_USB) +# define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif /* CONFIG_CMD_USB */ + +#if IS_ENABLED(CONFIG_FEC_MXC) +# define CONFIG_FEC_XCV_TYPE RMII +#endif /* CONFIG_FEC_MXC */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "mmcargs=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcpart} console=ttymxc0,${baudrate} panic=30\0" \ + "mmcboot=run mmcargs && ext4load mmc ${mmcdev}:${mmcpart} $loadaddr /boot/zImage && bootz $loadaddr - $fdtcontroladdr\0" \ + "bootcmd=run mmcboot\0" \ + "bootcmd_mfg=fastboot usb 0\0" + +#endif /* __O4_IMX6ULL_NANO_CONFIG_H */ From 1180baec98147e05a8b3b36199ae22010a4d4fe7 Mon Sep 17 00:00:00 2001 From: Oleh Kravchenko Date: Sat, 15 May 2021 00:18:33 +0300 Subject: [PATCH 34/42] Add EV-iMX280-NANO-X-MB board A simple prototyping board with one microSD port, one Ethernet port, 2 USB ports, I2C, SPI, GPIO, and UART interfaces. Signed-off-by: Oleh Kravchenko Cc: Stefano Babic --- MAINTAINERS | 2 + arch/arm/dts/Makefile | 3 + arch/arm/dts/ev-imx280-nano-x-mb.dts | 109 +++++++++++++++++++ board/out4/o4-imx6ull-nano/Kconfig | 7 ++ board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c | 20 ++-- configs/ev-imx280-nano-x-mb_defconfig | 91 ++++++++++++++++ 6 files changed, 223 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/ev-imx280-nano-x-mb.dts create mode 100644 configs/ev-imx280-nano-x-mb_defconfig diff --git a/MAINTAINERS b/MAINTAINERS index 875eb5dfa4..2accd1fb83 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -923,9 +923,11 @@ OUT4-IMX6ULL-NANO BOARD M: Oleh Kravchenko S: Maintained T: git https://github.com/Oleh-Kravchenko/u-boot-out4.git +F: arch/arm/dts/ev-imx280-nano-x-mb.dts F: arch/arm/dts/o4-imx-nano.dts F: arch/arm/dts/o4-imx6ull-nano.dtsi F: board/out4 +F: configs/ev-imx280-nano-x-mb_defconfig F: configs/o4-imx6ull-nano_defconfig F: include/configs/o4-imx6ull-nano.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b944778c1a..d29844e765 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -822,6 +822,9 @@ dtb-$(CONFIG_ARCH_MX6) += \ dtb-$(CONFIG_O4_IMX_NANO) += \ o4-imx-nano.dtb +dtb-$(CONFIG_EV_IMX280_NANO_X_MB) += \ + ev-imx280-nano-x-mb.dtb + dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ imx7-cm.dtb \ diff --git a/arch/arm/dts/ev-imx280-nano-x-mb.dts b/arch/arm/dts/ev-imx280-nano-x-mb.dts new file mode 100644 index 0000000000..7aec076af3 --- /dev/null +++ b/arch/arm/dts/ev-imx280-nano-x-mb.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko + +/dts-v1/; + +#include "o4-imx6ull-nano.dtsi" + +/ { + model = "EV-iMX280-NANO-X-MB"; + compatible = "evodbg,ev-imx280-nano-x-mb", + "out4,o4-imx6ull-nano", + "fsl,imx6ull"; + + aliases { + mmc1 = &usdhc1; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */ + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usdhc1 { + bus-width = <4>; + no-1-8-v; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; + status = "okay"; + wakeup-source; +}; + +&fec1 { + phy-handle = <&phy0>; + phy-mode = "rmii"; + phy-reset-duration = <250>; + phy-reset-post-delay = <100>; + phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_fec1 &pinctrl_mdio>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_phy0_irq>; + pinctrl-names = "default"; + reg = <0>; + }; + }; +}; + +&usbotg1 { + dr_mode = "otg"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig index c2497d521f..e2ab80b6d4 100644 --- a/board/out4/o4-imx6ull-nano/Kconfig +++ b/board/out4/o4-imx6ull-nano/Kconfig @@ -45,6 +45,12 @@ config O4_IMX_NANO A baseboard for EV-iMX280-NANO module: https://out4.ru/products/board/18-o4-imx-nano.html +config EV_IMX280_NANO_X_MB + bool "EV-IMX280-NANO-X-MB" + help + A simple baseboard for EV-iMX280-NANO module: + http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html + endchoice config IMX_CONFIG @@ -53,5 +59,6 @@ config IMX_CONFIG config DEFAULT_DEVICE_TREE default "o4-imx-nano" if O4_IMX_NANO + default "ev-imx280-nano-x-mb" if EV_IMX280_NANO_X_MB endif diff --git a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c index fec1755c32..edb200e9e5 100644 --- a/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c +++ b/board/out4/o4-imx6ull-nano/o4-imx6ull-nano.c @@ -39,16 +39,18 @@ static int setup_fec_clock(void) if (ret) return ret; - /* - * Use 50M anatop loopback REF_CLK2 for ENET2, - * clear gpr1[14], set gpr1[18]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, - IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + if (!IS_ENABLED(CONFIG_EV_IMX280_NANO_X_MB)) { + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); - ret = enable_fec_anatop_clock(1, ENET_50MHZ); - if (ret) - return ret; + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + } enable_enet_clk(1); } diff --git a/configs/ev-imx280-nano-x-mb_defconfig b/configs/ev-imx280-nano-x-mb_defconfig new file mode 100644 index 0000000000..b06aedef2a --- /dev/null +++ b/configs/ev-imx280-nano-x-mb_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARCH_MX6=y +CONFIG_ARM=y +CONFIG_DEFAULT_DEVICE_TREE="ev-imx280-nano-x-mb" +CONFIG_EV_IMX280_NANO_X_MB=y +CONFIG_HUSH_PARSER=y +CONFIG_IMX_MODULE_FUSE=y +CONFIG_MX6ULL=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_O4_IMX6ULL_NANO=y + +CONFIG_K4B4G1646D_BCMA=y +# CONFIG_MT41K256M16HA_125E is not set + +# Device Tree +CONFIG_OF_CONTROL=y +CONFIG_OF_LIBFDT_OVERLAY=y + +# Environment +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + +# Clock driver for imx6ull is not implemented +# CONFIG_CLK_IMX6Q=y + +# Thermal +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y + +# Serial +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y + +# eMMC support +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUPPORT_EMMC_RPMB=y + +# GPIO support +CONFIG_CMD_GPIO=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y + +# USB support +CONFIG_CI_UDC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_DM_USB=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y + +# Fastboot support +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_USB_FUNCTION_FASTBOOT=y + +# Ethernet support +CONFIG_CMD_DHCP=y +CONFIG_CMD_MDIO=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y + +# Watchdog support is broken +# CONFIG_CMD_WDT=y +# CONFIG_IMX_WATCHDOG=y +# CONFIG_SYSRESET_WATCHDOG=y +# CONFIG_WATCHDOG_RESET_DISABLE=y +# CONFIG_WDT=y + +# misc +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_PART=y From d9a7f1a9131372e852407e4a5c6e812ce37456e4 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Mon, 3 May 2021 10:02:10 +0200 Subject: [PATCH 35/42] arm: imx: imx8mm: clock: make debug output more descriptive Clock initialization functionality has ambitious debug messages, which are printed out when failures are triggered during execution: - Separate frequency table lookup functions have the the same output that makes it impossible to understand which function failed and produced the output - PLL decoding routine has a generic debug statement printed, which does not state the actual value failed to be found Extend the output for both cases with prefixing table lookup functions output with function name, and report the failed value in PLL decoding routine. Signed-off-by: Andrey Zhizhikin Cc: Stefano Babic Cc: Fabio Estevam Cc: "NXP i.MX U-Boot Team" Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 65d476e037..6f45d74c6b 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -72,7 +72,7 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) } if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) { - printf("No matched freq table %u\n", freq); + printf("%s: No matched freq table %u\n", __func__, freq); return -EINVAL; } @@ -148,7 +148,7 @@ void dram_enable_bypass(ulong clk_val) } if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) { - printf("No matched freq table %lu\n", clk_val); + printf("%s: No matched freq table %lu\n", __func__, clk_val); return; } @@ -646,7 +646,7 @@ static u32 decode_fracpll(enum clk_root_src frac_pll) pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1); break; default: - printf("Not supported\n"); + printf("Unsupported clk_root_src %d\n", frac_pll); return 0; } From cd18f1e6e6144bd72110b07144e77f9e84b2e7c8 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 3 May 2021 11:21:27 -0700 Subject: [PATCH 36/42] imx: ventana: enable dm support for PCI and FEC ethernet Enable driver model support for FEC ethernet which allows us to remove the iomux and board_eth_init function. Replace the toggling of the ethernet phy reset with dt configuration. Enable driver model support for PCI which allows us to remove the eth1000_initialize() call. Additionally enable PCI_INIT_R to scan for PCI devices on init such as the e1000 that is present on the GW552x. Convert board_pci_fixup to use dm callback and remove pcidisable env variable which is not supported for DM_PCI and thus leave PCI always enabled during init. Signed-off-by: Tim Harvey --- arch/arm/dts/imx6qdl-gw51xx.dtsi | 2 + arch/arm/dts/imx6qdl-gw52xx.dtsi | 2 + arch/arm/dts/imx6qdl-gw53xx.dtsi | 3 + arch/arm/dts/imx6qdl-gw54xx.dtsi | 3 + arch/arm/dts/imx6qdl-gw560x.dtsi | 2 + arch/arm/dts/imx6qdl-gw5903.dtsi | 3 + arch/arm/dts/imx6qdl-gw5904.dtsi | 3 + arch/arm/dts/imx6qdl-gw5907.dtsi | 2 + arch/arm/dts/imx6qdl-gw5910.dtsi | 3 + arch/arm/dts/imx6qdl-gw5912.dtsi | 4 + arch/arm/dts/imx6qdl-gw5913.dtsi | 3 + board/gateworks/gw_ventana/common.h | 1 - board/gateworks/gw_ventana/gw_ventana.c | 99 ++++--------------------- configs/gwventana_emmc_defconfig | 5 ++ configs/gwventana_gw5904_defconfig | 5 ++ configs/gwventana_nand_defconfig | 5 ++ include/configs/gw_ventana.h | 10 --- 17 files changed, 61 insertions(+), 94 deletions(-) diff --git a/arch/arm/dts/imx6qdl-gw51xx.dtsi b/arch/arm/dts/imx6qdl-gw51xx.dtsi index 2a21c6731e..7e28463084 100644 --- a/arch/arm/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi @@ -129,6 +129,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi index 6eedf8d40d..f1d9ba1fac 100644 --- a/arch/arm/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi @@ -195,6 +195,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi index 9deec7e352..172a45ba17 100644 --- a/arch/arm/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -188,6 +188,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; @@ -597,6 +599,7 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 >; }; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index a30ba4848e..e09fad6068 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -225,6 +225,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; @@ -675,6 +677,7 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 >; }; diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi index 0786b0d546..bfe65fd3c0 100644 --- a/arch/arm/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -279,6 +279,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5903.dtsi b/arch/arm/dts/imx6qdl-gw5903.dtsi index 78f9ec90b7..6ebf6aef2f 100644 --- a/arch/arm/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/dts/imx6qdl-gw5903.dtsi @@ -223,6 +223,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi index 5b7bd56932..9adbd728dc 100644 --- a/arch/arm/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -200,6 +200,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; fixed-link { diff --git a/arch/arm/dts/imx6qdl-gw5907.dtsi b/arch/arm/dts/imx6qdl-gw5907.dtsi index c8b29246b7..58f73a141e 100644 --- a/arch/arm/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/dts/imx6qdl-gw5907.dtsi @@ -131,6 +131,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5910.dtsi b/arch/arm/dts/imx6qdl-gw5910.dtsi index 248e077a56..446c1043a7 100644 --- a/arch/arm/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/dts/imx6qdl-gw5910.dtsi @@ -146,6 +146,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi index 7593872c07..88234a6f13 100644 --- a/arch/arm/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/dts/imx6qdl-gw5912.dtsi @@ -141,6 +141,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; @@ -426,6 +429,7 @@ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 >; }; diff --git a/arch/arm/dts/imx6qdl-gw5913.dtsi b/arch/arm/dts/imx6qdl-gw5913.dtsi index 9fae4cccd7..f4c2b2189f 100644 --- a/arch/arm/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/dts/imx6qdl-gw5913.dtsi @@ -121,6 +121,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index d73850c5b9..813f7d9f56 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -11,7 +11,6 @@ #include "ventana_eeprom.h" /* GPIO's common to all baseboards */ -#define GP_PHY_RST IMX_GPIO_NR(1, 30) #define GP_RS232_EN IMX_GPIO_NR(2, 11) #define GP_MSATA_SEL IMX_GPIO_NR(2, 8) diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 5237f2dac4..1ed9c1a39f 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include #include @@ -54,42 +53,6 @@ DECLARE_GLOBAL_DATA_PTR; struct ventana_board_info ventana_info; static int board_type; -/* ENET */ -static iomux_v3_cfg_t const enet_pads[] = { - IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), - IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | - MUX_PAD_CTRL(ENET_PAD_CTRL)), - /* PHY nRST */ - IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), -}; - -static void setup_iomux_enet(int gpio) -{ - SETUP_IOMUX_PADS(enet_pads); - - /* toggle PHY_RST# */ - gpio_request(gpio, "phy_rst#"); - gpio_direction_output(gpio, 0); - mdelay(10); - gpio_set_value(gpio, 1); - mdelay(100); -} - #ifdef CONFIG_USB_EHCI_MX6 /* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */ int board_ehci_hcd_init(int port) @@ -195,40 +158,7 @@ int mv88e61xx_hw_reset(struct phy_device *phydev) } #endif // CONFIG_MV88E61XX_SWITCH -int board_eth_init(struct bd_info *bis) -{ -#ifdef CONFIG_FEC_MXC - struct ventana_board_info *info = &ventana_info; - - if (test_bit(EECONFIG_ETH0, info->config)) { - setup_iomux_enet(GP_PHY_RST); - cpu_eth_init(bis); - } -#endif - -#ifdef CONFIG_E1000 - e1000_initialize(bis); -#endif - -#ifdef CONFIG_CI_UDC - /* For otg ethernet*/ - usb_eth_initialize(bis); -#endif - - /* default to the first detected enet dev */ - if (!env_get("ethprime")) { - struct eth_device *dev = eth_get_dev_by_index(0); - if (dev) { - env_set("ethprime", dev->name); - printf("set ethprime to %s\n", env_get("ethprime")); - } - } - - return 0; -} - #if defined(CONFIG_VIDEO_IPUV3) - static void enable_hdmi(struct display_info_t const *dev) { imx_enable_hdmi_phy(); @@ -427,7 +357,6 @@ int power_init_board(void) return 0; } -#if defined(CONFIG_CMD_PCI) int imx6_pcie_toggle_reset(void) { if (board_type < GW_UNKNOWN) { @@ -448,6 +377,7 @@ int imx6_pcie_toggle_reset(void) #define MAX_PCI_DEVS 32 struct pci_dev { pci_dev_t devfn; + struct udevice *dev; unsigned short vendor; unsigned short device; unsigned short class; @@ -458,18 +388,21 @@ struct pci_dev pci_devs[MAX_PCI_DEVS]; int pci_devno; int pci_bridgeno; -void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, - unsigned short vendor, unsigned short device, - unsigned short class) +void board_pci_fixup_dev(struct udevice *bus, struct udevice *udev) { - int i; - u32 dw; + struct pci_child_plat *pdata = dev_get_parent_plat(udev); struct pci_dev *pdev = &pci_devs[pci_devno++]; + unsigned short vendor = pdata->vendor; + unsigned short device = pdata->device; + unsigned int class = pdata->class; + pci_dev_t dev = dm_pci_get_bdf(udev); + int i; debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); /* store array of devs for later use in device-tree fixup */ + pdev->dev = udev; pdev->devfn = dev; pdev->vendor = vendor; pdev->device = device; @@ -496,19 +429,19 @@ void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, if (vendor == PCI_VENDOR_ID_PLX && (device & 0xfff0) == 0x8600 && PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { + ulong val; debug("configuring PLX 860X downstream PERST#\n"); - pci_hose_read_config_dword(hose, dev, 0x62c, &dw); - dw |= 0xaaa8; /* GPIO1-7 outputs */ - pci_hose_write_config_dword(hose, dev, 0x62c, dw); + pci_bus_read_config(bus, dev, 0x62c, &val, PCI_SIZE_32); + val |= 0xaaa8; /* GPIO1-7 outputs */ + pci_bus_write_config(bus, dev, 0x62c, val, PCI_SIZE_32); - pci_hose_read_config_dword(hose, dev, 0x644, &dw); - dw |= 0xfe; /* GPIO1-7 output high */ - pci_hose_write_config_dword(hose, dev, 0x644, dw); + pci_bus_read_config(bus, dev, 0x644, &val, PCI_SIZE_32); + val |= 0xfe; /* GPIO1-7 output high */ + pci_bus_write_config(bus, dev, 0x644, val, PCI_SIZE_32); mdelay(100); } } -#endif /* CONFIG_CMD_PCI */ #ifdef CONFIG_SERIAL_TAG /* diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 97b39b6e72..6e3aebbf1b 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_FIT_IMAGE_TINY=y @@ -85,9 +86,13 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_DM_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index ce40a4d85b..77e65f2236 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_FIT_IMAGE_TINY=y @@ -89,9 +90,13 @@ CONFIG_MV88E61XX_SWITCH=y CONFIG_MV88E61XX_CPU_PORT=5 CONFIG_MV88E61XX_PHY_PORTS=0xf CONFIG_MV88E61XX_FIXED_PORTS=0x0 +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_DM_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index a4d85956a0..db31d97f3d 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -34,6 +34,7 @@ CONFIG_USE_PREBOOT=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_MISC_INIT_R=y +CONFIG_PCI_INIT_R=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_STACK_R=y CONFIG_SPL_FIT_IMAGE_TINY=y @@ -91,9 +92,13 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y CONFIG_NAND_MXS_DT=y CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PCI=y +CONFIG_DM_PCI=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 5754b6aef0..4f2f323b77 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -65,8 +65,6 @@ * PCI express */ #ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCI_FIXUP_DEV #define CONFIG_PCIE_IMX #endif @@ -82,13 +80,6 @@ /* Various command support */ -/* Ethernet support */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_ARP_TIMEOUT 200UL - /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) @@ -129,7 +120,6 @@ #define CONFIG_SERVERIP 192.168.1.146 #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "pcidisable=1\0" \ "splashpos=m,m\0" \ "usb_pgood_delay=2000\0" \ "console=ttymxc1\0" \ From b8916306d1061b254d066ccaa4c797896c96a2c1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 27 May 2021 18:43:06 -0300 Subject: [PATCH 37/42] pico-imx6: README: Fix the boot mode settings URL The original URL that explains the boot mode setting is no longer valid. Update to the new one. Signed-off-by: Fabio Estevam --- board/technexion/pico-imx6/README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/technexion/pico-imx6/README b/board/technexion/pico-imx6/README index f1e84bfe82..f497086502 100644 --- a/board/technexion/pico-imx6/README +++ b/board/technexion/pico-imx6/README @@ -20,7 +20,7 @@ If the eMMC has already a U-Boot flashed then the user can go to step 2 below in order to update U-Boot. Put pico board in USB download mode (Refer to the following link for details: -https://www.technexion.com/support/knowledgebase/boot-configuration-settings-for-pico-baseboards/). +https://developer.technexion.com/docs/pico-evaluation-kit-boot-mode-settings ) Connect a USB to serial adapter between the host PC and pico. From 6ac4d4480663ca43f64a0ae1e49af5455bcff7aa Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Mon, 3 May 2021 09:59:17 +0200 Subject: [PATCH 38/42] arm: imx: imx8mm: correct unrecognized fracpll frequency Frequency requested by ddrphy_init_set_dfi_clk from fracpll uses MHZ() macro, which expands the value provided to the Hz range without taking into account the precise Hz setting. This causes the frequency of 266 MHz not ot be found in the imx8mm_fracpll_tbl, since it is entered there with a precise Hz value. This in turn causes the boot hang in SPL, as proper DDR fracpll frequency cannot be determined. Correct the value in imx8mm_fracpll_tbl to match the one expanded by MHZ(266) macro, rounding it down to MHz range only. Signed-off-by: Andrey Zhizhikin Cc: Stefano Babic Cc: Fabio Estevam Cc: "NXP i.MX U-Boot Team" Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Fixes: 825ab6b406 ("driver: ddr: Refine the ddr init driver on imx8m") Reviewed-by: Fabio Estevam --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 6f45d74c6b..f8e4ec0d90 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(600000000U, 300, 3, 2, 0), PLL_1443X_RATE(594000000U, 99, 1, 2, 0), PLL_1443X_RATE(400000000U, 300, 9, 1, 0), - PLL_1443X_RATE(266666667U, 400, 9, 2, 0), + PLL_1443X_RATE(266000000U, 400, 9, 2, 0), PLL_1443X_RATE(167000000U, 334, 3, 4, 0), PLL_1443X_RATE(100000000U, 300, 9, 3, 0), }; From fe133eb192a8a55813a4dc5ec72ecf45ba74f65e Mon Sep 17 00:00:00 2001 From: Oliver Graute Date: Mon, 31 May 2021 15:50:40 +0200 Subject: [PATCH 39/42] imx: support for conga-QMX8 board Add i.MX8QM qmx8 congatec board support U-Boot 2021.07-rc3-00528-gc9a966d9dd (May 31 2021 - 15:21:25 +0200) CPU: NXP i.MX8QM RevB A53 at 1200 MHz Model: Congatec QMX8 Qseven series Board: conga-QMX8 Build: SCFW 494c97f3, SECO-FW d63fdb21, ATF 09c5cc9 Boot: SD2 DRAM: 6 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 switch to partitions #0, OK mmc2 is current device Net: Error: ethernet@5b040000 address not set. No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Simon Glass Cc: Ye Li Cc: uboot-imx --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8qm-cgtqmx8.dts | 404 ++++++++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 7 + board/congatec/cgtqmx8/Kconfig | 14 + board/congatec/cgtqmx8/MAINTAINERS | 7 + board/congatec/cgtqmx8/Makefile | 11 + board/congatec/cgtqmx8/cgtqmx8.c | 460 ++++++++++++++++++++++++++++ board/congatec/cgtqmx8/imximage.cfg | 21 ++ board/congatec/cgtqmx8/spl.c | 77 +++++ board/congatec/common/Kconfig | 48 +++ board/congatec/common/Makefile | 23 ++ board/congatec/common/mmc.c | 49 +++ configs/cgtqmx8_defconfig | 86 ++++++ doc/board/congatec/cgtqmx8.rst | 70 +++++ doc/board/congatec/index.rst | 9 + doc/board/index.rst | 1 + include/configs/cgtqmx8.h | 181 +++++++++++ 17 files changed, 1469 insertions(+) create mode 100644 arch/arm/dts/imx8qm-cgtqmx8.dts create mode 100644 board/congatec/cgtqmx8/Kconfig create mode 100644 board/congatec/cgtqmx8/MAINTAINERS create mode 100644 board/congatec/cgtqmx8/Makefile create mode 100644 board/congatec/cgtqmx8/cgtqmx8.c create mode 100644 board/congatec/cgtqmx8/imximage.cfg create mode 100644 board/congatec/cgtqmx8/spl.c create mode 100644 board/congatec/common/Kconfig create mode 100644 board/congatec/common/Makefile create mode 100644 board/congatec/common/mmc.c create mode 100644 configs/cgtqmx8_defconfig create mode 100644 doc/board/congatec/cgtqmx8.rst create mode 100644 doc/board/congatec/index.rst create mode 100644 include/configs/cgtqmx8.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d29844e765..8889d5b1ca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -842,6 +842,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ + imx8qm-cgtqmx8.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts new file mode 100644 index 0000000000..555c357f6f --- /dev/null +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Copyright 2017 congatec AG + * Copyright (C) 2019 Oliver Graute + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Congatec QMX8 Qseven series"; + compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3000>; + }; + + reg_usdhc3_vmmc: usdhc3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + rtc_ext: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + /* power-domains = <&pd_mclk_out0>; */ + + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-qmx8 { + + pinctrl_hog: hoggrp{ + fsl,pins = < + SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021 + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021 + SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021 + SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021 + SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* Q7 connector */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc3_vmmc>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4e76612d05..71221d8d06 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -86,6 +86,12 @@ config TARGET_IMX8QM_MEK select BOARD_LATE_INIT select IMX8QM +config TARGET_CONGA_QMX8 + bool "Support congatec conga-QMX8 board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QM_ROM7720_A1 bool "Support i.MX8QM ROM-7720-A1" select BOARD_LATE_INIT @@ -101,6 +107,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" +source "board/congatec/cgtqmx8/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/board/congatec/cgtqmx8/Kconfig b/board/congatec/cgtqmx8/Kconfig new file mode 100644 index 0000000000..7273039261 --- /dev/null +++ b/board/congatec/cgtqmx8/Kconfig @@ -0,0 +1,14 @@ +if TARGET_CONGA_QMX8 + +config SYS_BOARD + default "cgtqmx8" + +config SYS_VENDOR + default "congatec" + +config SYS_CONFIG_NAME + default "cgtqmx8" + +source "board/congatec/common/Kconfig" + +endif diff --git a/board/congatec/cgtqmx8/MAINTAINERS b/board/congatec/cgtqmx8/MAINTAINERS new file mode 100644 index 0000000000..53bc0f93b7 --- /dev/null +++ b/board/congatec/cgtqmx8/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8QM CGTQMX8 BOARD +M: Oliver Graute +S: Maintained +F: board/congatec/cgtqmx8/ +F: arch/arm/dts/imx8qm-cgtqmx8.dts +F: include/configs/cgtqmx8.h +F: configs/cgtqmx8_defconfig diff --git a/board/congatec/cgtqmx8/Makefile b/board/congatec/cgtqmx8/Makefile new file mode 100644 index 0000000000..4b59dbb6bc --- /dev/null +++ b/board/congatec/cgtqmx8/Makefile @@ -0,0 +1,11 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cgtqmx8.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c new file mode 100644 index 0000000000..fb0cf09138 --- /dev/null +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -0,0 +1,460 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 congatec AG + * Copyright (C) 2019 Oliver Graute + */ +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +void board_late_mmc_env_init(void); +void init_clk_usdhc(u32 index); +int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + /* sc_ipc_t ipcHndl = 0; */ + sc_err_t scierr = 0; + + /* When start u-boot in XEN VM, directly return */ + /* if (IS_ENABLED(CONFIG_XEN)) */ + /* return 0; */ + + /* ipcHndl = gd->arch.ipc_channel_handle; */ + + /* Power up UART0, this is very early while power domain is not working */ + scierr = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); + if (scierr != SC_ERR_NONE) + return 0; + + /* Set UART0 clock root to 80 MHz */ + sc_pm_clock_rate_t rate = 80000000; + + scierr = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); + if (scierr != SC_ERR_NONE) + return 0; + + /* Enable UART0 clock root */ + scierr = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); + if (scierr != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_FSL_ESDHC_IMX) + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc1_sd[] = { + SC_P_USDHC1_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA6 | MUX_MODE_ALT(2) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_DATA7 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_VSELECT | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + struct power_domain pd; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 (onboard eMMC) USDHC1 + * mmc1 (external SD card) USDHC2 + * mmc2 (onboard µSD) USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + /* onboard eMMC */ + if (!imx8_power_domain_lookup_name("conn_sdhc0", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + /* external SD card */ + if (!imx8_power_domain_lookup_name("conn_sdhc1", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc1_sd, ARRAY_SIZE(usdhc1_sd)); + init_clk_usdhc(1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC1_CD_GPIO, "sd1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + break; + case 2: + /* onboard µSD */ + if (!imx8_power_domain_lookup_name("conn_sdhc2", &pd)) + power_domain_on(&pd); + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +#if (IS_ENABLED(CONFIG_FEC_MXC)) + +#include + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); +} + +static void enet_device_phy_reset(void) +{ + gpio_set_value(FEC0_RESET, 0); + udelay(50); + gpio_set_value(FEC0_RESET, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(struct bd_info *bis) +{ + setup_iomux_fec(); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +static int setup_fec(void) +{ + /* Reset ENET PHY */ + enet_device_phy_reset(); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define BKL_ENABLE IMX_GPIO_NR(1, 7) + +static iomux_cfg_t board_gpios[] = { + SC_P_LVDS0_I2C0_SCL | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_LVDS0_I2C0_SDA | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ESAI1_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + /* enable LVDS */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable backlight */ + gpio_request(BKL_ENABLE, "bkl_enable"); + gpio_direction_output(BKL_ENABLE, 1); + + /* ethernet reset */ + gpio_request(FEC0_RESET, "enet0_reset"); + gpio_direction_output(FEC0_RESET, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: conga-QMX8\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + +#if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); +#endif + + return 0; +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +extern u32 _end_ofs; +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "QMX8"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#ifdef IMX_LOAD_HDMI_FIMRWARE + char *end_of_uboot; + char command[256]; + + end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + + fdt_totalsize(gd->fdt_blob)); + end_of_uboot += 9; + + /* load hdmitxfw.bin and hdmirxfw.bin*/ + memcpy(IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, + IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE); + + sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR); + run_command(command, 0); + + sprintf(command, "hdprx load 0x%x", + IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE); + run_command(command, 0); +#endif + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +/* Only Enable USB3 resources currently */ +int board_usb_init(int index, enum usb_init_type init) +{ + return 0; +} diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg new file mode 100644 index 0000000000..e324c7ca37 --- /dev/null +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-val-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/congatec/cgtqmx8/spl.c b/board/congatec/cgtqmx8/spl.c new file mode 100644 index 0000000000..2a5d4c1bcd --- /dev/null +++ b/board/congatec/cgtqmx8/spl.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int offset; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd"); + while (offset != -FDT_ERR_NOTFOUND) { + lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset), + NULL, true); + offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset, + "nxp,imx8-pd"); + } + + uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +#if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/board/congatec/common/Kconfig b/board/congatec/common/Kconfig new file mode 100644 index 0000000000..5c205bd830 --- /dev/null +++ b/board/congatec/common/Kconfig @@ -0,0 +1,48 @@ +if !ARCH_IMX8M && !ARCH_IMX8 + +config CHAIN_OF_TRUST + depends on !FIT_SIGNATURE && SECURE_BOOT + imply CMD_BLOB + imply CMD_HASH if ARM + select FSL_CAAM + select SPL_BOARD_INIT if (ARM && SPL) + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL + select ENV_IS_NOWHERE + select CMD_EXT4 if ARM + select CMD_EXT4_WRITE if ARM + bool + default y + +config CMD_ESBC_VALIDATE + bool "Enable the 'esbc_validate' and 'esbc_halt' commands" + default y if CHAIN_OF_TRUST + help + This option enables two commands used for secure booting: + + esbc_validate - validate signature using RSA verification + esbc_halt - put the core in spin loop (Secure Boot Only) + +endif + +config VOL_MONITOR_LTC3882_READ + depends on VID + bool "Enable the LTC3882 voltage monitor read" + default n + help + This option enables LTC3882 voltage monitor read + functionality. It is used by common VID driver. + +config VOL_MONITOR_LTC3882_SET + depends on VID + bool "Enable the LTC3882 voltage monitor set" + default n + help + This option enables LTC3882 voltage monitor set + functionality. It is used by common VID driver. + +config USB_TCPC + bool "USB Typec port controller simple driver" + default n + help + Enable USB type-c port controller (TCPC) driver diff --git a/board/congatec/common/Makefile b/board/congatec/common/Makefile new file mode 100644 index 0000000000..d4ddfbf971 --- /dev/null +++ b/board/congatec/common/Makefile @@ -0,0 +1,23 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL +# necessary to create built-in.o +obj- := __dummy__.o +else + +obj-y += mmc.o + +endif diff --git a/board/congatec/common/mmc.c b/board/congatec/common/mmc.c new file mode 100644 index 0000000000..bb7a3d4a9a --- /dev/null +++ b/board/congatec/common/mmc.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + */ +#include +#include +#include +#include +#include +#include +#include + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str) && (strcmp(autodetect_str, "yes") == 0)) + return 1; + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig new file mode 100644 index 0000000000..238e421601 --- /dev/null +++ b/configs/cgtqmx8_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_CONGA_QMX8=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_BOOTAUX=y +CONFIG_LOG=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_HUSH_PARSER=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FUSE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-cgtqmx8" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set +CONFIG_SYS_MMCSD_FS_BOOT_PARTITION=0 +CONFIG_SYS_MMC_ENV_PART=0 +CONFIG_SYS_MMC_ENV_DEV=1 diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst new file mode 100644 index 0000000000..bccdef2f16 --- /dev/null +++ b/doc/board/congatec/cgtqmx8.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for the Congatec conga-QMX8 board +======================================== + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Build imx-mkimage +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ cd imx-atf/ + $ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga + $ make PLAT=imx8qm bl31 + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin + $ chmod +x imx-sc-firmware-1.1.bin + $ ./imx-sc-firmware-1.1.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin + $ chmod +x firmware-imx-8.0.bin + $ ./firmware-imx-8.0.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +.. code-block:: bash + + $ dd if=imx-sc-firmware-1.1.bin of=imx-sc-firmware-1.1.tar.bz2 bs=37185 skip=1 + $ tar -xf imx-sc-firmware-1.1.tar.bz2 + $ cp imx-sc-firmware-1.1/mx8qx-val-scfw-tcm.bin $(builddir) + + $ dd if=firmware-imx-8.0.bin of=firmware-imx-8.0.tar.bz2 bs=37180 skip=1 + $ tar -xf firmware-imx-8.0.tar.bz2 + $ cp firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img $(builddir) + +Build U-Boot +------------ + +.. code-block:: bash + + $ export ATF_LOAD_ADDR=0x80000000 + $ export BL33_LOAD_ADDR=0x80020000 + $ make cgtqmx8_defconfig + $ make u-boot.bin + $ make flash.bin + +Flash the binary into the SD card +--------------------------------- + +Burn the flash.bin binary to SD card offset 32KB: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync diff --git a/doc/board/congatec/index.rst b/doc/board/congatec/index.rst new file mode 100644 index 0000000000..cc57b36b2e --- /dev/null +++ b/doc/board/congatec/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Congatec +======== + +.. toctree:: + :maxdepth: 2 + + cgtqmx8.rst diff --git a/doc/board/index.rst b/doc/board/index.rst index a70d2de19d..747511f7dd 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -11,6 +11,7 @@ Board-specific doc AndesTech/index amlogic/index atmel/index + congatec/index coreboot/index emulation/index freescale/index diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h new file mode 100644 index 0000000000..15c50279ad --- /dev/null +++ b/include/configs/cgtqmx8.h @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * Copyright 2018 congatec AG + * + */ + +#ifndef __CGTQMX8_H +#define __CGTQMX8_H + +#include +#include + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x0 +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x013E000 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00120000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_OF_EMBED +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_EARLY_INIT_F + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif +#define FEC0_RESET IMX_GPIO_NR(2, 5) +#define FEC0_PDOMAIN "conn_enet0" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83800000\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-cgt-qmx8.dtb\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} earlycon\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp rw earlycon\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_MXC_PHYADDR -1 +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC + +#endif /* __CGTQMX8_H */ From a3a0bc85c0501c2374966104b8daca6c69101625 Mon Sep 17 00:00:00 2001 From: Navin Sankar Velliangiri Date: Tue, 18 May 2021 09:03:20 +0530 Subject: [PATCH 40/42] imx: Add SeeedStudio NPI-IMX6ULL Support CPU: Freescale i.MX6ULL rev1.1 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 49C Reset cause: POR Model: Seeed NPi iMX6ULL Dev Board with NAND Board: Seeed NPi i.MX6ULL Dev Board DRAM: 512 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial@2020000 Out: serial@2020000 Err: serial@2020000 Net: FEC0 Working: - Eth0 - MMC/SD - NAND - UART 1 - USB host Signed-off-by: Navin Sankar Velliangiri Note: Changes in v2: * removed unnecessary space in imx6ull-seeed-npi-imx6ull-dev-board.dts file. * Used SZ_2M for CONFIG_SYS_MALLOC_LEN size allocation. --- arch/arm/Kconfig | 1 + arch/arm/dts/Makefile | 1 + .../imx6ull-seeed-npi-imx6ull-dev-board.dts | 19 ++ .../dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi | 24 ++ arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi | 271 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/seeed/npi_imx6ull/Kconfig | 12 + board/seeed/npi_imx6ull/MAINTAINERS | 9 + board/seeed/npi_imx6ull/Makefile | 4 + board/seeed/npi_imx6ull/README | 61 ++++ board/seeed/npi_imx6ull/npi_imx6ull.c | 114 ++++++++ board/seeed/npi_imx6ull/spl.c | 205 +++++++++++++ configs/seeed_npi_imx6ull_defconfig | 80 ++++++ include/configs/npi_imx6ull.h | 96 +++++++ 14 files changed, 908 insertions(+) create mode 100644 arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts create mode 100644 arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi create mode 100644 arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi create mode 100644 board/seeed/npi_imx6ull/Kconfig create mode 100644 board/seeed/npi_imx6ull/MAINTAINERS create mode 100644 board/seeed/npi_imx6ull/Makefile create mode 100644 board/seeed/npi_imx6ull/README create mode 100644 board/seeed/npi_imx6ull/npi_imx6ull.c create mode 100644 board/seeed/npi_imx6ull/spl.c create mode 100644 configs/seeed_npi_imx6ull_defconfig create mode 100644 include/configs/npi_imx6ull.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..3c46f3ff39 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -2008,6 +2008,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/seeed/npi_imx6ull/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8889d5b1ca..6884c4e98f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -810,6 +810,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ + imx6ull-seeed-npi-imx6ull-dev-board.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts new file mode 100644 index 0000000000..ce03ddfd21 --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-seeed-npi-imx6ull.dtsi" +#include "imx6ull-seeed-npi-imx6ull-u-boot.dtsi" + +/ { + model = "Seeed NPi iMX6ULL Dev Board with NAND"; + compatible = "seeed,imx6ull-seeed-npi-imx6ull", "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi new file mode 100644 index 0000000000..054e1aa94b --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&gpmi { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc2 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi b/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi new file mode 100644 index 0000000000..b019474dba --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +#include +#include +#include + +/ { + model = "Seeed NPi-iMX6ULL Dev Board"; + compatible = "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + user-led { + label = "User"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_uart1: uart1grp { + fsl,pin = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 0f274c41a1..23cab3932b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -453,6 +453,17 @@ config TARGET_NITROGEN6X imply USB_ETHER_SMSC95XX imply USB_HOST_ETHER +config TARGET_NPI_IMX6ULL + bool "Seeed NPI-IMX6ULL" + depends on MX6ULL + select DM + select DM_ETH + select DM_MMC + select DM_GPIO + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_OPOS6ULDEV bool "Armadeus OPOS6ULDev board" depends on MX6UL diff --git a/board/seeed/npi_imx6ull/Kconfig b/board/seeed/npi_imx6ull/Kconfig new file mode 100644 index 0000000000..5e298299a3 --- /dev/null +++ b/board/seeed/npi_imx6ull/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NPI_IMX6ULL + +config SYS_BOARD + default "npi_imx6ull" + +config SYS_VENDOR + default "seeed" + +config SYS_CONFIG_NAME + default "npi_imx6ull" + +endif diff --git a/board/seeed/npi_imx6ull/MAINTAINERS b/board/seeed/npi_imx6ull/MAINTAINERS new file mode 100644 index 0000000000..c6a915c79b --- /dev/null +++ b/board/seeed/npi_imx6ull/MAINTAINERS @@ -0,0 +1,9 @@ +NPI_IMX6ULL BOARD +M: Navin Sankar Velliangiri +S: Maintained +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi +F: arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi +F: board/seeed/npi-imx6ull/ +F: configs/seeed_npi_imx6ull_defconfig +F: include/configs/npi_imx6ull.h diff --git a/board/seeed/npi_imx6ull/Makefile b/board/seeed/npi_imx6ull/Makefile new file mode 100644 index 0000000000..93ea413517 --- /dev/null +++ b/board/seeed/npi_imx6ull/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := npi_imx6ull.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/seeed/npi_imx6ull/README b/board/seeed/npi_imx6ull/README new file mode 100644 index 0000000000..01d218a9bc --- /dev/null +++ b/board/seeed/npi_imx6ull/README @@ -0,0 +1,61 @@ +How to use U-BOOT on SeeedStudio NPI-IMX6ULL Single Board Computer +------------------------------------------------------------------ + +- Configure and build U-Boot for NPI-IMX6ULL: + + $ export ARCH=arm + $ export CROSS_COMPILE=arm-none-linux-gnueabihf- + $ make seeed_npi_imx6ull_defconfig + $ make + +This will generate SPL and u-boot-dtb.img images. + +Boot from MMC/SD: +- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card: + + $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 0 + SW4 -> 0 + SW5 -> 1 + SW6 -> 0 + SW7 -> 0 + SW8 -> 1 + +Boot from NAND: +- Boot the board using SD/MMC or Serial download and load the SPL into memory +either from SD/MMC or TFTP. + +Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi) + +Flash SPL to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr SPL + $ nand erase.part spl + $ nandbcb init $loadaddr 0x0 $filesize + +Flash u-boot image to NAND from SD/MMC, + + $ ext4load mmc 0:2 $loadaddr u-boot-dtb.img + $ nand erase.part uboot + $ nand write $loadaddr uboot $filesize + +- Boot mode settings: + + Boot switch position: SW1 -> 0 + SW2 -> 1 + SW3 -> 1 + SW4 -> 0 + SW5 -> 0 + SW6 -> 1 + SW7 -> 0 + SW8 -> 0 + +- Connect the Serial cable to UART0 and the PC for the console. + +- Reset the board using reset button and U-Boot should boot from NAND. diff --git a/board/seeed/npi_imx6ull/npi_imx6ull.c b/board/seeed/npi_imx6ull/npi_imx6ull.c new file mode 100644 index 0000000000..eb9ee555c8 --- /dev/null +++ b/board/seeed/npi_imx6ull/npi_imx6ull.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FEC_MXC + +static int setup_fec(int fec_id) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + if (fec_id == 0) { + /* + * Use 50MHz anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + } else { + /* + * Use 50MHz anatop loopbak REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + } + + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("Board: Seeed NPi i.MX6ULL Dev Board\n"); + + return 0; +} diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c new file mode 100644 index 0000000000..4b56f52d98 --- /dev/null +++ b/board/seeed/npi_imx6ull/spl.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Configuration for Micron MT41K256M16TW-107 32M x 16 x 8 -> 512MiB */ + +static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000030, + .grp_ddrmode_ctl = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ddr_type = 0x000c0000, +}; + +static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_ras = 0x00000030, + .dram_cas = 0x00000030, + .dram_odt0 = 0x00000030, + .dram_odt1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_reset = 0x00000030, +}; + +static struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00000000, + .p0_mpdgctrl0 = 0x41480148, + .p0_mprddlctl = 0x40403E42, + .p0_mpwrdlctl = 0x40405852, +}; + +struct mx6_ddr_sysinfo ddr_sysinfo = { + .dsize = 0, /* Bus size = 16bit */ + .cs_density = 32, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1, + .rtt_nom = 1, + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .pd_fast_exit = 1, + .sde_to_rst = 0x10, + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 7, /* 8 refresh commands per refresh cycle */ +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); +} + +static void spl_dram_init(void) +{ + mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifndef CONFIG_NAND_MXS +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + { + .esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, +#ifndef CONFIG_NAND_MXS + { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 8, + }, +#endif +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_NAND_MXS + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#endif + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* Setup iomux and fec */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); +} diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig new file mode 100644 index 0000000000..6503cabbd0 --- /dev/null +++ b/configs/seeed_npi_imx6ull_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=8 +CONFIG_ENV_SIZE=0x4000 +CONFIG_MX6ULL=y +CONFIG_TARGET_NPI_IMX6ULL=y +CONFIG_SPL_TEXT_BASE=0x908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-seeed-npi-imx6ull-dev-board" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_DMA=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +# CONFIG_CMD_I2C is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)" +CONFIG_SYS_NAND_USE_FLASH_BBT=y +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_DM_I2C_GPIO is not set +# CONFIG_SYS_I2C_MXC is not set +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x180000 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PMIC=y +CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_MMC=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_SMBIOS_MANUFACTURER="Seeed" diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h new file mode 100644 index 0000000000..3be9b8ff55 --- /dev/null +++ b/include/configs/npi_imx6ull.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri + */ + +#ifndef _NPI_IMX6ULL_H +#define _NPI_IMX6ULL_H + +#include +#include "mx6_common.h" + +/* SPL options */ +#include "imx6_spl.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +/* Size of malloc() poll */ +#define CONFIG_SYS_MALLOC_LEN SZ_2M + +/* Console configs */ +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* environment settings */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_ENV_IS_IN_NAND) +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#ifdef CONFIG_CMD_NET +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#endif + +#define CONFIG_IMX_THERMAL + +#define CONFIG_FEC_ENET_DEV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200n8\0" \ + "image=zImage\0" \ + "fdtfile=imx6ull-seeed-npi-dev-board.dtb\0" \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "fdt_addr_r=0x82000000\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" \ + "root=/dev/mmcblk0p2 rootwait\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) + +#include + +#endif /* _NPI_IMX6ULL_H */ From d4f15ecd4724e633bc7f238b26f98efd5096e632 Mon Sep 17 00:00:00 2001 From: Andrey Zhizhikin Date: Sun, 2 May 2021 16:32:37 +0200 Subject: [PATCH 41/42] imx8mn: configs: add support for distro boot commands Supported boot device types in iMX8MN: MMC, DHCP. Add DISTRO_DEFAULTS config option and include the distro boot command header file to enable full support of distro boot on i.MX8M Nano EVK (both DDR and LPDDR derivatives). Drop previous environment, which was targeting customized boot commands and boot order. Signed-off-by: Andrey Zhizhikin Cc: Peng Fan Reviewed-by: Fabio Estevam --- configs/imx8mn_ddr4_evk_defconfig | 1 + configs/imx8mn_evk_defconfig | 1 + include/configs/imx8mn_evk.h | 68 +++++++------------------------ 3 files changed, 16 insertions(+), 54 deletions(-) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index a3e51bad82..8eca79fd19 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 86601ebad3..e477028f71 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 596e255ca6..985bec803a 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -31,69 +31,29 @@ #endif +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) \ + func(DHCP, dhcp, na) + +#include +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ "image=Image\0" \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "console=ttymxc1,115200\0" \ - "fdt_addr=0x43000000\0" \ + "fdt_addr_r=0x43000000\0" \ "boot_fit=no\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ - "bootm ${loadaddr}; " \ - "else " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ - "bootm ${loadaddr}; " \ - "else " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "fi;" /* Link Definitions */ #define CONFIG_LOADADDR 0x40480000 From 40496ac3b71b9589a9149d423b81133eebce07b1 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 28 May 2021 10:26:57 -0300 Subject: [PATCH 42/42] mx7d: Add Storopack's SMEGW01 board Add support for Storopack's SMEGW01 board, which is an IoT gateway based on the i.MX7D SoC. Based on the original U-Boot work done by Phytec. Signed-off-by: Fabio Estevam --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx7d-smegw01.dts | 190 +++++++++++++++++++++++++++ arch/arm/mach-imx/mx7/Kconfig | 9 ++ board/storopack/smegw01/Kconfig | 12 ++ board/storopack/smegw01/MAINTAINERS | 7 + board/storopack/smegw01/Makefile | 4 + board/storopack/smegw01/imximage.cfg | 100 ++++++++++++++ board/storopack/smegw01/smegw01.c | 95 ++++++++++++++ configs/smegw01_defconfig | 63 +++++++++ include/configs/smegw01.h | 63 +++++++++ 10 files changed, 545 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx7d-smegw01.dts create mode 100644 board/storopack/smegw01/Kconfig create mode 100644 board/storopack/smegw01/MAINTAINERS create mode 100644 board/storopack/smegw01/Makefile create mode 100644 board/storopack/smegw01/imximage.cfg create mode 100644 board/storopack/smegw01/smegw01.c create mode 100644 configs/smegw01_defconfig create mode 100644 include/configs/smegw01.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 6884c4e98f..27bc6a7961 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -834,8 +834,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7s-warp.dtb \ imx7d-meerkat96.dtb \ imx7d-pico-pi.dtb \ - imx7d-pico-hobbit.dtb - + imx7d-pico-hobbit.dtb \ + imx7d-smegw01.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ imx7ulp-evk.dtb diff --git a/arch/arm/dts/imx7d-smegw01.dts b/arch/arm/dts/imx7d-smegw01.dts new file mode 100644 index 0000000000..aefc654ad8 --- /dev/null +++ b/arch/arm/dts/imx7d-smegw01.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2020 PHYTEC Messtechnik GmbH +// Author: Jens Lang +// Copyright (C) 2021 Fabio Estevam + +/dts-v1/; +#include "imx7d.dtsi" + +/ { + model = "Storopack SMEGW01 board"; + compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc3; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + max-frequency = <200000000>; + bus-width = <8>; + fsl,tuning-step = <1>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c + >; + }; + + pinctrl_usdhc1: usdhc1 { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5d + MX7D_PAD_SD3_CLK__SD3_CLK 0x1d + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5e + MX7D_PAD_SD3_CLK__SD3_CLK 0x1e + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5f + MX7D_PAD_SD3_CLK__SD3_CLK 0x0f + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 5c6fe426ef..adedc01164 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -70,6 +70,14 @@ config TARGET_PICO_IMX7D select SUPPORT_SPL imply CMD_DM +config TARGET_SMEGW01 + bool "smegw01" + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select MX7D + imply CMD_DM + config TARGET_WARP7 bool "warp7" select BOARD_LATE_INIT @@ -94,6 +102,7 @@ source "board/compulab/cl-som-imx7/Kconfig" source "board/ronetix/imx7-cm/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" source "board/novtech/meerkat96/Kconfig" +source "board/storopack/smegw01/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" diff --git a/board/storopack/smegw01/Kconfig b/board/storopack/smegw01/Kconfig new file mode 100644 index 0000000000..4503b65419 --- /dev/null +++ b/board/storopack/smegw01/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SMEGW01 + +config SYS_BOARD + default "smegw01" + +config SYS_VENDOR + default "storopack" + +config SYS_CONFIG_NAME + default "smegw01" + +endif diff --git a/board/storopack/smegw01/MAINTAINERS b/board/storopack/smegw01/MAINTAINERS new file mode 100644 index 0000000000..6acb8b9341 --- /dev/null +++ b/board/storopack/smegw01/MAINTAINERS @@ -0,0 +1,7 @@ +SMEGW01 BOARD +M: Fabio Estevam +S: Maintained +F: board/storopack/ +F: arch/arm/dts/imx7d-smegw01.dts +F: configs/smegw01_defconfig +F: include/configs/smegw01.h diff --git a/board/storopack/smegw01/Makefile b/board/storopack/smegw01/Makefile new file mode 100644 index 0000000000..f02e7bb8b0 --- /dev/null +++ b/board/storopack/smegw01/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2016 NXP Semiconductors + +obj-y := smegw01.o diff --git a/board/storopack/smegw01/imximage.cfg b/board/storopack/smegw01/imximage.cfg new file mode 100644 index 0000000000..c7fa06996c --- /dev/null +++ b/board/storopack/smegw01/imximage.cfg @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017 PHYTEC America, LLC + * + * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +IMAGE_VERSION 2 +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* DDR initialization came from Phytec */ +DATA 4 0x30340004 0x4F400005 +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x0040002b +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x090b1109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000802 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00001f15 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f0f0707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000d6e +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 +CHECK_BITS_SET 4 0x307900c4 0x1 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c new file mode 100644 index 0000000000..e6bff80e55 --- /dev/null +++ b/board/storopack/smegw01/smegw01.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Fabio Estevam + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +}; + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_fec(); + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + /* + * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), + * since we use PMIC_PWRON to reset the board. + */ + clrsetbits_le16(&wdog->wcr, 0, 0x10); + + return 0; +} diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig new file mode 100644 index 0000000000..aa10577a9f --- /dev/null +++ b/configs/smegw01_defconfig @@ -0,0 +1,63 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_SMEGW01=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/storopack/smegw01/imximage.cfg" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DFU_MMC=y +CONFIG_DM_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h new file mode 100644 index 0000000000..50f00136ac --- /dev/null +++ b/include/configs/smegw01.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 NXP Semiconductors + * Copyright (C) 2021 Fabio Estevam + * + * Configuration settings for the smegw01 board. + */ + +#ifndef __SMEGW01_CONFIG_H +#define __SMEGW01_CONFIG_H + +#include "mx7_common.h" +#include + +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdtfile=imx7d-smegw01.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#endif