s3c44b0: extract cache from cpu.c
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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40fd626223
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b2368754a9
@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(CPU).a
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START = start.o
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COBJS = interrupts.o cpu.o
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COBJS = cache.o cpu.o interrupts.o
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SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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91
cpu/s3c44b0/cache.c
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91
cpu/s3c44b0/cache.c
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@ -0,0 +1,91 @@
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/*
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* (C) Copyright 2004
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* DAVE Srl
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* http://www.dave-tech.it
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* http://www.wawnet.biz
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* mailto:info@wawnet.biz
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/hardware.h>
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static void s3c44b0_flush_cache(void)
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{
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volatile int i;
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/* flush cycle */
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for(i=0x10002000;i<0x10004800;i+=16)
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{
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*((int *)i)=0x0;
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}
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}
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void icache_enable (void)
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{
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ulong reg;
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s3c44b0_flush_cache();
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/*
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Init cache
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Non-cacheable area (everything outside RAM)
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0x0000:0000 - 0x0C00:0000
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*/
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NCACHBE0 = 0xC0000000;
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NCACHBE1 = 0x00000000;
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/*
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Enable chache
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*/
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reg = SYSCFG;
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reg |= 0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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void icache_disable (void)
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{
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ulong reg;
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reg = SYSCFG;
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reg &= ~0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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int icache_status (void)
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{
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return 0;
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}
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void dcache_enable (void)
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{
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icache_enable();
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}
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void dcache_disable (void)
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{
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icache_disable();
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}
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int dcache_status (void)
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{
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return dcache_status();
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}
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@ -32,17 +32,6 @@
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#include <command.h>
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#include <asm/hardware.h>
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static void s3c44b0_flush_cache(void)
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{
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volatile int i;
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/* flush cycle */
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for(i=0x10002000;i<0x10004800;i+=16)
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{
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*((int *)i)=0x0;
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}
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}
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int cpu_init (void)
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{
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icache_enable();
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@ -92,54 +81,3 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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/*NOTREACHED*/
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return (0);
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}
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void icache_enable (void)
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{
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ulong reg;
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s3c44b0_flush_cache();
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/*
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Init cache
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Non-cacheable area (everything outside RAM)
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0x0000:0000 - 0x0C00:0000
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*/
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NCACHBE0 = 0xC0000000;
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NCACHBE1 = 0x00000000;
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/*
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Enable chache
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*/
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reg = SYSCFG;
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reg |= 0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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void icache_disable (void)
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{
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ulong reg;
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reg = SYSCFG;
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reg &= ~0x00000006; /* 8kB */
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SYSCFG = reg;
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}
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int icache_status (void)
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{
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return 0;
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}
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void dcache_enable (void)
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{
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icache_enable();
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}
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void dcache_disable (void)
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{
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icache_disable();
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}
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int dcache_status (void)
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{
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return dcache_status();
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}
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