barco: drop unsupported board configuration
The barco board appears to be unmaintained since it was added about 5 years ago. The environment location has probably never been correct. Drop it. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Marc Leeman <marc.leeman@barco.com> Acked-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Wolfgang Denk
parent
93b1140090
commit
afaa27bdd6
5
CREDITS
5
CREDITS
@ -278,11 +278,6 @@ N: Thomas Lange
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E: thomas@corelatus.se
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D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes
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N: Marc Leeman
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E: marc.leeman@barco.com
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D: Support for Barco Streaming Video Card (SVC) and Sample Compress Network (SCN)
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W: www.barco.com
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N: The LEOX team
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E: team@leox.org
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D: Support for LEOX boards, DS164x RTC
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@ -1,44 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o flash.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,11 +0,0 @@
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This port of U-Boot is tuned to run on a range of Barco Control Rooms
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Streaming Video Solutions, including:
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- Streaming Video Card (SVC)
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- Sample Compress Network (SCN)
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For more information, see http://www.barcocontrolrooms.com/
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Code and configuration are originally based on the Sandpoint board
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Marc Leeman <marc.leeman@barco.com>
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@ -1,344 +0,0 @@
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/********************************************************************
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*
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* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
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*
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* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco.c,v $
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* $Revision: 1.4 $
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* $Author: mleeman $
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* $Date: 2005/03/02 16:40:20 $
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*
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* Last ChangeLog Entry
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* $Log: barco.c,v $
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* Revision 1.4 2005/03/02 16:40:20 mleeman
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* remove empty labels (3.4 complains)
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*
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* Revision 1.3 2005/02/21 12:48:58 mleeman
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* update of copyright years (feedback wd)
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*
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* Revision 1.2 2005/02/21 10:10:53 mleeman
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* - split up switch statement to a function call (Linux kernel coding guidelines)
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* ( feedback wd)
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*
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* Revision 1.1 2005/02/14 09:31:07 mleeman
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* renaming of files
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*
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* Revision 1.1 2005/02/14 09:23:46 mleeman
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* - moved 'barcohydra' directory to a more generic barco; since we will be
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* supporting and adding multiple boards
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*
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* Revision 1.3 2005/02/10 13:57:32 mleeman
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* fixed flash corruption: I should exit from the moment I find the correct value
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*
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* Revision 1.2 2005/02/09 12:56:23 mleeman
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* add generic header to track changes in sources
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*
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*
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*******************************************************************/
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/*
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* (C) Copyright 2004
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* Marc Leeman <marc.leeman@barco.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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#include <malloc.h>
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#include <command.h>
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#include "config.h"
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#include "barco_svc.h"
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#define TRY_WORKING (3)
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#define BOOT_DEFAULT (2)
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#define BOOT_WORKING (1)
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int checkboard (void)
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{
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/*TODO: Check processor type */
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puts ( "Board: Streaming Video Card for Hydra systems "
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#ifdef CONFIG_MPC8240
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"8240"
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#endif
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#ifdef CONFIG_MPC8245
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"8245"
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#endif
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" Unity ##Test not implemented yet##\n");
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return 0;
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}
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phys_size_t initdram (int board_type)
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{
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long size;
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long new_bank0_end;
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long mear1;
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long emear1;
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size = get_ram_size (CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
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new_bank0_end = size - 1;
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mear1 = mpc824x_mpc107_getreg (MEAR1);
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emear1 = mpc824x_mpc107_getreg (EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg (MEAR1, mear1);
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mpc824x_mpc107_setreg (EMEAR1, emear1);
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return (size);
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_barcohydra_config_table[] = {
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER } },
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_barcohydra_config_table,
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#endif
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};
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void pci_init_board (void)
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{
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pci_mpc824x_init (&hose);
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}
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int write_flash (char *addr, char value)
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{
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char *adr = (char *)0xFF800000;
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int cnt = 0;
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char status,oldstatus;
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*(adr+0x55) = 0xAA; udelay (1);
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*(adr+0xAA) = 0x55; udelay (1);
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*(adr+0x55) = 0xA0; udelay (1);
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*addr = value;
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status = *addr;
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do {
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oldstatus = status;
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status = *addr;
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if ((oldstatus & 0x40) == (status & 0x40)) {
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return 4;
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}
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cnt++;
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if (cnt > 10000) {
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return 2;
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}
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} while ( (status & 0x20) == 0 );
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oldstatus = *addr;
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status = *addr;
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if ((oldstatus & 0x40) == (status & 0x40)) {
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return 0;
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} else {
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*(adr+0x55) = 0xF0;
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return 1;
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}
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}
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unsigned update_flash (unsigned char *buf)
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{
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switch ((*buf) & 0x3) {
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case TRY_WORKING:
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printf ("found 3 and converted it to 2\n");
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write_flash ((char *)buf, (*buf) & 0xFE);
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*((unsigned char *)0xFF800000) = 0xF0;
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udelay (100);
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printf ("buf [%#010x] %#010x\n", (unsigned)buf, (*buf));
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/* XXX - fall through??? */
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case BOOT_WORKING :
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return BOOT_WORKING;
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}
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return BOOT_DEFAULT;
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}
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unsigned scan_flash (void)
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{
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char section[] = "kernel";
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int cfgFileLen = (CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH >> 1);
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int sectionPtr = 0;
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int foundItem = 0; /* 0: None, 1: section found, 2: "=" found */
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int bufPtr;
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unsigned char *buf;
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buf = (unsigned char*)(CONFIG_SYS_FLASH_RANGE_BASE + CONFIG_SYS_FLASH_RANGE_SIZE \
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- CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH);
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for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) {
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if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) {
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return BOOT_DEFAULT;
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}
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/* This is the scanning loop, we try to find a particular
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* quoted value
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*/
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switch (foundItem) {
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case 0:
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if ((section[sectionPtr] == 0)) {
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++foundItem;
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} else if (buf[bufPtr] == section[sectionPtr]) {
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++sectionPtr;
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} else {
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sectionPtr = 0;
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}
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break;
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case 1:
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++foundItem;
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break;
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case 2:
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++foundItem;
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break;
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case 3:
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default:
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return update_flash (&buf[bufPtr - 1]);
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}
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}
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printf ("Failed to read %s\n",section);
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return BOOT_DEFAULT;
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}
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TSBootInfo* find_boot_info (void)
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{
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unsigned bootimage = scan_flash ();
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TSBootInfo* info = (TSBootInfo*)malloc (sizeof(TSBootInfo));
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switch (bootimage) {
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case TRY_WORKING:
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info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS;
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break;
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case BOOT_WORKING :
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info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS;
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break;
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case BOOT_DEFAULT:
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default:
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info->address= CONFIG_SYS_DEFAULT_KERNEL_ADDRESS;
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}
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info->size = *((unsigned int *)(info->address ));
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return info;
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}
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void barcobcd_boot (void)
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{
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TSBootInfo* start;
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char *bootm_args[2];
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char *buf;
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int cnt;
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extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
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buf = (char *)(0x00800000);
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/* make certain there are enough chars to print the command line here!
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*/
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bootm_args[0] = (char *)malloc (16*sizeof(char));
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bootm_args[1] = (char *)malloc (16*sizeof(char));
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start = find_boot_info ();
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printf ("Booting kernel at address %#10x with size %#10x\n",
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start->address, start->size);
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/* give length of the kernel image to bootm */
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sprintf (bootm_args[0],"%x",start->size);
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/* give address of the kernel image to bootm */
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sprintf (bootm_args[1],"%x",(unsigned)buf);
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printf ("flash address: %#10x\n",start->address+8);
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printf ("buf address: %#10x\n",(unsigned)buf);
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/* aha, we reserve 8 bytes here... */
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for (cnt = 0; cnt < start->size ; cnt++) {
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buf[cnt] = ((char *)start->address)[cnt+8];
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}
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/* initialise RAM memory */
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*((unsigned int *)0xFEC00000) = 0x00141A98;
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do_bootm (NULL,0,2,bootm_args);
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}
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int barcobcd_boot_image (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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barcobcd_boot ();
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return 0;
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}
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/* Currently, boot_working and boot_default are the same command. This is
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* left in here to see what we'll do in the future */
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U_BOOT_CMD (
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try_working, 1, 1, barcobcd_boot_image,
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"check flash value and boot the appropriate image",
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""
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);
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U_BOOT_CMD (
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boot_working, 1, 1, barcobcd_boot_image,
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"check flash value and boot the appropriate image",
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""
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);
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U_BOOT_CMD (
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boot_default, 1, 1, barcobcd_boot_image,
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"check flash value and boot the appropriate image",
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""
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);
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/*
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* We are not using serial communication, so just provide empty functions
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*/
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int serial_init (void)
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{
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return 0;
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}
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void serial_setbrg (void)
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{
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return;
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}
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void serial_putc (const char c)
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{
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return;
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}
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void serial_puts (const char *c)
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{
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return;
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}
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int serial_getc (void)
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{
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return 0;
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}
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int serial_tstc (void)
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{
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return 0;
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}
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@ -1,68 +0,0 @@
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/********************************************************************
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*
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* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
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*
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* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/barco_svc.h,v $
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* $Revision: 1.2 $
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* $Author: mleeman $
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* $Date: 2005/02/21 12:48:58 $
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*
|
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* Last ChangeLog Entry
|
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* $Log: barco_svc.h,v $
|
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* Revision 1.2 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:31:07 mleeman
|
||||
* renaming of files
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:23:46 mleeman
|
||||
* - moved 'barcohydra' directory to a more generic barco; since we will be
|
||||
* supporting and adding multiple boards
|
||||
*
|
||||
* Revision 1.1 2005/02/08 15:40:19 mleeman
|
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* modified and added platform files
|
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*
|
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* Revision 1.2 2005/01/25 08:05:04 mleeman
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* more cleanup of the code
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*
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* Revision 1.1 2004/07/20 08:49:55 mleeman
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* Working version of the default and nfs kernel booting.
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*
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*
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*******************************************************************/
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#ifndef _LOCAL_BARCOHYDRA_H_
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#define _LOCAL_BARCOHYDRA_H_
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#include <flash.h>
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#include <asm/io.h>
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|
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/* Defines for the barcohydra board */
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#ifndef CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH
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#define CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH (0x10000)
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#endif
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#ifndef CONFIG_SYS_DEFAULT_KERNEL_ADDRESS
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#define CONFIG_SYS_DEFAULT_KERNEL_ADDRESS (CONFIG_SYS_FLASH_BASE + 0x30000)
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#endif
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|
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#ifndef CONFIG_SYS_WORKING_KERNEL_ADDRESS
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#define CONFIG_SYS_WORKING_KERNEL_ADDRESS (0xFFE00000)
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#endif
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|
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typedef struct SBootInfo {
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unsigned int address;
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unsigned int size;
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unsigned char state;
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}TSBootInfo;
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|
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/* barcohydra.c */
|
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int checkboard(void);
|
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phys_size_t initdram(int board_type);
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void pci_init_board(void);
|
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void check_flash(void);
|
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int write_flash(char *addr, char value);
|
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TSBootInfo* find_boot_info(void);
|
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void final_boot(void);
|
||||
#endif
|
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@ -1,153 +0,0 @@
|
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/*
|
||||
* (C) Copyright 2001
|
||||
* Thomas Koeller, tkoeller@gmx.net
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#define __ASSEMBLY__ 1
|
||||
#endif
|
||||
|
||||
#include <asm-offsets.h>
|
||||
#include <config.h>
|
||||
#include <asm/processor.h>
|
||||
#include <mpc824x.h>
|
||||
#include <ppc_asm.tmpl>
|
||||
|
||||
#if defined(USE_DINK32)
|
||||
/* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
|
||||
#define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
|
||||
#else
|
||||
#define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
|
||||
#endif
|
||||
|
||||
.text
|
||||
|
||||
/* Values to program into memory controller registers */
|
||||
tbl: .long MCCR1, MCCR1VAL
|
||||
.long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
|
||||
.long MCCR3
|
||||
.long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
|
||||
(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
|
||||
(CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)
|
||||
.long MCCR4
|
||||
.long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
|
||||
(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
|
||||
(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
|
||||
((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
|
||||
(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
|
||||
(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
|
||||
((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
|
||||
.long MSAR1
|
||||
.long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMSAR1
|
||||
.long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long MSAR2
|
||||
.long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMSAR2
|
||||
.long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long MEAR1
|
||||
.long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMEAR1
|
||||
.long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long MEAR2
|
||||
.long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
|
||||
.long EMEAR2
|
||||
.long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
|
||||
(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
|
||||
(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
|
||||
(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
|
||||
.long 0
|
||||
|
||||
|
||||
/*
|
||||
* Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
|
||||
* must be done in assembly, since we have no stack at this point.
|
||||
*/
|
||||
.global early_init_f
|
||||
early_init_f:
|
||||
mflr r10
|
||||
|
||||
/* basic memory controller configuration */
|
||||
lis r3, CONFIG_ADDR_HIGH
|
||||
lis r4, CONFIG_DATA_HIGH
|
||||
bl lab
|
||||
lab: mflr r5
|
||||
lwzu r0, tbl - lab(r5)
|
||||
loop: lwz r1, 4(r5)
|
||||
stwbrx r0, 0, r3
|
||||
eieio
|
||||
stwbrx r1, 0, r4
|
||||
eieio
|
||||
lwzu r0, 8(r5)
|
||||
cmpli cr0, 0, r0, 0
|
||||
bne cr0, loop
|
||||
|
||||
/* set bank enable bits */
|
||||
lis r0, MBER@h
|
||||
ori r0, 0, MBER@l
|
||||
li r1, CONFIG_SYS_BANK_ENABLE
|
||||
stwbrx r0, 0, r3
|
||||
eieio
|
||||
stb r1, 0(r4)
|
||||
eieio
|
||||
|
||||
/* delay loop */
|
||||
lis r0, 0x0003
|
||||
mtctr r0
|
||||
delay: bdnz delay
|
||||
|
||||
/* enable memory controller */
|
||||
lis r0, MCCR1@h
|
||||
ori r0, 0, MCCR1@l
|
||||
stwbrx r0, 0, r3
|
||||
eieio
|
||||
lwbrx r0, 0, r4
|
||||
oris r0, 0, MCCR1_MEMGO@h
|
||||
stwbrx r0, 0, r4
|
||||
eieio
|
||||
|
||||
/* set up stack pointer */
|
||||
lis r1, CONFIG_SYS_INIT_SP_OFFSET@h
|
||||
ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
|
||||
|
||||
mtlr r10
|
||||
blr
|
||||
@ -1,611 +0,0 @@
|
||||
/********************************************************************
|
||||
*
|
||||
* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
|
||||
*
|
||||
* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/flash.c,v $
|
||||
* $Revision: 1.3 $
|
||||
* $Author: mleeman $
|
||||
* $Date: 2005/02/21 12:48:58 $
|
||||
*
|
||||
* Last ChangeLog Entry
|
||||
* $Log: flash.c,v $
|
||||
* Revision 1.3 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.2 2005/02/21 11:04:04 mleeman
|
||||
* remove dead code and Coding style (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:23:46 mleeman
|
||||
* - moved 'barcohydra' directory to a more generic barco; since we will be
|
||||
* supporting and adding multiple boards
|
||||
*
|
||||
* Revision 1.2 2005/02/09 12:56:23 mleeman
|
||||
* add generic header to track changes in sources
|
||||
*
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <mpc824x.h>
|
||||
#include <asm/processor.h>
|
||||
#include <flash.h>
|
||||
|
||||
#define ROM_CS0_START 0xFF800000
|
||||
#define ROM_CS1_START 0xFF000000
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_FLASH)
|
||||
# ifndef CONFIG_ENV_ADDR
|
||||
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
|
||||
# endif
|
||||
# ifndef CONFIG_ENV_SIZE
|
||||
# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
|
||||
# endif
|
||||
# ifndef CONFIG_ENV_SECT_SIZE
|
||||
# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
||||
|
||||
/*flash command address offsets*/
|
||||
|
||||
#define ADDR0 (0xAAA)
|
||||
#define ADDR1 (0x555)
|
||||
#define ADDR3 (0x001)
|
||||
|
||||
#define FLASH_WORD_SIZE unsigned char
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
static unsigned long flash_id(unsigned char mfct, unsigned char chip) __attribute__ ((const));
|
||||
|
||||
typedef struct{
|
||||
FLASH_WORD_SIZE extval;
|
||||
unsigned short intval;
|
||||
} map_entry;
|
||||
|
||||
static unsigned long flash_id(unsigned char mfct, unsigned char chip)
|
||||
{
|
||||
static const map_entry mfct_map[] = {
|
||||
{(FLASH_WORD_SIZE) AMD_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
|
||||
{(FLASH_WORD_SIZE) FUJ_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
|
||||
{(FLASH_WORD_SIZE) STM_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
|
||||
{(FLASH_WORD_SIZE) MT_MANUFACT, (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
|
||||
{(FLASH_WORD_SIZE) INTEL_MANUFACT,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
|
||||
{(FLASH_WORD_SIZE) INTEL_ALT_MANU,(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
|
||||
};
|
||||
|
||||
static const map_entry chip_map[] = {
|
||||
{AMD_ID_F040B, FLASH_AM040},
|
||||
{AMD_ID_F033C, FLASH_AM033},
|
||||
{AMD_ID_F065D, FLASH_AM065},
|
||||
{ATM_ID_LV040, FLASH_AT040},
|
||||
{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
|
||||
};
|
||||
|
||||
const map_entry *p;
|
||||
unsigned long result = FLASH_UNKNOWN;
|
||||
|
||||
/* find chip id */
|
||||
for(p = &chip_map[0]; p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++){
|
||||
if(p->extval == chip){
|
||||
result = FLASH_VENDMASK | p->intval;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* find vendor id */
|
||||
for(p = &mfct_map[0]; p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++){
|
||||
if(p->extval == mfct){
|
||||
result &= ~FLASH_VENDMASK;
|
||||
result |= (unsigned long) p->intval << 16;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
unsigned long flash_init(void)
|
||||
{
|
||||
unsigned long i;
|
||||
unsigned char j;
|
||||
static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++){
|
||||
flash_info_t * const pflinfo = &flash_info[i];
|
||||
pflinfo->flash_id = FLASH_UNKNOWN;
|
||||
pflinfo->size = 0;
|
||||
pflinfo->sector_count = 0;
|
||||
}
|
||||
|
||||
/* Enable writes to Hydra/Argus flash */
|
||||
{
|
||||
register unsigned int temp;
|
||||
CONFIG_READ_WORD(PICR1,temp);
|
||||
temp |= PICR1_FLASH_WR_EN;
|
||||
CONFIG_WRITE_WORD(PICR1,temp);
|
||||
}
|
||||
|
||||
for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++){
|
||||
flash_info_t * const pflinfo = &flash_info[i];
|
||||
const unsigned long base_address = flash_banks[i];
|
||||
volatile FLASH_WORD_SIZE * const flash = (FLASH_WORD_SIZE *) base_address;
|
||||
|
||||
/* write autoselect sequence */
|
||||
flash[0x5555] = 0xaa;
|
||||
flash[0x2aaa] = 0x55;
|
||||
flash[0x5555] = 0x90;
|
||||
__asm__ __volatile__("sync");
|
||||
|
||||
pflinfo->flash_id = flash_id(flash[0x0], flash[0x1]);
|
||||
|
||||
switch(pflinfo->flash_id & FLASH_TYPEMASK){
|
||||
case FLASH_AM033:
|
||||
pflinfo->size = 0x00200000;
|
||||
pflinfo->sector_count = 64;
|
||||
for(j = 0; j < 64; j++){
|
||||
pflinfo->start[j] = base_address + 0x00010000 * j;
|
||||
pflinfo->protect[j] = flash[(j << 16) | 0x2];
|
||||
}
|
||||
break;
|
||||
case FLASH_AM065:
|
||||
pflinfo->size = 0x00800000;
|
||||
pflinfo->sector_count =128;
|
||||
for(j = 0; j < 128; j++){
|
||||
pflinfo->start[j] = base_address + 0x00010000 * j;
|
||||
pflinfo->protect[j] = flash[(j << 16) | 0x2];
|
||||
}
|
||||
break;
|
||||
case FLASH_AT040:
|
||||
pflinfo->size = 0x00080000;
|
||||
pflinfo->sector_count = 2;
|
||||
pflinfo->start[0] = base_address ;
|
||||
pflinfo->start[1] = base_address + 0x00004000;
|
||||
pflinfo->protect[0] = ((flash[0x02] & 0X01)==0) ? 0X02 : 0X01;
|
||||
pflinfo->protect[1] = 0X02;
|
||||
break;
|
||||
case FLASH_AM040:
|
||||
pflinfo->size = 0x00080000;
|
||||
pflinfo->sector_count = 8;
|
||||
for(j = 0; j < 8; j++){
|
||||
pflinfo->start[j] = base_address + 0x00010000 * j;
|
||||
pflinfo->protect[j] = flash[(j << 16) | 0x2];
|
||||
}
|
||||
break;
|
||||
case FLASH_STM800AB:
|
||||
pflinfo->size = 0x00100000;
|
||||
pflinfo->sector_count = 19;
|
||||
pflinfo->start[0] = base_address;
|
||||
pflinfo->start[1] = base_address + 0x4000;
|
||||
pflinfo->start[2] = base_address + 0x6000;
|
||||
pflinfo->start[3] = base_address + 0x8000;
|
||||
for(j = 1; j < 16; j++){
|
||||
pflinfo->start[j+3] = base_address + 0x00010000 * j;
|
||||
}
|
||||
break;
|
||||
}
|
||||
/* Protect monitor and environment sectors */
|
||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_MONITOR_BASE,
|
||||
CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
|
||||
flash_protect(FLAG_PROTECT_SET,
|
||||
CONFIG_ENV_ADDR,
|
||||
CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
#endif
|
||||
|
||||
/* reset device to read mode */
|
||||
flash[0x0000] = 0xf0;
|
||||
__asm__ __volatile__("sync");
|
||||
}
|
||||
|
||||
return flash_info[0].size + flash_info[1].size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info(flash_info_t *info)
|
||||
{
|
||||
static const char unk[] = "Unknown";
|
||||
const char *mfct = unk, *type = unk;
|
||||
unsigned int i;
|
||||
|
||||
if(info->flash_id != FLASH_UNKNOWN){
|
||||
switch(info->flash_id & FLASH_VENDMASK){
|
||||
case FLASH_MAN_ATM:
|
||||
mfct = "Atmel";
|
||||
break;
|
||||
case FLASH_MAN_AMD:
|
||||
mfct = "AMD";
|
||||
break;
|
||||
case FLASH_MAN_FUJ:
|
||||
mfct = "FUJITSU";
|
||||
break;
|
||||
case FLASH_MAN_STM:
|
||||
mfct = "STM";
|
||||
break;
|
||||
case FLASH_MAN_SST:
|
||||
mfct = "SST";
|
||||
break;
|
||||
case FLASH_MAN_BM:
|
||||
mfct = "Bright Microelectonics";
|
||||
break;
|
||||
case FLASH_MAN_INTEL:
|
||||
mfct = "Intel";
|
||||
break;
|
||||
}
|
||||
|
||||
switch(info->flash_id & FLASH_TYPEMASK){
|
||||
case FLASH_AT040:
|
||||
type = "AT49LV040 (512K * 8, uniform sector size)";
|
||||
break;
|
||||
case FLASH_AM033:
|
||||
type = "AM29F033C (4 Mbit * 8, uniform sector size)";
|
||||
break;
|
||||
case FLASH_AM040:
|
||||
type = "AM29F040B (512K * 8, uniform sector size)";
|
||||
break;
|
||||
case FLASH_AM065:
|
||||
type = "AM29F0465D ( 8 MBit * 8, uniform sector size) or part of AM29F652D( 16 MB)";
|
||||
break;
|
||||
case FLASH_AM400B:
|
||||
type = "AM29LV400B (4 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_AM400T:
|
||||
type = "AM29LV400T (4 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_AM800B:
|
||||
type = "AM29LV800B (8 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_AM800T:
|
||||
type = "AM29LV800T (8 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_AM160T:
|
||||
type = "AM29LV160T (16 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_AM320B:
|
||||
type = "AM29LV320B (32 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_AM320T:
|
||||
type = "AM29LV320T (32 Mbit, top boot sector)";
|
||||
break;
|
||||
case FLASH_STM800AB:
|
||||
type = "M29W800AB (8 Mbit, bottom boot sect)";
|
||||
break;
|
||||
case FLASH_SST800A:
|
||||
type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
|
||||
break;
|
||||
case FLASH_SST160A:
|
||||
type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
printf(
|
||||
"\n Brand: %s Type: %s\n"
|
||||
" Size: %lu KB in %d Sectors\n",
|
||||
mfct,
|
||||
type,
|
||||
info->size >> 10,
|
||||
info->sector_count
|
||||
);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
|
||||
for (i = 0; i < info->sector_count; i++){
|
||||
unsigned long size;
|
||||
unsigned int erased;
|
||||
unsigned long * flash = (unsigned long *) info->start[i];
|
||||
|
||||
/*
|
||||
* Check if whole sector is erased
|
||||
*/
|
||||
size =
|
||||
(i != (info->sector_count - 1)) ?
|
||||
(info->start[i + 1] - info->start[i]) >> 2 :
|
||||
(info->start[0] + info->size - info->start[i]) >> 2;
|
||||
|
||||
for(
|
||||
flash = (unsigned long *) info->start[i], erased = 1;
|
||||
(flash != (unsigned long *) info->start[i] + size) && erased;
|
||||
flash++
|
||||
){
|
||||
erased = *flash == ~0x0UL;
|
||||
}
|
||||
|
||||
printf(
|
||||
"%s %08lX %s %s",
|
||||
(i % 5) ? "" : "\n ",
|
||||
info->start[i],
|
||||
erased ? "E" : " ",
|
||||
info->protect[i] ? "RO" : " "
|
||||
);
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
return;
|
||||
}
|
||||
|
||||
int flash_erase(flash_info_t *info, int s_first, int s_last)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[0]);
|
||||
int flag, prot, sect, l_sect;
|
||||
ulong start, now, last;
|
||||
unsigned char sh8b;
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf ("- missing\n");
|
||||
} else {
|
||||
printf ("- no sectors to erase\n");
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
||||
(info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
|
||||
printf ("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect=s_first; sect<=s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
|
||||
if (prot) {
|
||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
||||
prot);
|
||||
} else {
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Check the ROM CS */
|
||||
if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
|
||||
sh8b = 3;
|
||||
}
|
||||
else{
|
||||
sh8b = 0;
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect<=s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr = (FLASH_WORD_SIZE *)(info->start[0] + (
|
||||
(info->start[sect] - info->start[0]) << sh8b));
|
||||
if (info->flash_id & FLASH_MAN_SST){
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00800080;
|
||||
addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00500050; /* block erase */
|
||||
udelay(30000); /* wait 30 ms */
|
||||
}
|
||||
else
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00300030; /* sector erase */
|
||||
l_sect = sect;
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag){
|
||||
enable_interrupts();
|
||||
}
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* We wait for the last triggered sector
|
||||
*/
|
||||
if (l_sect < 0){
|
||||
goto DONE;
|
||||
}
|
||||
|
||||
start = get_timer (0);
|
||||
last = start;
|
||||
addr = (FLASH_WORD_SIZE *)(info->start[0] + (
|
||||
(info->start[l_sect] - info->start[0]) << sh8b));
|
||||
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
|
||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
printf ("Timeout\n");
|
||||
return 1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
serial_putc ('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
|
||||
DONE:
|
||||
/* reset to read mode */
|
||||
addr = (FLASH_WORD_SIZE *)info->start[0];
|
||||
addr[0] = (FLASH_WORD_SIZE)0x00F000F0; /* reset bank */
|
||||
|
||||
printf (" done\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
||||
{
|
||||
ulong cp, wp, data;
|
||||
int i, l, rc;
|
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */
|
||||
|
||||
/*
|
||||
* handle unaligned start bytes
|
||||
*/
|
||||
if ((l = addr - wp) != 0) {
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
for (; i<4 && cnt>0; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
++cp;
|
||||
}
|
||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
}
|
||||
|
||||
/*
|
||||
* handle word aligned part
|
||||
*/
|
||||
while (cnt >= 4) {
|
||||
data = 0;
|
||||
for (i=0; i<4; ++i) {
|
||||
data = (data << 8) | *src++;
|
||||
}
|
||||
if ((rc = write_word(info, wp, data)) != 0) {
|
||||
return (rc);
|
||||
}
|
||||
wp += 4;
|
||||
cnt -= 4;
|
||||
}
|
||||
|
||||
if (cnt == 0) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* handle unaligned tail bytes
|
||||
*/
|
||||
data = 0;
|
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
||||
data = (data << 8) | *src++;
|
||||
--cnt;
|
||||
}
|
||||
for (; i<4; ++i, ++cp) {
|
||||
data = (data << 8) | (*(uchar *)cp);
|
||||
}
|
||||
|
||||
return (write_word(info, wp, data));
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns:
|
||||
* 0 - OK
|
||||
* 1 - write timeout
|
||||
* 2 - Flash not erased
|
||||
*/
|
||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
||||
{
|
||||
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)info->start[0];
|
||||
volatile FLASH_WORD_SIZE *dest2;
|
||||
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
|
||||
ulong start;
|
||||
int flag;
|
||||
int i;
|
||||
unsigned char sh8b;
|
||||
|
||||
/* Check the ROM CS */
|
||||
if ((info->start[0] >= ROM_CS1_START) && (info->start[0] < ROM_CS0_START)){
|
||||
sh8b = 3;
|
||||
}
|
||||
else{
|
||||
sh8b = 0;
|
||||
}
|
||||
|
||||
dest2 = (FLASH_WORD_SIZE *)(((dest - info->start[0]) << sh8b) +
|
||||
info->start[0]);
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest2 & (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
|
||||
return (2);
|
||||
}
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++){
|
||||
addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00AA00AA;
|
||||
addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE)0x00550055;
|
||||
addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE)0x00A000A0;
|
||||
|
||||
dest2[i << sh8b] = data2[i];
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag){
|
||||
enable_interrupts();
|
||||
}
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer (0);
|
||||
while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
|
||||
(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
@ -1,78 +0,0 @@
|
||||
/********************************************************************
|
||||
*
|
||||
* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
|
||||
*
|
||||
* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/board/barco/speed.h,v $
|
||||
* $Revision: 1.2 $
|
||||
* $Author: mleeman $
|
||||
* $Date: 2005/02/21 12:48:58 $
|
||||
*
|
||||
* Last ChangeLog Entry
|
||||
* $Log: speed.h,v $
|
||||
* Revision 1.2 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:23:46 mleeman
|
||||
* - moved 'barcohydra' directory to a more generic barco; since we will be
|
||||
* supporting and adding multiple boards
|
||||
*
|
||||
* Revision 1.2 2005/02/09 12:56:23 mleeman
|
||||
* add generic header to track changes in sources
|
||||
*
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Timer value for timer 2, ICLK = 10
|
||||
*
|
||||
* SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1))
|
||||
* SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1
|
||||
*
|
||||
* SPEED_FCOUNT2 timer 2 counting frequency
|
||||
* GCLK CPU clock
|
||||
* SPEED_TMR2_PS prescaler
|
||||
*/
|
||||
#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Timer value for PIT
|
||||
*
|
||||
* PIT_TIME = SPEED_PITC / PITRTCLK
|
||||
* PITRTCLK = 8192
|
||||
*/
|
||||
#define SPEED_PITC (82 << 16) /* start counting from 82 */
|
||||
|
||||
/*
|
||||
* The new value for PTA is calculated from
|
||||
*
|
||||
* PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock !)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
* DFBRG For normal mode (no clock reduction) always 0
|
||||
* PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh)
|
||||
* NCS Number of SDRAM banks (chip selects) on this UPM.
|
||||
*/
|
||||
@ -147,7 +147,6 @@ TQM5200 powerpc mpc5xxx tqm5200 tqc - TQM5200:
|
||||
MVBC_P powerpc mpc5xxx mvbc_p matrix_vision - MVBC_P:MVBC_P
|
||||
sorcery powerpc mpc8220
|
||||
A3000 powerpc mpc824x a3000
|
||||
barco powerpc mpc824x
|
||||
BMW powerpc mpc824x bmw
|
||||
CU824 powerpc mpc824x cu824
|
||||
eXalion powerpc mpc824x eXalion
|
||||
|
||||
@ -11,7 +11,8 @@ easily if here is something they might want to dig for...
|
||||
|
||||
Board Arch CPU removed Commit last known maintainer/contact
|
||||
=============================================================================
|
||||
ERIC powerpc 405GP - 2010-11-21 Swen Anderson <sand@peppercon.de>
|
||||
barco powerpc MPC8245 - 2010-11-23 Marc Leeman <marc.leeman@barco.com>
|
||||
ERIC powerpc 405GP d9ba451 2010-11-21 Swen Anderson <sand@peppercon.de>
|
||||
VoVPN-GW_100MHz powerpc MPC8260 26fe3d2 2010-10-24 Juergen Selent <j.selent@elmeg.de>
|
||||
NC650 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
|
||||
CP850 powerpc MPC852 333d86d 2010-10-19 Wolfgang Denk <wd@denx.de>
|
||||
|
||||
@ -1,364 +0,0 @@
|
||||
/********************************************************************
|
||||
*
|
||||
* Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
|
||||
*
|
||||
* $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
|
||||
* $Revision: 1.2 $
|
||||
* $Author: mleeman $
|
||||
* $Date: 2005/02/21 12:48:58 $
|
||||
*
|
||||
* Last ChangeLog Entry
|
||||
* $Log: barco.h,v $
|
||||
* Revision 1.2 2005/02/21 12:48:58 mleeman
|
||||
* update of copyright years (feedback wd)
|
||||
*
|
||||
* Revision 1.1 2005/02/14 09:29:25 mleeman
|
||||
* moved barcohydra.h to barco.h
|
||||
*
|
||||
* Revision 1.4 2005/02/09 12:56:23 mleeman
|
||||
* add generic header to track changes in sources
|
||||
*
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
/*
|
||||
* (C) Copyright 2001, 2002
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC824X 1
|
||||
#define CONFIG_MPC8245 1
|
||||
#define CONFIG_BARCOBCD_STREAMING 1
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFF00000
|
||||
|
||||
#undef USE_DINK32
|
||||
|
||||
#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_DRAM_SPEED 100 /* MHz */
|
||||
|
||||
#define CONFIG_BOOTARGS "mem=32M"
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_DNS
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
#undef CONFIG_CMD_NET
|
||||
|
||||
|
||||
#define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
#define CONFIG_BOOTCOMMAND "boot_default"
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#undef CONFIG_PCI_PNP
|
||||
|
||||
#define PCI_ENET0_IOADDR 0x80000000
|
||||
#define PCI_ENET0_MEMADDR 0x80000000
|
||||
#define PCI_ENET1_IOADDR 0x81000000
|
||||
#define PCI_ENET1_MEMADDR 0x81000000
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
|
||||
|
||||
#define CONFIG_LOGBUFFER
|
||||
#ifdef CONFIG_LOGBUFFER
|
||||
#define CONFIG_SYS_STDOUT_ADDR 0x1FFC000
|
||||
#define CONFIG_SYS_POST_WORD_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 4)
|
||||
#else
|
||||
#define CONFIG_SYS_STDOUT_ADDR 0x2B9000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
|
||||
|
||||
#if defined (USE_DINK32)
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x00030000
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00090000
|
||||
#define CONFIG_SYS_RAMBOOT 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x00030000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFF00000
|
||||
#define CONFIG_SYS_FLASH_SIZE (8 * 1024 * 1024) /* Unity has onboard 1MByte flash */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET 0x000047A4 /* Offset of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
|
||||
/* #define ENV_CRC 0x8BF6F24B XXX - FIXME: gets defined automatically */
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_EUMB_ADDR 0xFDF00000
|
||||
|
||||
#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFC00000 /* flash memory address range */
|
||||
#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00400000
|
||||
#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
|
||||
#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
|
||||
|
||||
/*
|
||||
* select i2c support configuration
|
||||
*
|
||||
* Supported configurations are {none, software, hardware} drivers.
|
||||
* If the software driver is chosen, there are some additional
|
||||
* configuration items that the driver uses to drive the port pins.
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1 /* To enable I2C support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
#ifdef CONFIG_SOFT_I2C
|
||||
#error "Soft I2C is not configured properly. Please review!"
|
||||
#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
#endif /* CONFIG_SOFT_I2C */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
|
||||
#define CONFIG_SYS_DBUS_SIZE2 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* NS16550 Configuration (internal DUART)
|
||||
*/
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_SYS_ROMNAL 0x0F /*rom/flash next access time */
|
||||
#define CONFIG_SYS_ROMFAL 0x1E /*rom/flash access time */
|
||||
|
||||
#define CONFIG_SYS_REFINT 0x8F /* no of clock cycles between CBR refresh cycles */
|
||||
|
||||
/* the following are for SDRAM only*/
|
||||
#define CONFIG_SYS_BSTOPRE 0x25C /* Burst To Precharge, sets open page interval */
|
||||
#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
|
||||
#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
|
||||
#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
|
||||
#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
|
||||
#define CONFIG_SYS_ACTORW 2 /* Activate to R/W */
|
||||
#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
|
||||
#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
|
||||
|
||||
#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
|
||||
#define CONFIG_SYS_EXTROM 0
|
||||
#define CONFIG_SYS_REGDIMM 0
|
||||
|
||||
|
||||
/* memory bank settings*/
|
||||
/*
|
||||
* only bits 20-29 are actually used from these vales to set the
|
||||
* start/end address the upper two bits will be 0, and the lower 20
|
||||
* bits will be set to 0x00000 for a start address, or 0xfffff for an
|
||||
* end address
|
||||
*/
|
||||
#define CONFIG_SYS_BANK0_START 0x00000000
|
||||
#define CONFIG_SYS_BANK0_END 0x01FFFFFF
|
||||
#define CONFIG_SYS_BANK0_ENABLE 1
|
||||
#define CONFIG_SYS_BANK1_START 0x02000000
|
||||
#define CONFIG_SYS_BANK1_END 0x02ffffff
|
||||
#define CONFIG_SYS_BANK1_ENABLE 0
|
||||
#define CONFIG_SYS_BANK2_START 0x03f00000
|
||||
#define CONFIG_SYS_BANK2_END 0x03ffffff
|
||||
#define CONFIG_SYS_BANK2_ENABLE 0
|
||||
#define CONFIG_SYS_BANK3_START 0x04000000
|
||||
#define CONFIG_SYS_BANK3_END 0x04ffffff
|
||||
#define CONFIG_SYS_BANK3_ENABLE 0
|
||||
#define CONFIG_SYS_BANK4_START 0x05000000
|
||||
#define CONFIG_SYS_BANK4_END 0x05FFFFFF
|
||||
#define CONFIG_SYS_BANK4_ENABLE 0
|
||||
#define CONFIG_SYS_BANK5_START 0x06000000
|
||||
#define CONFIG_SYS_BANK5_END 0x06FFFFFF
|
||||
#define CONFIG_SYS_BANK5_ENABLE 0
|
||||
#define CONFIG_SYS_BANK6_START 0x07000000
|
||||
#define CONFIG_SYS_BANK6_END 0x07FFFFFF
|
||||
#define CONFIG_SYS_BANK6_ENABLE 0
|
||||
#define CONFIG_SYS_BANK7_START 0x08000000
|
||||
#define CONFIG_SYS_BANK7_END 0x08FFFFFF
|
||||
#define CONFIG_SYS_BANK7_ENABLE 0
|
||||
/*
|
||||
* Memory bank enable bitmask, specifying which of the banks defined above
|
||||
are actually present. MSB is for bank #7, LSB is for bank #0.
|
||||
*/
|
||||
#define CONFIG_SYS_BANK_ENABLE 0x01
|
||||
|
||||
#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
|
||||
/* see 8240 book for bit definitions */
|
||||
#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
|
||||
/* currently accessed page in memory */
|
||||
/* see 8240 book for details */
|
||||
|
||||
/* SDRAM 0 - 256MB */
|
||||
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* stack in DCACHE @ 1GB (no backing mem) */
|
||||
#if defined(USE_DINK32)
|
||||
#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
|
||||
#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#endif
|
||||
|
||||
/* PCI memory */
|
||||
#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
/* Flash, config addrs, etc */
|
||||
#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
|
||||
#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
|
||||
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
|
||||
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_CHECKSUM
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/* values according to the manual */
|
||||
|
||||
#define CONFIG_DRAM_50MHZ 1
|
||||
#define CONFIG_SDRAM_50MHZ
|
||||
|
||||
#define CONFIG_DISK_SPINUP_TIME 1000000
|
||||
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user