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Merge tag 'for-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next

Browse Source 
mpc83xx, keymile boards: enable DM_ETH and add DTS
  - mpc83xx: remove unneeded extern declaration in cpu_init
  - powerpc, qe: fix codingstyle issues for drivers/qe
  - powerpc, qe: add DTS support for parallel I/O ports
  - net, qe: add DM support for QE UEC ethernet
  - add DTS for all mpc83xx based boards from keymile
    mainly they are not mainlined to linux.
  - add u-boot specific dtsi
  - add stdout-path
  - add missing ucc4 par_io definitions, which were
    in board code, but not in linux DTS
  - remove not used ethernet nodes
This commit is contained in:
Tom Rini 2020-09-17 09:55:01 -04:00
commit ae52e75d23
58 changed files with 6815 additions and 1133 deletions
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8
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -101,34 +101,42 @@ config TARGET_IDS8313
config TARGET_KMETER1
bool "Support kmeter1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMCOGE5NE
bool "Support kmcoge5ne"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEGR1
bool "Support kmtegr1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUXX1
bool "Support tuxx1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMSUPX5
bool "Support kmsupx5"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TUGE1
bool "Support tuge1"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMOPTI2
bool "Support kmopti2"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_KMTEPR2
bool "Support kmtepr2"
select VENDOR_KM
select KM_ENABLE_FULL_DM_DTS_SUPPORT
config TARGET_TQM834X
bool "Support TQM834x"

2
arch/powerpc/cpu/mpc83xx/Makefile
View File

@ -27,7 +27,9 @@ obj-y += cpu_init.o
obj-y += speed.o
obj-y += interrupts.o
obj-y += ecc.o
ifndef CONFIG_PINCTRL
obj-$(CONFIG_QE) += qe_io.o
endif
obj-$(CONFIG_FSL_SERDES) += serdes.o
ifndef CONFIG_ARCH_MPC8308
obj-$(CONFIG_PCI) += pci.o

11
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -9,10 +9,14 @@
#include <ioports.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <fsl_qe.h>
#ifdef CONFIG_USB_EHCI_FSL
#include <usb/ehci-ci.h>
#endif
#include <linux/delay.h>
#ifdef CONFIG_QE
#include <fsl_qe.h>
#endif
#include "lblaw/lblaw.h"
#include "elbc/elbc.h"
@ -26,9 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
extern void qe_init(uint qe_base);
extern void qe_reset(void);
#if !defined(CONFIG_PINCTRL)
static void config_qe_ioports(void)
{
u8 port, pin;
@ -45,6 +48,7 @@ static void config_qe_ioports(void)
}
}
#endif
#endif
/*
* Breathe some life into the CPU...
@ -191,10 +195,13 @@ void cpu_init_f (volatile immap_t * im)
__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
#endif
#if !defined(CONFIG_PINCTRL)
#ifdef CONFIG_QE
/* Config QE ioports */
config_qe_ioports();
#endif
#endif
/* Set up preliminary BR/OR regs */
init_early_memctl_regs();

98
arch/powerpc/cpu/mpc83xx/qe_io.c
View File

@ -12,57 +12,93 @@
#include <asm/immap_83xx.h>
#define NUM_OF_PINS 32
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
/** qe_cfg_iopin configure one io pin setting
*
* @par_io: pointer to parallel I/O base
* @port: io pin port
* @pin: io pin number which get configured
* @dir: direction of io pin 2 bits valid
* 00 = pin disabled
* 01 = output
* 10 = input
* 11 = pin is I/O
* @open_drain: is pin open drain
* @assign: pin assignment registers select the function of the pin
*/
static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
int open_drain, int assign)
{
u32 pin_2bit_mask;
u32 pin_2bit_dir;
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
u32 dbit_mask;
u32 dbit_dir;
u32 dbit_asgn;
u32 bit_mask;
u32 tmp_val;
int offset;
offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
/* Calculate pin location and 2bit mask and dir */
pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
dbit_mask = (u32)(0x3 << offset);
dbit_dir = (u32)(dir << offset);
/* Setup the direction */
tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].dir2) :
in_be32(&par_io->ioport[port].dir1);
if (pin > (NUM_OF_PINS/2) -1) {
out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val);
if (pin > (NUM_OF_PINS / 2) - 1) {
out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
} else {
out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val);
out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
}
/* Calculate pin location for 1bit mask */
pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
/* Setup the open drain */
tmp_val = in_be32(&par_io->ioport[port].podr);
if (open_drain) {
out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val);
} else {
out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val);
}
if (open_drain)
out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
else
out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
/* Setup the assignment */
tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
in_be32(&par_io->ioport[port].ppar2):
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].ppar2) :
in_be32(&par_io->ioport[port].ppar1);
pin_2bit_assign = (u32)(assign
<< (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
dbit_asgn = (u32)(assign << offset);
/* Clear and set 2 bits mask */
if (pin > (NUM_OF_PINS/2) - 1) {
out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val);
if (pin > (NUM_OF_PINS / 2) - 1) {
out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
} else {
out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val);
out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
}
}
#if !defined(CONFIG_PINCTRL)
/** qe_config_iopin configure one io pin setting
*
* @port: io pin port
* @pin: io pin number which get configured
* @dir: direction of io pin 2 bits valid
* 00 = pin disabled
* 01 = output
* 10 = input
* 11 = pin is I/O
* @open_drain: is pin open drain
* @assign: pin assignment registers select the function of the pin
*/
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
}
#endif

8
arch/powerpc/dts/Makefile
View File

@ -1,5 +1,11 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb
dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb
dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb
dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb
dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb
@ -16,6 +22,8 @@ dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb
dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb

33
arch/powerpc/dts/km8309-uboot.dtsi Normal file
View File

@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA 8309 U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
cpus {
u-boot,dm-pre-reloc;
PowerPC,8309@0 {
u-boot,dm-pre-reloc;
};
};
chosen {
stdout-path = &serial0;
};
};
&qe {
compatible = "fsl,qe", "simple-bus";
};
&soc {
u-boot,dm-pre-reloc;
};
&serial0 {
clock-frequency = <132000000>;
u-boot,dm-pre-reloc;
};

67
arch/powerpc/dts/km8321-uboot.dtsi Normal file
View File

@ -0,0 +1,67 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA 8321 U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
cpus {
u-boot,dm-pre-reloc;
PowerPC,8321@0 {
u-boot,dm-pre-reloc;
};
};
chosen {
stdout-path = &serial0;
};
};
&enet_piggy2 {
status = "okay";
};
&qe {
compatible = "fsl,qe", "simple-bus";
};
&serial0 {
clock-frequency = <132000000>;
u-boot,dm-pre-reloc;
};
&soc {
u-boot,dm-pre-reloc;
par_io@1400 {
compatible = "fsl,mpc8360-par_io";
u-boot,dm-pre-reloc;
serial_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@1 {
u-boot,dm-pre-reloc;
};
ucc_pin@3 {
u-boot,dm-pre-reloc;
};
ucc_pin@4 {
u-boot,dm-pre-reloc;
};
ucc_pin@5 {
u-boot,dm-pre-reloc;
};
ucc_pin@6 {
u-boot,dm-pre-reloc;
};
ucc_pin@7 {
u-boot,dm-pre-reloc;
};
};
};

220
arch/powerpc/dts/km8321.dtsi Normal file
View File

@ -0,0 +1,220 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA km8321 common ports Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8321@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <16384>; // L1, 16K
i-cache-size = <16384>; // L1, 16K
timebase-frequency = <66000000>;
bus-frequency = <264000000>;
clock-frequency = <528000000>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
soc: soc8321@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <264000000>;
i2c0: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8313-i2c","fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <100000>;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8321-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0x80 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0x100 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8321-dma-channel",
"fsl,elo-dma-channel";
reg = <0x180 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "fsl,pq2pro-pic", "fsl,ipic";
interrupt-controller;
reg = <0x700 0x100>;
device_type = "ipic";
};
par_io: par_io@1400 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1400 0x100>;
ranges;
device_type = "par_io";
num-ports = <7>;
qe_pio_d: gpio-controller@48 {
#gpio-cells = <2>;
compatible = "fsl,mpc8360-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x1448 0x18>;
gpio-controller;
};
};
};
qe: qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0x0 0xe0100000 0x00100000>;
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <396000000>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x00004000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x4000>;
};
};
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
enet_piggy2: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk17";
phy-handle = <&phy_piggy2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc4>;
};
mdio: mdio@3320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3320 0x18>;
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
phy_piggy2: ethernet-phy@00 {
reg = <0x0>;
device_type = "ethernet-phy";
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <32 8 33 8>;
interrupt-parent = <&ipic>;
};
bootcount@0x13ff8 {
device_type = "bootcount";
compatible = "u-boot,bootcount";
reg = <0x13ff8 0x08>;
};
spi0: spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "qe";
#address-cells = <1>;
#size-cells = <0>;
pio-handle = <&pio_spi>;
};
};
localbus: localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
};
};
#include "km8321-uboot.dtsi"

61
arch/powerpc/dts/km836x-uboot.dtsi Normal file
View File

@ -0,0 +1,61 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA km836x U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
cpus {
u-boot,dm-pre-reloc;
PowerPC,8360@0 {
u-boot,dm-pre-reloc;
};
};
chosen {
stdout-path = &serial0;
};
};
&qe {
compatible = "fsl,qe", "simple-bus";
};
&soc {
u-boot,dm-pre-reloc;
par_io@1400 {
u-boot,dm-pre-reloc;
serial_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@0 {
u-boot,dm-pre-reloc;
};
ucc_pin@1 {
u-boot,dm-pre-reloc;
};
ucc_pin@3 {
u-boot,dm-pre-reloc;
};
ucc_pin@4 {
u-boot,dm-pre-reloc;
};
ucc_pin@5 {
u-boot,dm-pre-reloc;
};
ucc_pin@6 {
u-boot,dm-pre-reloc;
};
ucc_pin@7 {
u-boot,dm-pre-reloc;
};
};
};
&serial0 {
u-boot,dm-pre-reloc;
};

182
arch/powerpc/dts/km836x.dtsi Normal file
View File

@ -0,0 +1,182 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA km836x common ports Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8360@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; /* 32 bytes */
i-cache-line-size = <32>; /* 32 bytes */
d-cache-size = <32768>; /* L1, 32K */
i-cache-size = <32768>; /* L1, 32K */
timebase-frequency = <0>; /* Filled in by U-Boot */
bus-frequency = <0>; /* Filled in by U-Boot */
clock-frequency = <0>; /* Filled in by U-Boot */
};
};
memory {
device_type = "memory";
reg = <0 0>; /* Filled in by U-Boot */
};
soc: soc8360@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8360-immr", "simple-bus";
ranges = <0x0 0xe0000000 0x00200000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <0>;/* Filled in by U-Boot */
/* power management control module*/
pmc: power@b00 {
compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
reg = <0xb00 0x100 0xa00 0x100>;
interrupts = <80 0x8>;
interrupt-parent = <&ipic>;
};
i2c0: i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8313-i2c","fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <100000>;
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
status = "disabled";
};
serial1: serial@4600 {
cell-index = <1>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4600 0x100>;
clock-frequency = <133333333>;
interrupts = <10 0x8>;
interrupt-parent = <&ipic>;
status = "disabled";
};
ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "fsl,pq2pro-pic", "fsl,ipic";
interrupt-controller;
reg = <0x700 0x100>;
};
par_io: par_io@1400 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1400 0x100>;
ranges;
compatible = "fsl,mpc8360-par_io";
device_type = "par_io";
num-ports = <7>;
qe_pio_c: gpio-controller@30 {
#gpio-cells = <2>;
compatible = "fsl,mpc8360-qe-pario-bank",
"fsl,mpc8323-qe-pario-bank";
reg = <0x1430 0x18>;
gpio-controller;
};
};
qe: qe@100000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe";
ranges = <0x0 0x100000 0x100000>;
reg = <0x100000 0x480>;
clock-frequency = <0>; /* Filled in by U-Boot */
brg-frequency = <0>; /* Filled in by U-Boot */
bus-frequency = <0>; /* Filled in by U-Boot */
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x0000c000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0xc000>;
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <
32 0x8 /* ucc1 */
33 0x8 /* ucc2 */
34 0x8 /* ucc3 */
35 0x8 /* ucc4 */
40 0x8 /* ucc1 */
>;
interrupt-parent = <&ipic>;
};
spi0: spi@4c0 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x4c0 0x40>;
interrupts = <2>;
interrupt-parent = <&qeic>;
mode = "qe";
#address-cells = <1>;
#size-cells = <0>;
pio-handle = <&pio_spi>;
};
bootcount@0x1bff8 {
device_type = "bootcount";
compatible = "u-boot,bootcount";
reg = <0x1bff8 0x08>;
};
};
};
localbus: localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
};
};
#include "km836x-uboot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
aliases {
/delete-property/ ethernet1;
/delete-property/ ethernet2;
};
};
&enet_switch {
status = "disabled";
};
&enet_mate {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA KMCOGE5ne Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km836x.dtsi"
/ {
model = "kmcoge5ne";
compatible = "ABB,kmcoge5ne";
aliases {
ethernet0 = &enet_admin;
ethernet1 = &enet_mate;
ethernet2 = &enet_switch;
serial0 = &serial0;
};
};
&soc {
/* brg for hdlc clk */
brg@0 {
compatible = "fsl,mpc-brg";
brg-name = "brg16";
brg-frequency = <20000000>; /* 20 MHz */
pio-handle = <&pio_brg>;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the fan unit */
fanu-ivm@50 {
label = "FANUV";
compatible = "dummy";
reg = <0x50>;
};
/* fan unit (GPIOs and so on) */
fanu@20 {
label = "FANUV_CTRL";
compatible = "dummy";
reg = <0x20>;
};
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
backplane@50 {
label = "BP_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
};
};
&serial0 {
status = "okay";
};
&par_io {
pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */
0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */
0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */
0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */
0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */
0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */
0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */
0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */
0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */
0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */
0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */
2 9 1 0 3 0 /* GTX_CLK (CLK10) */
2 8 2 0 1 0 /* GTX125 (CLK9) */
>;
};
pio_ucc4: ucc_pin@3 { /* RMII, admin front port */
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */
0 2 1 0 1 0 /* MDC (PA2, in, f1) */
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */
4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */
4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */
>;
};
pio_brg: brg_pin@0 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 25 1 0 1 0 /* BRG (PC25, out, f1) */
>;
};
pio_tdm: tdm_pin@00 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
/* TDMa */
0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
/* TDMb */
0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
/* TDMc */
1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
/* TDMd */
1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
/* TDMe */
3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
/* TDMf */
3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
/* TDMg */
4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
/* TDMh */
4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
/* RxTxClk0/1 */
2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
/* RxTxSync0/1 */
2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
};
};
&qe {
/* mng-switch port (UCC1, MDIO 0x10, RGMII) */
enet_switch: ethernet@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk9";
/*id=0, full-dup, 1G, no-pause, no-asym_p*/
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc1>;
};
/* admin and debug port (UCC4, MDIO 0x00, RMII) */
enet_admin: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk17";
phy-handle = <&phy_admin>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc4>;
};
/* mate backplane port (UCC5, MDIO 0x08, RMII) */
enet_mate: ucc@2400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <5>;
reg = <0x2400 0x200>;
interrupts = <40>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_mate>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc5>;
};
mdio@3320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3320 0x18>;
compatible = "fsl,ucc-mdio";
/* admin front port (UCC4, MDIO 0x00, RMII) */
phy_admin: ethernet-phy@00 {
reg = <0x0>;
};
/* mate bp port (UCC5, MDIO 0x08, RMII) */
phy_mate: ethernet-phy@08 {
reg = <0x08>;
};
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000
1 0 0xe8000000 0x01000000
3 0 0xa0000000 0x10000000
4 0 0xb0000000 0x10000000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x04000000>;
nornand = "nor";
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xC0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xE0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};
#include "kmcoge5ne-uboot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA kmeter1 U-Boot specific Device Tree Source parts
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/ {
aliases {
/delete-property/ ethernet1;
/delete-property/ ethernet2;
/delete-property/ ethernet3;
/delete-property/ ethernet4;
/delete-property/ ethernet5;
/delete-property/ ethernet6;
};
};
&enet_estar1 {
status = "disabled";
};
&enet_estar2 {
status = "disabled";
};
&enet_eth1 {
status = "disabled";
};
&enet_eth2 {
status = "disabled";
};
&enet_eth3 {
status = "disabled";
};
&enet_eth4 {
status = "disabled";
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA KMETER1 Device Tree Source
*
* 2008-2011 DENX Software Engineering GmbH
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*/
/dts-v1/;
#include "km836x.dtsi"
/ {
model = "KMETER1";
compatible = "ABB,KMETER1";
aliases {
ethernet0 = &enet_piggy2;
ethernet1 = &enet_estar1;
ethernet2 = &enet_estar2;
ethernet3 = &enet_eth1;
ethernet4 = &enet_eth2;
ethernet5 = &enet_eth3;
ethernet6 = &enet_eth4;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@48 {
label = "Top";
compatible = "national,lm75";
reg = <0x48>;
};
temp@49 {
label = "Control";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "Power";
compatible = "national,lm75";
reg = <0x4a>;
};
temp@4b {
label = "Front";
compatible = "national,lm75";
reg = <0x4b>;
};
};
};
};
&serial0 {
status = "okay";
};
&par_io {
pio_ucc1: ucc_pin@0 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
0 3 1 0 1 0 /* TxD0 */
0 4 1 0 1 0 /* TxD1 */
0 5 1 0 1 0 /* TxD2 */
0 6 1 0 1 0 /* TxD3 */
0 9 2 0 1 0 /* RxD0 */
0 10 2 0 1 0 /* RxD1 */
0 11 2 0 1 0 /* RxD2 */
0 12 2 0 1 0 /* RxD3 */
0 7 1 0 1 0 /* TX_EN */
0 8 1 0 1 0 /* TX_ER */
0 15 2 0 1 0 /* RX_DV */
0 16 2 0 1 0 /* RX_ER */
0 0 2 0 1 0 /* RX_CLK */
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
2 8 2 0 1 0 /* GTX125 - CLK9 */
>;
};
pio_ucc2: ucc_pin@1 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
0 17 1 0 1 0 /* TxD0 */
0 18 1 0 1 0 /* TxD1 */
0 19 1 0 1 0 /* TxD2 */
0 20 1 0 1 0 /* TxD3 */
0 23 2 0 1 0 /* RxD0 */
0 24 2 0 1 0 /* RxD1 */
0 25 2 0 1 0 /* RxD2 */
0 26 2 0 1 0 /* RxD3 */
0 21 1 0 1 0 /* TX_EN */
0 22 1 0 1 0 /* TX_ER */
0 29 2 0 1 0 /* RX_DV */
0 30 2 0 1 0 /* RX_ER */
0 31 2 0 1 0 /* RX_CLK */
2 2 1 0 2 0 /* GTX_CLK - CLK3 */
2 3 2 0 1 0 /* GTX125 - CLK4 */
>;
};
pio_ucc4: ucc_pin@3 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_ucc5: ucc_pin@4 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
>;
};
pio_ucc6: ucc_pin@5 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
>;
};
pio_ucc7: ucc_pin@6 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
>;
};
pio_ucc8: ucc_pin@7 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
0 1 3 0 2 0 /* MDIO */
0 2 1 0 1 0 /* MDC */
4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */
4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */
>;
};
/* UCC3 as HDLC controller for ICN */
pio5: ucc_pin@02 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
1 0 1 0 1 0 /* TxD0 */
1 6 2 0 1 0 /* RxD0 */
1 12 2 0 1 0 /* CTS */
2 11 2 0 1 0 /* TX-CLK12 */
>;
};
pio_tdm: tdm_pin@00 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
/* TDMa */
0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */
0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */
0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */
2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */
/* TDMb */
0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */
0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */
0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */
2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */
/* TDMc */
1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */
1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */
1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */
2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */
/* TDMd */
1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */
1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */
1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */
2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */
/* TDMe */
3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */
3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */
3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */
2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */
/* TDMf */
3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */
3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */
3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */
2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */
/* TDMg */
4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */
4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */
4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */
2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */
/* TDMh */
4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */
4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */
4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */
2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */
/* RxTxClk0/1 */
2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */
2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */
/* RxTxSync0/1 */
2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */
2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */
};
};
&qe {
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
enet_estar1: ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk9";
phy-handle = <&phy_estar1>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc1>;
};
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
enet_estar2: ucc@3000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <2>;
reg = <0x3000 0x200>;
interrupts = <33>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk4";
phy-handle = <&phy_estar2>;
phy-connection-type = "rgmii-id";
pio-handle = <&pio_ucc2>;
};
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
enet_piggy2: ucc@3200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <4>;
reg = <0x3200 0x200>;
interrupts = <35>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk17";
phy-handle = <&phy_piggy2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc4>;
};
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
enet_eth1: ucc@2400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <5>;
reg = <0x2400 0x200>;
interrupts = <40>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth1>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc5>;
};
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
enet_eth2: ucc@3400 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <6>;
reg = <0x3400 0x200>;
interrupts = <41>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth2>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc6>;
};
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
enet_eth3: ucc@2600 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <7>;
reg = <0x2600 0x200>;
interrupts = <42>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth3>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc7>;
};
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
enet_eth4: ucc@3600 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <8>;
reg = <0x3600 0x200>;
interrupts = <43>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk16";
phy-handle = <&phy_eth4>;
phy-connection-type = "rmii";
pio-handle = <&pio_ucc8>;
};
mdio@3320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3320 0x18>;
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC4, MDIO 0x00, RMII) */
phy_piggy2: ethernet-phy@0 {
reg = <0x0>;
};
/* Eth-1 (UCC5, MDIO 0x08, RMII) */
phy_eth1: ethernet-phy@8 {
reg = <0x08>;
};
/* Eth-2 (UCC6, MDIO 0x09, RMII) */
phy_eth2: ethernet-phy@9 {
reg = <0x09>;
};
/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
phy_eth3: ethernet-phy@a {
reg = <0x0a>;
};
/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
phy_eth4: ethernet-phy@b {
reg = <0x0b>;
};
/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
phy_estar1: ethernet-phy@10 {
interrupt-parent = <&ipic>;
interrupts = <17 0x8>;
reg = <0x10>;
};
/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
phy_estar2: ethernet-phy@11 {
interrupt-parent = <&ipic>;
interrupts = <18 0x8>;
reg = <0x11>;
};
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
1 0 0xe8000000 0x01000000 /* LB 1 */
3 0 0xa0000000 0x10000000>; /* LB 3 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x04000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xC0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xE0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};
#include "kmeter1-uboot.dtsi"

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA OPTI2 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "KMOPTI2";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "power";
compatible = "national,lm75";
reg = <0x4a>;
};
};
i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@4 {
reg = <4>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */
3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */
3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000 /* LB 2 PAXE */
3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
use-advanced-sector-protection;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA SUPC5 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "SUPC5";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
/* UCC4_RMII_CLK (CLK17) */
3 10 2 0 3 0
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
* port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&spi0 {
pio-handle = <&pio_spi>;
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA SUPM5 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "SUPM5";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */
3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */
3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TEGR1 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
/ {
model = "KMTEGR1";
compatible = "ABB,kmpbec8309";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_zynq;
ethernet1 = &enet_piggy2;
serial0 = &serial0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8309@0 {
device_type = "cpu";
reg = <0x0>;
d-cache-line-size = <32>; // 32 bytes
i-cache-line-size = <32>; // 32 bytes
d-cache-size = <16384>; // L1, 16K
i-cache-size = <16384>; // L1, 16K
timebase-frequency = <66000000>;
bus-frequency = <264000000>;
clock-frequency = <264000000>;
};
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>;
};
soc: soc8309@e0000000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0xe0000000 0x00100000>;
reg = <0xe0000000 0x00000200>;
bus-frequency = <264000000>;
i2c@3000 {
#address-cells = <1>;
#size-cells = <0>;
cell-index = <0>;
compatible = "fsl,mpc8313-i2c","fsl-i2c";
reg = <0x3000 0x100>;
interrupts = <14 0x8>;
interrupt-parent = <&ipic>;
clock-frequency = <400000>;
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/*
* Inventory EEPROM of the
* unit itself
*/
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@48 {
label = "front";
compatible = "national,lm75";
reg = <0x48>;
};
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "power";
compatible = "national,lm75";
reg = <0x4a>;
};
temp@4b {
label = "bottom";
compatible = "national,lm75";
reg = <0x4b>;
};
};
i2c@6 {
reg = <6>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@5 {
reg = <5>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@7 {
reg = <7>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
serial0: serial@4500 {
cell-index = <0>;
device_type = "serial";
compatible = "fsl,ns16550", "ns16550";
reg = <0x4500 0x100>;
clock-frequency = <264000000>;
interrupts = <9 0x8>;
interrupt-parent = <&ipic>;
};
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8309-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a8>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0x80 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0x100 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8309-dma-channel",
"fsl,elo-dma-channel";
reg = <0x180 0x28>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
ipic: pic@700 {
#address-cells = <0>;
#interrupt-cells = <2>;
compatible = "fsl,pq2pro-pic", "fsl,ipic";
interrupt-controller;
reg = <0x700 0x100>;
device_type = "ipic";
};
gpio1: gpio-controller@c00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
reg = <0xc00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio-controller@d00 {
#gpio-cells = <2>;
compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio";
reg = <0xd00 0x100>;
interrupts = <75 0x8>;
interrupt-parent = <&ipic>;
gpio-controller;
interrupt-controller;
#interrupt-cells = <2>;
};
spi@7000 {
cell-index = <0>;
compatible = "fsl,spi";
reg = <0x7000 0x1000>;
interrupts = <16 0x8>;
interrupt-parent = <&ipic>;
mode = "cpu";
#address-cells = <1>;
#size-cells = <0>;
/* GPIO_15 chipselect for ZYNQ flash */
gpios = <&gpio1 15 0>;
zynq_flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,m25p80";
reg = <0>;
spi-max-frequency = <4000000>;
m25p,fast-read;
partition@0 {
label = "bootloader";
reg = <0x0 0x01000000>;
};
};
};
};
qe: qe@e0100000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "qe";
compatible = "fsl,qe";
ranges = <0x0 0xe0100000 0x00100000>;
reg = <0xe0100000 0x480>;
brg-frequency = <0>;
bus-frequency = <396000000>;
fsl,qe-num-snums = <32>;
muram@10000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,qe-muram", "fsl,cpm-muram";
ranges = <0x0 0x00010000 0x00004000>;
data-only@0 {
compatible = "fsl,qe-muram-data",
"fsl,cpm-muram-data";
reg = <0x0 0x4000>;
};
};
/* ZYNQ (UCC1, MDIO 0x10, MII) */
enet_zynq: ethernet@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <0x2000 0x200>;
interrupts = <32>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
/*id=0, full-dup, 100M, no-pause, no-asym_p*/
fixed-link = <0 1 100 0 0>;
rx-clock-name = "clk9";
tx-clock-name = "clk10";
phy-connection-type = "mii";
};
/* Piggy2 (UCC3, MDIO 0x00, RMII) */
enet_piggy2: ucc@2200 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <3>;
reg = <0x2200 0x200>;
interrupts = <34>;
interrupt-parent = <&qeic>;
local-mac-address = [ 00 00 00 00 00 00 ];
rx-clock-name = "none";
tx-clock-name = "clk12";
phy-handle = <&phy_piggy2>;
phy-connection-type = "rmii";
};
mdio@2320 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2320 0x38>;
compatible = "fsl,ucc-mdio";
/* Piggy2 (UCC3, MDIO 0x00, RMII) */
phy_piggy2: ethernet-phy@0 {
reg = <0x0>;
device_type = "ethernet-phy";
};
/* Explicitly set the tbi-phy to a non-zero address
* so that it does not conflict with phy_piggy2 that
* is unfortunately at address 0
*/
tbi1: tbi-phy@1 {
reg = <0x1>;
device_type = "tbi-phy";
};
};
qeic: interrupt-controller@80 {
interrupt-controller;
compatible = "fsl,qe-ic";
#address-cells = <0>;
#interrupt-cells = <1>;
reg = <0x80 0x80>;
big-endian;
interrupts = <32 8 33 8>;
interrupt-parent = <&ipic>;
};
bootcount@0x13ff8 {
device_type = "bootcount";
compatible = "u-boot,bootcount";
reg = <0x13ff8 0x08>;
};
};
localbus@e0005000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus",
"simple-bus";
reg = <0xe0005000 0xd8>;
ranges = <0 0 0xf0000000 0x04000000
1 0 0xe8000000 0x01000000
2 0 0xe0000000 0x10000000
3 0 0xb0000000 0x10000000>;
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
nornand = "nor";
#address-cells = <1>;
#size-cells = <1>;
use-advanced-sector-protection;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xc0000>;
};
partition@c0000 { /* 256KB */
label = "qe-fw";
reg = <0xc0000 0x40000>;
};
partition@100000 { /* 128KB */
label = "env";
reg = <0x100000 0x20000>;
};
partition@120000 { /* 128KB */
label = "envred";
reg = <0x120000 0x20000>;
};
partition@140000 { /* 64256KB */
label = "ubi0";
reg = <0x140000 0x3EC0000>;
};
};
};
};
#include "km8309-uboot.dtsi"

142
arch/powerpc/dts/kmtepr2.dts Normal file
View File

@ -0,0 +1,142 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TEPR2 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "KMTEPR2";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&i2c0 {
mux@70 {
compatible = "nxp,pca9547";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* Inventory EEPROM of the unit itself */
ivm@50 {
label = "MAIN_CTRL";
compatible = "dummy";
reg = <0x50>;
};
};
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
/* Temperature sensors */
temp@49 {
label = "board";
compatible = "national,lm75";
reg = <0x49>;
};
temp@4a {
label = "power";
compatible = "national,lm75";
reg = <0x4a>;
};
};
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
*port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */
3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
use-advanced-sector-protection;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

100
arch/powerpc/dts/kmtuge1.dts Normal file
View File

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TUGE1 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "TUGE1";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
*port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000>; /* LB 2 PAXI */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

100
arch/powerpc/dts/kmtuxa1.dts Normal file
View File

@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ABB PGGA TUXA1 Device Tree Source
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "km8321.dtsi"
/ {
model = "TUXA1";
compatible = "ABB,kmpbec8321";
#address-cells = <1>;
#size-cells = <1>;
aliases {
ethernet0 = &enet_piggy2;
serial0 = &serial0;
};
};
&par_io {
/* UCC5 as HDLC controller for ICN */
pio_ucc5: ucc_pin@04 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
2 0 1 0 2 0 /* TxD0 */
2 8 2 0 2 0 /* RxD0 */
2 29 2 0 2 0 /* CTS */
3 30 2 0 1 0 /* ICN CLK */
>;
};
/* UCC4 Piggy Ethernet */
pio_ucc4: ucc_pin@03 {
pio-map = <
/* port pin dir open_drain assignment has_irq */
3 4 3 0 2 0 /* MDIO */
3 5 1 0 2 0 /* MDC */
1 18 1 0 1 0 /* TxD0 */
1 19 1 0 1 0 /* TxD1 */
1 22 2 0 1 0 /* RxD0 */
1 23 2 0 1 0 /* RxD1 */
1 26 2 0 1 0 /* RX_ER */
1 28 2 0 1 0 /* RX_DV */
1 30 1 0 1 0 /* TX_EN */
1 31 2 0 1 0 /* CRS */
3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */
>;
};
pio_spi: spi_pin@01 {
pio-map = <
/*
*port pin dir open_drain assignment has_irq
* SPI_MOSI (PD0, bi, f3)
*/
3 0 3 0 1 0
/* SPI_MISO (PD1, bi, f3) */
3 1 3 0 1 0
/* SPI_CLK (PD2, bi, f3) */
3 2 3 0 1 0
>;
};
};
&localbus {
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */
1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */
2 0 0xa0000000 0x10000000 /* LB 2 LPXF */
3 0 0xb0000000 0x10000000>; /* LB 3 PINC2 */
flash@0,0 {
compatible = "cfi-flash";
reg = <0 0x00000000 0x04000000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 { /* 768KB */
label = "u-boot";
reg = <0 0xC0000>;
};
partition@c0000 { /* 128KB */
label = "env";
reg = <0xc0000 0x20000>;
};
partition@e0000 { /* 128KB */
label = "envred";
reg = <0xe0000 0x20000>;
};
partition@100000 { /* 64512KB */
label = "ubi0";
reg = <0x100000 0x3F00000>;
};
};
};

17
board/keymile/km83xx/Kconfig
View File

@ -1,3 +1,20 @@
menu "KM 83xx Options"
depends on MPC83xx
config KM_ENABLE_FULL_DM_DTS_SUPPORT
bool "enable full DM/DTS support for KM 83xx boards"
default y
select CMD_DM
select DM
select DM_ETH
select DM_MDIO
select DM_SERIAL
select OF_CONTROL
select PINCTRL
select PINCTRL_QE
select PHYLIB
endmenu
if TARGET_KMETER1
config SYS_BOARD

23
board/keymile/km83xx/MAINTAINERS
View File

@ -1,5 +1,6 @@
KM83XX BOARD
M: Holger Brunck <holger.brunck@hitachi-powergrids.com>
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: board/keymile/km83xx/
F: include/configs/km8360.h
@ -7,12 +8,24 @@ F: configs/kmcoge5ne_defconfig
F: configs/kmeter1_defconfig
F: include/configs/tuxx1.h
F: configs/kmopti2_defconfig
F: configs/kmsupx5_defconfig
F: configs/kmtepr2_defconfig
F: configs/kmtegr1_defconfig
F: configs/tuge1_defconfig
F: configs/tuxx1_defconfig
KMSUPX5 BOARD
M: Heiko Schocher <hs@denx.de>
S: Maintained
F: configs/kmsupx5_defconfig
F: arch/powerpc/dts/km8309-uboot.dtsi
F: arch/powerpc/dts/km8321-uboot.dtsi
F: arch/powerpc/dts/km8321.dtsi
F: arch/powerpc/dts/km836x-uboot.dtsi
F: arch/powerpc/dts/km836x.dtsi
F: arch/powerpc/dts/kmcoge5ne-uboot.dtsi
F: arch/powerpc/dts/kmcoge5ne.dts
F: arch/powerpc/dts/kmeter1-uboot.dtsi
F: arch/powerpc/dts/kmeter1.dts
F: arch/powerpc/dts/kmopti2.dts
F: arch/powerpc/dts/kmsupc5.dts
F: arch/powerpc/dts/kmsupm5.dts
F: arch/powerpc/dts/kmtegr1.dts
F: arch/powerpc/dts/kmtepr2.dts
F: arch/powerpc/dts/kmtuge1.dts
F: arch/powerpc/dts/kmtuxa1.dts

64
board/keymile/km83xx/km83xx.c
View File

@ -36,70 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
#if defined(CONFIG_ARCH_MPC8360)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
/* UCC4 - UEC */
{1, 14, 1, 0, 1}, /* TxD0 */
{1, 15, 1, 0, 1}, /* TxD1 */
{1, 20, 2, 0, 1}, /* RxD0 */
{1, 21, 2, 0, 1}, /* RxD1 */
{1, 18, 1, 0, 1}, /* TX_EN */
{1, 26, 2, 0, 1}, /* RX_DV */
{1, 27, 2, 0, 1}, /* RX_ER */
{1, 24, 2, 0, 1}, /* COL */
{1, 25, 2, 0, 1}, /* CRS */
{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
/* DUART - UART2 */
{5, 0, 1, 0, 2}, /* UART2_SOUT */
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
#elif !defined(CONFIG_ARCH_MPC8309)
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
{0, 18, 1, 0, 3}, /* LA02 */
{0, 19, 1, 0, 3}, /* LA03 */
{0, 20, 1, 0, 3}, /* LA04 */
{0, 21, 1, 0, 3}, /* LA05 */
{0, 22, 1, 0, 3}, /* LA06 */
{0, 23, 1, 0, 3}, /* LA07 */
{0, 24, 1, 0, 3}, /* LA08 */
{0, 25, 1, 0, 3}, /* LA09 */
{0, 26, 1, 0, 3}, /* LA10 */
{0, 27, 1, 0, 3}, /* LA11 */
{0, 28, 1, 0, 3}, /* LA12 */
{0, 29, 1, 0, 3}, /* LA13 */
{0, 30, 1, 0, 3}, /* LA14 */
{0, 31, 1, 0, 3}, /* LA15 */
/* MDIO */
{3, 4, 3, 0, 2}, /* MDIO */
{3, 5, 1, 0, 2}, /* MDC */
/* UCC4 - UEC */
{1, 18, 1, 0, 1}, /* TxD0 */
{1, 19, 1, 0, 1}, /* TxD1 */
{1, 22, 2, 0, 1}, /* RxD0 */
{1, 23, 2, 0, 1}, /* RxD1 */
{1, 26, 2, 0, 1}, /* RxER */
{1, 28, 2, 0, 1}, /* Rx_DV */
{1, 30, 1, 0, 1}, /* TxEN */
{1, 31, 2, 0, 1}, /* CRS */
{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
#endif
/* END of table */
{0, 0, 0, 0, QE_IOP_TAB_END},
};
static int piggy_present(void)
{
struct km_bec_fpga __iomem *base =

11
configs/kmcoge5ne_defconfig
View File

@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth1"
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmcoge5ne"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMCOGE5NE=y
@ -156,7 +156,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
@ -173,6 +172,7 @@ CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -186,8 +186,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -197,8 +198,10 @@ CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y

10
configs/kmeter1_defconfig
View File

@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth2"
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmeter1"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMETER1=y
@ -120,7 +120,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_EADC_2=y
CONFIG_LCRR_CLKDIV_4=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
@ -136,6 +135,7 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -149,8 +149,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -159,7 +160,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

11
configs/kmopti2_defconfig
View File

@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmopti2"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMOPTI2=y
@ -139,7 +139,6 @@ CONFIG_ACR_APARK_MASTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
@ -155,6 +154,7 @@ CONFIG_CMD_ASKENV=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
@ -168,8 +168,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -178,7 +179,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

10
configs/kmsupx5_defconfig
View File

@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmsupm5"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMSUPX5=y
@ -119,7 +119,6 @@ CONFIG_ACR_APARK_MASTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
@ -148,8 +147,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -158,7 +158,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

12
configs/kmtegr1_defconfig
View File

@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth1"
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmtegr1"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMTEGR1=y
@ -118,7 +118,6 @@ CONFIG_ACR_APARK_MASTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1"
@ -150,8 +149,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF0100000
CONFIG_ENV_ADDR_REDUND=0xF0120000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -161,9 +161,13 @@ CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
CONFIG_SYS_NS16550=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y

10
configs/kmtepr2_defconfig
View File

@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmtepr2"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_KMTEPR2=y
@ -139,7 +139,6 @@ CONFIG_ACR_APARK_MASTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
@ -168,8 +167,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -178,7 +178,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

10
configs/tuge1_defconfig
View File

@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmtuge1"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_TUGE1=y
@ -119,7 +119,6 @@ CONFIG_ACR_APARK_MASTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
@ -148,8 +147,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -158,7 +158,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

11
configs/tuxx1_defconfig
View File

@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_DEFAULT_DEVICE_TREE="kmtuxa1"
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_TUXX1=y
@ -141,7 +141,6 @@ CONFIG_ACR_APARK_MASTER=y
CONFIG_ACR_PARKM_USB_I2C1_BOOT=y
CONFIG_LCRR_EADC_1=y
CONFIG_LCRR_CLKDIV_2=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_MISC_INIT_R=y
@ -170,8 +169,9 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xF00C0000
CONFIG_ENV_ADDR_REDUND=0xF00E0000
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
@ -180,7 +180,10 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_SMSC=y
CONFIG_DM_ETH_PHY=y
CONFIG_QE_UEC=y
# CONFIG_PCI is not set
# CONFIG_PINCTRL_FULL is not set
CONFIG_QE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

53
doc/device-tree-bindings/soc/fsl/cpm_qe/qe/ucc.txt Normal file
View File

@ -0,0 +1,53 @@
* UCC (Unified Communications Controllers)
Required properties:
- compatible : ucc_geth
- cell-index : the ucc number(1-8), corresponding to UCCx in UM.
- reg : Offset and length of the register set for the device
- rx-clock-name: the UCC receive clock source
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
- tx-clock-name: the UCC transmit clock source
"none": clock source is disabled
"brg1" through "brg16": clock source is BRG1-BRG16, respectively
"clk1" through "clk24": clock source is CLK1-CLK24, respectively
The following two properties are deprecated. rx-clock has been replaced
with rx-clock-name, and tx-clock has been replaced with tx-clock-name.
Drivers that currently use the deprecated properties should continue to
do so, in order to support older device trees, but they should be updated
to check for the new properties first.
- rx-clock : represents the UCC receive clock source.
0x00 : clock source is disabled;
0x1~0x10 : clock source is BRG1~BRG16 respectively;
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
- tx-clock: represents the UCC transmit clock source;
0x00 : clock source is disabled;
0x1~0x10 : clock source is BRG1~BRG16 respectively;
0x11~0x28: clock source is QE_CLK1~QE_CLK24 respectively.
- phy-handle : The phandle for the PHY connected to this controller.
- phy-connection-type : a string naming the controller/PHY interface type,
i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
Delay), "rgmii-txid" (delay on TX only), "rgmii-rxid" (delay on RX only),
"tbi", or "rtbi".
- pio-handle : The phandle for the Parallel I/O port configuration.
Deprecated properties:
- device-id : the ucc number(1-8), corresponding to UCCx in UM.
you should use cell-index
Example:
ucc@2000 {
device_type = "network";
compatible = "ucc_geth";
cell-index = <1>;
reg = <2000 200>;
interrupts = <a0 0>;
interrupt-parent = <700>;
mac-address = [ 00 04 9f 00 23 23 ];
rx-clock = "none";
tx-clock = "clk9";
phy-handle = <212000>;
phy-connection-type = "gmii";
pio-handle = <140001>;
};

2
drivers/net/Kconfig
View File

@ -432,6 +432,8 @@ config PCNET
This driver supports AMD PCnet series fast ethernet family of
PCI chipsets/adapters.
source "drivers/net/qe/Kconfig"
config RTL8139
bool "Realtek 8139 series Ethernet controller driver"
help

1
drivers/net/Makefile
View File

@ -78,6 +78,7 @@ obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-y += qe/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o

9
drivers/net/qe/Kconfig Normal file
View File

@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2020 Heiko Schocher <hs@denx.de>
config QE_UEC
bool "NXP QE UEC Ethernet controller"
depends on DM_ETH
help
This driver supports the NXP QE UEC ethernet controller

5
drivers/net/qe/Makefile Normal file
View File

@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2020 Heiko Schocher <hs@denx.de>
obj-$(CONFIG_QE_UEC) += dm_qe_uec.o dm_qe_uec_phy.o uccf.o

1167
drivers/net/qe/dm_qe_uec.c Normal file
View File

File diff suppressed because it is too large Load Diff

22
drivers/net/qe/dm_qe_uec.h Normal file
View File

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0+
*
* QE UEC ethernet controller driver
*
* based on drivers/qe/uec.c from NXP
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*/
#ifndef _DM_QE_UEC_H
#define _DM_QE_UEC_H
#define qe_uec_dbg(dev, fmt, args...) debug("%s:" fmt, dev->name, ##args)
#include "uec.h"
/* QE UEC private structure */
struct qe_uec_priv {
struct uec_priv *uec;
struct phy_device *phydev;
};
#endif

163
drivers/net/qe/dm_qe_uec_phy.c Normal file
View File

@ -0,0 +1,163 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* QE UEC ethernet phy controller driver
*
* based on phy parts of drivers/qe/uec.c and drivers/qe/uec_phy.c
* from NXP
*
* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/io.h>
#include <linux/ioport.h>
#include "dm_qe_uec.h"
struct qe_uec_mdio_priv {
struct ucc_mii_mng *base;
};
static int
qe_uec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
{
struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
struct ucc_mii_mng *regs = priv->base;
u32 tmp_reg;
u16 value;
debug("%s: regs: %p addr: %x devad: %x reg: %x\n", __func__, regs,
addr, devad, reg);
/* Setting up the MII management Address Register */
tmp_reg = ((u32)addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg;
out_be32(&regs->miimadd, tmp_reg);
/* clear MII management command cycle */
out_be32(&regs->miimcom, 0);
sync();
/* Perform an MII management read cycle */
out_be32(&regs->miimcom, MIIMCOM_READ_CYCLE);
/* Wait till MII management write is complete */
while ((in_be32(&regs->miimind)) &
(MIIMIND_NOT_VALID | MIIMIND_BUSY))
;
/* Read MII management status */
value = (u16)in_be32(&regs->miimstat);
if (value == 0xffff)
return -EINVAL;
return value;
};
static int
qe_uec_mdio_write(struct udevice *dev, int addr, int devad, int reg,
u16 value)
{
struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
struct ucc_mii_mng *regs = priv->base;
u32 tmp_reg;
debug("%s: regs: %p addr: %x devad: %x reg: %x val: %x\n", __func__,
regs, addr, devad, reg, value);
/* Stop the MII management read cycle */
out_be32(&regs->miimcom, 0);
/* Setting up the MII management Address Register */
tmp_reg = ((u32)addr << MIIMADD_PHY_ADDRESS_SHIFT) | reg;
out_be32(&regs->miimadd, tmp_reg);
/* Setting up the MII management Control Register with the value */
out_be32(&regs->miimcon, (u32)value);
sync();
/* Wait till MII management write is complete */
while ((in_be32(&regs->miimind)) & MIIMIND_BUSY)
;
return 0;
};
static const struct mdio_ops qe_uec_mdio_ops = {
.read = qe_uec_mdio_read,
.write = qe_uec_mdio_write,
};
static int qe_uec_mdio_probe(struct udevice *dev)
{
struct qe_uec_mdio_priv *priv = dev_get_priv(dev);
fdt_size_t base;
ofnode node;
u32 num = 0;
int ret = -ENODEV;
priv->base = (struct ucc_mii_mng *)dev_read_addr(dev);
base = (fdt_size_t)priv->base;
/*
* idea from linux:
* drivers/net/ethernet/freescale/fsl_pq_mdio.c
*
* Find the UCC node that controls the given MDIO node
*
* For some reason, the QE MDIO nodes are not children of the UCC
* devices that control them. Therefore, we need to scan all UCC
* nodes looking for the one that encompases the given MDIO node.
* We do this by comparing physical addresses. The 'start' and
* 'end' addresses of the MDIO node are passed, and the correct
* UCC node will cover the entire address range.
*/
node = ofnode_by_compatible(ofnode_null(), "ucc_geth");
while (ofnode_valid(node)) {
fdt_size_t size;
fdt_addr_t addr;
addr = ofnode_get_addr_index(node, 0);
ret = ofnode_get_addr_size_index(node, 0, &size);
if (addr == FDT_ADDR_T_NONE) {
node = ofnode_by_compatible(node, "ucc_geth");
continue;
}
/* check if priv->base in start end */
if (base > addr && base < (addr + size)) {
ret = ofnode_read_u32(node, "cell-index", &num);
if (ret)
ret = ofnode_read_u32(node, "device-id",
&num);
break;
}
node = ofnode_by_compatible(node, "ucc_geth");
}
if (ret) {
printf("%s: no cell-index nor device-id found!", __func__);
return ret;
}
/* Setup MII master clock source */
qe_set_mii_clk_src(num - 1);
return 0;
}
static const struct udevice_id qe_uec_mdio_ids[] = {
{ .compatible = "fsl,ucc-mdio" },
{ }
};
U_BOOT_DRIVER(mvmdio) = {
.name = "qe_uec_mdio",
.id = UCLASS_MDIO,
.of_match = qe_uec_mdio_ids,
.probe = qe_uec_mdio_probe,
.ops = &qe_uec_mdio_ops,
.priv_auto_alloc_size = sizeof(struct qe_uec_mdio_priv),
};

507
drivers/net/qe/uccf.c Normal file
View File

@ -0,0 +1,507 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
*/
#include <common.h>
#include <malloc.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/immap_qe.h>
#include "uccf.h"
#include <fsl_qe.h>
void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
{
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
}
u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
{
switch (ucc_num) {
case 0:
return QE_CR_SUBBLOCK_UCCFAST1;
case 1:
return QE_CR_SUBBLOCK_UCCFAST2;
case 2:
return QE_CR_SUBBLOCK_UCCFAST3;
case 3:
return QE_CR_SUBBLOCK_UCCFAST4;
case 4:
return QE_CR_SUBBLOCK_UCCFAST5;
case 5:
return QE_CR_SUBBLOCK_UCCFAST6;
case 6:
return QE_CR_SUBBLOCK_UCCFAST7;
case 7:
return QE_CR_SUBBLOCK_UCCFAST8;
default:
return QE_CR_SUBBLOCK_INVALID;
}
}
static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
u8 *reg_num, u8 *shift)
{
switch (ucc_num) {
case 0: /* UCC1 */
*p_cmxucr = &qe_immr->qmx.cmxucr1;
*reg_num = 1;
*shift = 16;
break;
case 2: /* UCC3 */
*p_cmxucr = &qe_immr->qmx.cmxucr1;
*reg_num = 1;
*shift = 0;
break;
case 4: /* UCC5 */
*p_cmxucr = &qe_immr->qmx.cmxucr2;
*reg_num = 2;
*shift = 16;
break;
case 6: /* UCC7 */
*p_cmxucr = &qe_immr->qmx.cmxucr2;
*reg_num = 2;
*shift = 0;
break;
case 1: /* UCC2 */
*p_cmxucr = &qe_immr->qmx.cmxucr3;
*reg_num = 3;
*shift = 16;
break;
case 3: /* UCC4 */
*p_cmxucr = &qe_immr->qmx.cmxucr3;
*reg_num = 3;
*shift = 0;
break;
case 5: /* UCC6 */
*p_cmxucr = &qe_immr->qmx.cmxucr4;
*reg_num = 4;
*shift = 16;
break;
case 7: /* UCC8 */
*p_cmxucr = &qe_immr->qmx.cmxucr4;
*reg_num = 4;
*shift = 0;
break;
default:
break;
}
}
static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
{
u32 *p_cmxucr = NULL;
u8 reg_num = 0;
u8 shift = 0;
u32 clk_bits;
u32 clk_mask;
int source = -1;
/* check if the UCC number is in range. */
if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
return -EINVAL;
if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
printf("%s: bad comm mode type passed\n", __func__);
return -EINVAL;
}
ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
switch (reg_num) {
case 1:
switch (clock) {
case QE_BRG1:
source = 1;
break;
case QE_BRG2:
source = 2;
break;
case QE_BRG7:
source = 3;
break;
case QE_BRG8:
source = 4;
break;
case QE_CLK9:
source = 5;
break;
case QE_CLK10:
source = 6;
break;
case QE_CLK11:
source = 7;
break;
case QE_CLK12:
source = 8;
break;
case QE_CLK15:
source = 9;
break;
case QE_CLK16:
source = 10;
break;
default:
source = -1;
break;
}
break;
case 2:
switch (clock) {
case QE_BRG5:
source = 1;
break;
case QE_BRG6:
source = 2;
break;
case QE_BRG7:
source = 3;
break;
case QE_BRG8:
source = 4;
break;
case QE_CLK13:
source = 5;
break;
case QE_CLK14:
source = 6;
break;
case QE_CLK19:
source = 7;
break;
case QE_CLK20:
source = 8;
break;
case QE_CLK15:
source = 9;
break;
case QE_CLK16:
source = 10;
break;
default:
source = -1;
break;
}
break;
case 3:
switch (clock) {
case QE_BRG9:
source = 1;
break;
case QE_BRG10:
source = 2;
break;
case QE_BRG15:
source = 3;
break;
case QE_BRG16:
source = 4;
break;
case QE_CLK3:
source = 5;
break;
case QE_CLK4:
source = 6;
break;
case QE_CLK17:
source = 7;
break;
case QE_CLK18:
source = 8;
break;
case QE_CLK7:
source = 9;
break;
case QE_CLK8:
source = 10;
break;
case QE_CLK16:
source = 11;
break;
default:
source = -1;
break;
}
break;
case 4:
switch (clock) {
case QE_BRG13:
source = 1;
break;
case QE_BRG14:
source = 2;
break;
case QE_BRG15:
source = 3;
break;
case QE_BRG16:
source = 4;
break;
case QE_CLK5:
source = 5;
break;
case QE_CLK6:
source = 6;
break;
case QE_CLK21:
source = 7;
break;
case QE_CLK22:
source = 8;
break;
case QE_CLK7:
source = 9;
break;
case QE_CLK8:
source = 10;
break;
case QE_CLK16:
source = 11;
break;
default:
source = -1;
break;
}
break;
default:
source = -1;
break;
}
if (source == -1) {
printf("%s: Bad combination of clock and UCC\n", __func__);
return -ENOENT;
}
clk_bits = (u32)source;
clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
if (mode == COMM_DIR_RX) {
clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
}
clk_bits <<= shift;
clk_mask <<= shift;
out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
return 0;
}
static uint ucc_get_reg_baseaddr(int ucc_num)
{
uint base = 0;
/* check if the UCC number is in range */
if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
printf("%s: the UCC num not in ranges\n", __func__);
return 0;
}
switch (ucc_num) {
case 0:
base = 0x00002000;
break;
case 1:
base = 0x00003000;
break;
case 2:
base = 0x00002200;
break;
case 3:
base = 0x00003200;
break;
case 4:
base = 0x00002400;
break;
case 5:
base = 0x00003400;
break;
case 6:
base = 0x00002600;
break;
case 7:
base = 0x00003600;
break;
default:
break;
}
base = (uint)qe_immr + base;
return base;
}
void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
{
ucc_fast_t *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
/* Enable reception and/or transmission on this UCC. */
gumr = in_be32(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr |= UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 1;
}
if (mode & COMM_DIR_RX) {
gumr |= UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 1;
}
out_be32(&uf_regs->gumr, gumr);
}
void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
{
ucc_fast_t *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
/* Disable reception and/or transmission on this UCC. */
gumr = in_be32(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr &= ~UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 0;
}
if (mode & COMM_DIR_RX) {
gumr &= ~UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 0;
}
out_be32(&uf_regs->gumr, gumr);
}
int ucc_fast_init(struct ucc_fast_inf *uf_info,
struct ucc_fast_priv **uccf_ret)
{
struct ucc_fast_priv *uccf;
ucc_fast_t *uf_regs;
if (!uf_info)
return -EINVAL;
if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
printf("%s: Illagal UCC number!\n", __func__);
return -EINVAL;
}
uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
if (!uccf) {
printf("%s: No memory for UCC fast data structure!\n",
__func__);
return -ENOMEM;
}
memset(uccf, 0, sizeof(struct ucc_fast_priv));
/* Save fast UCC structure */
uccf->uf_info = uf_info;
uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
if (!uccf->uf_regs) {
printf("%s: No memory map for UCC fast controller!\n",
__func__);
return -ENOMEM;
}
uccf->enabled_tx = 0;
uccf->enabled_rx = 0;
uf_regs = uccf->uf_regs;
uccf->p_ucce = (u32 *)&uf_regs->ucce;
uccf->p_uccm = (u32 *)&uf_regs->uccm;
/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
| UCC_GUEMR_MODE_FAST_TX);
/* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
/* Set the Giga ethernet VFIFO stuff */
if (uf_info->eth_type == GIGA_ETH) {
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* Allocate memory for Rx Virtual Fifo */
uccf->ucc_fast_rx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* utfb, urfb are offsets from MURAM base */
out_be32(&uf_regs->utfb,
uccf->ucc_fast_tx_virtual_fifo_base_offset);
out_be32(&uf_regs->urfb,
uccf->ucc_fast_rx_virtual_fifo_base_offset);
/* Set Virtual Fifo registers */
out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
}
/* Set the Fast ethernet VFIFO stuff */
if (uf_info->eth_type == FAST_ETH) {
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_UTFS_INIT,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* Allocate memory for Rx Virtual Fifo */
uccf->ucc_fast_rx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_URFS_INIT +
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* utfb, urfb are offsets from MURAM base */
out_be32(&uf_regs->utfb,
uccf->ucc_fast_tx_virtual_fifo_base_offset);
out_be32(&uf_regs->urfb,
uccf->ucc_fast_rx_virtual_fifo_base_offset);
/* Set Virtual Fifo registers */
out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
}
/* Rx clock routing */
if (uf_info->rx_clock != QE_CLK_NONE) {
if (ucc_set_clk_src(uf_info->ucc_num,
uf_info->rx_clock, COMM_DIR_RX)) {
printf("%s: Illegal value for parameter 'RxClock'.\n",
__func__);
return -EINVAL;
}
}
/* Tx clock routing */
if (uf_info->tx_clock != QE_CLK_NONE) {
if (ucc_set_clk_src(uf_info->ucc_num,
uf_info->tx_clock, COMM_DIR_TX)) {
printf("%s: Illegal value for parameter 'TxClock'.\n",
__func__);
return -EINVAL;
}
}
/* Clear interrupt mask register to disable all of interrupts */
out_be32(&uf_regs->uccm, 0x0);
/* Writing '1' to clear all of envents */
out_be32(&uf_regs->ucce, 0xffffffff);
*uccf_ret = uccf;
return 0;
}

119
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
*/
#ifndef __UCCF_H__
#define __UCCF_H__
#include "common.h"
#include "linux/immap_qe.h"
#include <fsl_qe.h>
/* Fast or Giga ethernet */
enum enet_type {
FAST_ETH,
GIGA_ETH,
};
/* General UCC Extended Mode Register */
#define UCC_GUEMR_MODE_MASK_RX 0x02
#define UCC_GUEMR_MODE_MASK_TX 0x01
#define UCC_GUEMR_MODE_FAST_RX 0x02
#define UCC_GUEMR_MODE_FAST_TX 0x01
#define UCC_GUEMR_MODE_SLOW_RX 0x00
#define UCC_GUEMR_MODE_SLOW_TX 0x00
/* Bit 3 must be set 1 */
#define UCC_GUEMR_SET_RESERVED3 0x10
/* General UCC FAST Mode Register */
#define UCC_FAST_GUMR_TCI 0x20000000
#define UCC_FAST_GUMR_TRX 0x10000000
#define UCC_FAST_GUMR_TTX 0x08000000
#define UCC_FAST_GUMR_CDP 0x04000000
#define UCC_FAST_GUMR_CTSP 0x02000000
#define UCC_FAST_GUMR_CDS 0x01000000
#define UCC_FAST_GUMR_CTSS 0x00800000
#define UCC_FAST_GUMR_TXSY 0x00020000
#define UCC_FAST_GUMR_RSYN 0x00010000
#define UCC_FAST_GUMR_RTSM 0x00002000
#define UCC_FAST_GUMR_REVD 0x00000400
#define UCC_FAST_GUMR_ENR 0x00000020
#define UCC_FAST_GUMR_ENT 0x00000010
/* GUMR [MODE] bit maps */
#define UCC_FAST_GUMR_HDLC 0x00000000
#define UCC_FAST_GUMR_QMC 0x00000002
#define UCC_FAST_GUMR_UART 0x00000004
#define UCC_FAST_GUMR_BISYNC 0x00000008
#define UCC_FAST_GUMR_ATM 0x0000000a
#define UCC_FAST_GUMR_ETH 0x0000000c
/* Transmit On Demand (UTORD) */
#define UCC_SLOW_TOD 0x8000
#define UCC_FAST_TOD 0x8000
/* Fast Ethernet (10/100 Mbps) */
/* Rx virtual FIFO size */
#define UCC_GETH_URFS_INIT 512
/* 1/2 urfs */
#define UCC_GETH_URFET_INIT 256
/* 3/4 urfs */
#define UCC_GETH_URFSET_INIT 384
/* Tx virtual FIFO size */
#define UCC_GETH_UTFS_INIT 512
/* 1/2 utfs */
#define UCC_GETH_UTFET_INIT 256
#define UCC_GETH_UTFTT_INIT 128
/* Gigabit Ethernet (1000 Mbps) */
/* Rx virtual FIFO size */
#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/
/* 1/2 urfs */
#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/
/* 3/4 urfs */
#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/
/* Tx virtual FIFO size */
#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/
/* 1/2 utfs */
#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/
#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/
/* UCC fast alignment */
#define UCC_FAST_RX_ALIGN 4
#define UCC_FAST_MRBLR_ALIGNMENT 4
#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
/* Sizes */
#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8
/* UCC fast structure. */
struct ucc_fast_inf {
int ucc_num;
qe_clock_e rx_clock;
qe_clock_e tx_clock;
enum enet_type eth_type;
};
struct ucc_fast_priv {
struct ucc_fast_inf *uf_info;
ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */
u32 *p_ucce; /* a pointer to the event register */
u32 *p_uccm; /* a pointer to the mask register */
int enabled_tx; /* whether UCC is enabled for Tx (ENT) */
int enabled_rx; /* whether UCC is enabled for Rx (ENR) */
u32 ucc_fast_tx_virtual_fifo_base_offset;
u32 ucc_fast_rx_virtual_fifo_base_offset;
};
void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
int ucc_fast_init(struct ucc_fast_inf *uf_info,
struct ucc_fast_priv **uccf_ret);
#endif /* __UCCF_H__ */

693
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
*/
#ifndef __UEC_H__
#define __UEC_H__
#include "uccf.h"
#include <fsl_qe.h>
#include <phy.h>
#define MAX_TX_THREADS 8
#define MAX_RX_THREADS 8
#define MAX_TX_QUEUES 8
#define MAX_RX_QUEUES 8
#define MAX_PREFETCHED_BDS 4
#define MAX_IPH_OFFSET_ENTRY 8
#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
/* UEC UPSMR (Protocol Specific Mode Register)
*/
#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
#define UPSMR_PRO 0x00400000 /* Promiscuous */
#define UPSMR_CAP 0x00200000 /* CAM polarity */
#define UPSMR_RSH 0x00100000 /* Receive Short Frames */
#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
#define UPSMR_BRO 0x00000200 /* Broadcast Address */
#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
#define UPSMR_SGMM 0x00000020 /* SGMII mode */
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
/* UEC MACCFG1 (MAC Configuration 1 Register)
*/
#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
#define MACCFG1_INIT_VALUE (0)
/* UEC MACCFG2 (MAC Configuration 2 Register)
*/
#define MACCFG2_PREL 0x00007000
#define MACCFG2_PREL_SHIFT (31 - 19)
#define MACCFG2_PREL_MASK 0x0000f000
#define MACCFG2_SRP 0x00000080
#define MACCFG2_STP 0x00000040
#define MACCFG2_RESERVED_1 0x00000020 /* must be set */
#define MACCFG2_LC 0x00000010 /* Length Check */
#define MACCFG2_MPE 0x00000008
#define MACCFG2_FDX 0x00000001 /* Full Duplex */
#define MACCFG2_FDX_MASK 0x00000001
#define MACCFG2_PAD_CRC 0x00000004
#define MACCFG2_CRC_EN 0x00000002
#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
#define MACCFG2_INTERFACE_MODE_MASK 0x00000300
#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
/* UEC Event Register */
#define UCCE_MPD 0x80000000
#define UCCE_SCAR 0x40000000
#define UCCE_GRA 0x20000000
#define UCCE_CBPR 0x10000000
#define UCCE_BSY 0x08000000
#define UCCE_RXC 0x04000000
#define UCCE_TXC 0x02000000
#define UCCE_TXE 0x01000000
#define UCCE_TXB7 0x00800000
#define UCCE_TXB6 0x00400000
#define UCCE_TXB5 0x00200000
#define UCCE_TXB4 0x00100000
#define UCCE_TXB3 0x00080000
#define UCCE_TXB2 0x00040000
#define UCCE_TXB1 0x00020000
#define UCCE_TXB0 0x00010000
#define UCCE_RXB7 0x00008000
#define UCCE_RXB6 0x00004000
#define UCCE_RXB5 0x00002000
#define UCCE_RXB4 0x00001000
#define UCCE_RXB3 0x00000800
#define UCCE_RXB2 0x00000400
#define UCCE_RXB1 0x00000200
#define UCCE_RXB0 0x00000100
#define UCCE_RXF7 0x00000080
#define UCCE_RXF6 0x00000040
#define UCCE_RXF5 0x00000020
#define UCCE_RXF4 0x00000010
#define UCCE_RXF3 0x00000008
#define UCCE_RXF2 0x00000004
#define UCCE_RXF1 0x00000002
#define UCCE_RXF0 0x00000001
#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
UCCE_RXC | UCCE_TXC | UCCE_TXE)
/* UEC TEMODR Register */
#define TEMODER_SCHEDULER_ENABLE 0x2000
#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
#define TEMODER_RMON_STATISTICS 0x0100
#define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15)
#define TEMODER_INIT_VALUE 0xc000
/* UEC REMODR Register */
#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
#define REMODER_RX_EXTENDED_FEATURES 0x80000000
#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9)
#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10)
#define REMODER_RX_QOS_MODE_SHIFT (31 - 15)
#define REMODER_RMON_STATISTICS 0x00001000
#define REMODER_RX_EXTENDED_FILTERING 0x00000800
#define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23)
#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
#define REMODER_IP_CHECKSUM_CHECK 0x00000002
#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
#define REMODER_INIT_VALUE 0
/* BMRx - Bus Mode Register */
#define BMR_GLB 0x20
#define BMR_BO_BE 0x10
#define BMR_DTB_SECONDARY_BUS 0x02
#define BMR_BDB_SECONDARY_BUS 0x01
#define BMR_SHIFT 24
#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
/* UEC UCCS (Ethernet Status Register)
*/
#define UCCS_BPR 0x02
#define UCCS_PAU 0x02
#define UCCS_MPD 0x01
/* UEC MIIMCFG (MII Management Configuration Register)
*/
#define MIIMCFG_RESET_MANAGEMENT 0x80000000
#define MIIMCFG_NO_PREAMBLE 0x00000010
#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
/* UEC MIIMCOM (MII Management Command Register)
*/
#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
/* UEC MIIMADD (MII Management Address Register)
*/
#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
/* UEC MIIMCON (MII Management Control Register)
*/
#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
#define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
/* UEC MIIMIND (MII Management Indicator Register)
*/
#define MIIMIND_NOT_VALID 0x00000004
#define MIIMIND_SCAN 0x00000002
#define MIIMIND_BUSY 0x00000001
/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
*/
#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
/* UEC UESCR (Ethernet Statistics Control Register)
*/
#define UESCR_AUTOZ 0x8000
#define UESCR_CLRCNT 0x4000
#define UESCR_MAXCOV_SHIFT (15 - 7)
#define UESCR_SCOV_SHIFT (15 - 15)
/****** Tx data struct collection ******/
/* Tx thread data, each Tx thread has one this struct. */
struct uec_thread_data_tx {
u8 res0[136];
} __packed;
/* Tx thread parameter, each Tx thread has one this struct. */
struct uec_thread_tx_pram {
u8 res0[64];
} __packed;
/* Send queue queue-descriptor, each Tx queue has one this QD */
struct uec_send_queue_qd {
u32 bd_ring_base; /* pointer to BD ring base address */
u8 res0[0x8];
u32 last_bd_completed_address; /* last entry in BD ring */
u8 res1[0x30];
} __packed;
/* Send queue memory region */
struct uec_send_queue_mem_region {
struct uec_send_queue_qd sqqd[MAX_TX_QUEUES];
} __packed;
/* Scheduler struct */
struct uec_scheduler {
u16 cpucount0; /* CPU packet counter */
u16 cpucount1; /* CPU packet counter */
u16 cecount0; /* QE packet counter */
u16 cecount1; /* QE packet counter */
u16 cpucount2; /* CPU packet counter */
u16 cpucount3; /* CPU packet counter */
u16 cecount2; /* QE packet counter */
u16 cecount3; /* QE packet counter */
u16 cpucount4; /* CPU packet counter */
u16 cpucount5; /* CPU packet counter */
u16 cecount4; /* QE packet counter */
u16 cecount5; /* QE packet counter */
u16 cpucount6; /* CPU packet counter */
u16 cpucount7; /* CPU packet counter */
u16 cecount6; /* QE packet counter */
u16 cecount7; /* QE packet counter */
u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
u32 rtsrshadow; /* temporary variable handled by QE */
u32 time; /* temporary variable handled by QE */
u32 ttl; /* temporary variable handled by QE */
u32 mblinterval; /* max burst length interval */
u16 nortsrbytetime; /* normalized value of byte time in tsr units */
u8 fracsiz;
u8 res0[1];
u8 strictpriorityq; /* Strict Priority Mask register */
u8 txasap; /* Transmit ASAP register */
u8 extrabw; /* Extra BandWidth register */
u8 oldwfqmask; /* temporary variable handled by QE */
u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
u32 minw; /* temporary variable handled by QE */
u8 res1[0x70 - 0x64];
} __packed;
/* Tx firmware counters */
struct uec_tx_firmware_statistics_pram {
u32 sicoltx; /* single collision */
u32 mulcoltx; /* multiple collision */
u32 latecoltxfr; /* late collision */
u32 frabortduecol; /* frames aborted due to tx collision */
u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
u32 carriersenseertx; /* carrier sense error */
u32 frtxok; /* frames transmitted OK */
u32 txfrexcessivedefer;
u32 txpkts256; /* total packets(including bad) 256~511 B */
u32 txpkts512; /* total packets(including bad) 512~1023B */
u32 txpkts1024; /* total packets(including bad) 1024~1518B */
u32 txpktsjumbo; /* total packets(including bad) >1024 */
} __packed;
/* Tx global parameter table */
struct uec_tx_global_pram {
u16 temoder;
u8 res0[0x38 - 0x02];
u32 sqptr;
u32 schedulerbasepointer;
u32 txrmonbaseptr;
u32 tstate;
u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
u32 vtagtable[0x8];
u32 tqptr;
u8 res2[0x80 - 0x74];
} __packed;
/****** Rx data struct collection ******/
/* Rx thread data, each Rx thread has one this struct. */
struct uec_thread_data_rx {
u8 res0[40];
} __packed;
/* Rx thread parameter, each Rx thread has one this struct. */
struct uec_thread_rx_pram {
u8 res0[128];
} __packed;
/* Rx firmware counters */
struct uec_rx_firmware_statistics_pram {
u32 frrxfcser; /* frames with crc error */
u32 fraligner; /* frames with alignment error */
u32 inrangelenrxer; /* in range length error */
u32 outrangelenrxer; /* out of range length error */
u32 frtoolong; /* frame too long */
u32 runt; /* runt */
u32 verylongevent; /* very long event */
u32 symbolerror; /* symbol error */
u32 dropbsy; /* drop because of BD not ready */
u8 res0[0x8];
u32 mismatchdrop; /* drop because of MAC filtering */
u32 underpkts; /* total frames less than 64 octets */
u32 pkts256; /* total frames(including bad)256~511 B */
u32 pkts512; /* total frames(including bad)512~1023 B */
u32 pkts1024; /* total frames(including bad)1024~1518 B */
u32 pktsjumbo; /* total frames(including bad) >1024 B */
u32 frlossinmacer;
u32 pausefr; /* pause frames */
u8 res1[0x4];
u32 removevlan;
u32 replacevlan;
u32 insertvlan;
} __packed;
/* Rx interrupt coalescing entry, each Rx queue has one this entry. */
struct uec_rx_interrupt_coalescing_entry {
u32 maxvalue;
u32 counter;
} __packed;
struct uec_rx_interrupt_coalescing_table {
struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES];
} __packed;
/* RxBD queue entry, each Rx queue has one this entry. */
struct uec_rx_bd_queues_entry {
u32 bdbaseptr; /* BD base pointer */
u32 bdptr; /* BD pointer */
u32 externalbdbaseptr; /* external BD base pointer */
u32 externalbdptr; /* external BD pointer */
} __packed;
/* Rx global parameter table */
struct uec_rx_global_pram {
u32 remoder; /* ethernet mode reg. */
u32 rqptr; /* base pointer to the Rx Queues */
u32 res0[0x1];
u8 res1[0x20 - 0xc];
u16 typeorlen;
u8 res2[0x1];
u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
u32 rxrmonbaseptr; /* Rx RMON statistics base */
u8 res3[0x30 - 0x28];
u32 intcoalescingptr; /* Interrupt coalescing table pointer */
u8 res4[0x36 - 0x34];
u8 rstate;
u8 res5[0x46 - 0x37];
u16 mrblr; /* max receive buffer length reg. */
u32 rbdqptr; /* RxBD parameter table description */
u16 mflr; /* max frame length reg. */
u16 minflr; /* min frame length reg. */
u16 maxd1; /* max dma1 length reg. */
u16 maxd2; /* max dma2 length reg. */
u32 ecamptr; /* external CAM address */
u32 l2qt; /* VLAN priority mapping table. */
u32 l3qt[0x8]; /* IP priority mapping table. */
u16 vlantype; /* vlan type */
u16 vlantci; /* default vlan tci */
u8 addressfiltering[64];/* address filtering data structure */
u32 exf_global_param; /* extended filtering global parameters */
u8 res6[0x100 - 0xc4]; /* Initialize to zero */
} __packed;
#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
/****** UEC common ******/
/* UCC statistics - hardware counters */
struct uec_hardware_statistics {
u32 tx64;
u32 tx127;
u32 tx255;
u32 rx64;
u32 rx127;
u32 rx255;
u32 txok;
u16 txcf;
u32 tmca;
u32 tbca;
u32 rxfok;
u32 rxbok;
u32 rbyt;
u32 rmca;
u32 rbca;
} __packed;
/* InitEnet command parameter */
struct uec_init_cmd_pram {
u8 resinit0;
u8 resinit1;
u8 resinit2;
u8 resinit3;
u16 resinit4;
u8 res1[0x1];
u8 largestexternallookupkeysize;
u32 rgftgfrxglobal;
u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
u8 res2[0x38 - 0x30];
u32 txglobal; /* tx global */
u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
u8 res3[0x1];
} __packed;
#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
#define ENET_INIT_PARAM_SNUM_SHIFT 24
#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
/* structure representing 82xx Address Filtering Enet Address in PRAM */
struct uec_82xx_enet_addr {
u8 res1[0x2];
u16 h; /* address (MSB) */
u16 m; /* address */
u16 l; /* address (LSB) */
} __packed;
/* structure representing 82xx Address Filtering PRAM */
struct uec_82xx_add_filtering_pram {
u32 iaddr_h; /* individual address filter, high */
u32 iaddr_l; /* individual address filter, low */
u32 gaddr_h; /* group address filter, high */
u32 gaddr_l; /* group address filter, low */
struct uec_82xx_enet_addr taddr;
struct uec_82xx_enet_addr paddr[4];
u8 res0[0x40 - 0x38];
} __packed;
/* Buffer Descriptor */
struct buffer_descriptor {
u16 status;
u16 len;
u32 data;
} __packed;
#define SIZEOFBD sizeof(struct buffer_descriptor)
/* Common BD flags */
#define BD_WRAP 0x2000
#define BD_INT 0x1000
#define BD_LAST 0x0800
#define BD_CLEAN 0x3000
/* TxBD status flags */
#define TX_BD_READY 0x8000
#define TX_BD_PADCRC 0x4000
#define TX_BD_WRAP BD_WRAP
#define TX_BD_INT BD_INT
#define TX_BD_LAST BD_LAST
#define TX_BD_TXCRC 0x0400
#define TX_BD_DEF 0x0200
#define TX_BD_PP 0x0100
#define TX_BD_LC 0x0080
#define TX_BD_RL 0x0040
#define TX_BD_RC 0x003C
#define TX_BD_UNDERRUN 0x0002
#define TX_BD_TRUNC 0x0001
#define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC)
/* RxBD status flags */
#define RX_BD_EMPTY 0x8000
#define RX_BD_OWNER 0x4000
#define RX_BD_WRAP BD_WRAP
#define RX_BD_INT BD_INT
#define RX_BD_LAST BD_LAST
#define RX_BD_FIRST 0x0400
#define RX_BD_CMR 0x0200
#define RX_BD_MISS 0x0100
#define RX_BD_BCAST 0x0080
#define RX_BD_MCAST 0x0040
#define RX_BD_LG 0x0020
#define RX_BD_NO 0x0010
#define RX_BD_SHORT 0x0008
#define RX_BD_CRCERR 0x0004
#define RX_BD_OVERRUN 0x0002
#define RX_BD_IPCH 0x0001
#define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
RX_BD_CRCERR | RX_BD_OVERRUN)
/* BD access macros */
#define BD_STATUS(_bd) (in_be16(&((_bd)->status)))
#define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v))
#define BD_LENGTH(_bd) (in_be16(&((_bd)->len)))
#define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v))
#define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0))
#define BD_DATA(_bd) ((u8 *)(((_bd)->data)))
#define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data))
#define BD_ADVANCE(_bd, _status, _base) \
(((_status) & BD_WRAP) ? (_bd) = \
((struct buffer_descriptor *)(_base)) : ++(_bd))
/* Rx Prefetched BDs */
struct uec_rx_pref_bds {
struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
} __packed;
/* Alignments */
#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
#define UEC_THREAD_RX_PRAM_ALIGNMENT 128
#define UEC_THREAD_TX_PRAM_ALIGNMENT 64
#define UEC_THREAD_DATA_ALIGNMENT 256
#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
#define UEC_SCHEDULER_ALIGNMENT 4
#define UEC_TX_STATISTICS_ALIGNMENT 4
#define UEC_RX_STATISTICS_ALIGNMENT 4
#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
#define UEC_RX_BD_QUEUES_ALIGNMENT 8
#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
#define UEC_RX_BD_RING_ALIGNMENT 32
#define UEC_TX_BD_RING_ALIGNMENT 32
#define UEC_MRBLR_ALIGNMENT 128
#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
#define UEC_RX_DATA_BUF_ALIGNMENT 64
#define UEC_VLAN_PRIORITY_MAX 8
#define UEC_IP_PRIORITY_MAX 64
#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
#define UEC_RX_BD_RING_SIZE_MIN 8
#define UEC_TX_BD_RING_SIZE_MIN 2
/* TBI / MII Set Register */
enum enet_tbi_mii_reg {
ENET_TBI_MII_CR = 0x00,
ENET_TBI_MII_SR = 0x01,
ENET_TBI_MII_ANA = 0x04,
ENET_TBI_MII_ANLPBPA = 0x05,
ENET_TBI_MII_ANEX = 0x06,
ENET_TBI_MII_ANNPT = 0x07,
ENET_TBI_MII_ANLPANP = 0x08,
ENET_TBI_MII_EXST = 0x0F,
ENET_TBI_MII_JD = 0x10,
ENET_TBI_MII_TBICON = 0x11
};
/* TBI MDIO register bit fields*/
#define TBICON_CLK_SELECT 0x0020
#define TBIANA_ASYMMETRIC_PAUSE 0x0100
#define TBIANA_SYMMETRIC_PAUSE 0x0080
#define TBIANA_HALF_DUPLEX 0x0040
#define TBIANA_FULL_DUPLEX 0x0020
#define TBICR_PHY_RESET 0x8000
#define TBICR_ANEG_ENABLE 0x1000
#define TBICR_RESTART_ANEG 0x0200
#define TBICR_FULL_DUPLEX 0x0100
#define TBICR_SPEED1_SET 0x0040
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
| TBIANA_SYMMETRIC_PAUSE \
| TBIANA_FULL_DUPLEX \
)
#define TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
/* UEC number of threads */
enum uec_num_of_threads {
UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
};
/* UEC initialization info struct */
#define STD_UEC_INFO(num) \
{ \
.uf_info = { \
.ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
.rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
.tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
.eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
}, \
.num_threads_tx = UEC_NUM_OF_THREADS_1, \
.num_threads_rx = UEC_NUM_OF_THREADS_1, \
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.tx_bd_ring_len = 16, \
.rx_bd_ring_len = 16, \
.phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
.enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \
.speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
}
struct uec_inf {
struct ucc_fast_inf uf_info;
enum uec_num_of_threads num_threads_tx;
enum uec_num_of_threads num_threads_rx;
unsigned int risc_tx;
unsigned int risc_rx;
u16 rx_bd_ring_len;
u16 tx_bd_ring_len;
u8 phy_address;
phy_interface_t enet_interface_type;
int speed;
};
/* UEC driver initialized info */
#define MAX_RXBUF_LEN 1536
#define MAX_FRAME_LEN 1518
#define MIN_FRAME_LEN 64
#define MAX_DMA1_LEN 1520
#define MAX_DMA2_LEN 1520
/* UEC driver private struct */
struct uec_priv {
struct uec_inf *uec_info;
struct ucc_fast_priv *uccf;
struct eth_device *dev;
uec_t *uec_regs;
/* enet init command parameter */
struct uec_init_cmd_pram *p_init_enet_param;
u32 init_enet_param_offset;
/* Rx and Tx parameter */
struct uec_rx_global_pram *p_rx_glbl_pram;
u32 rx_glbl_pram_offset;
struct uec_tx_global_pram *p_tx_glbl_pram;
u32 tx_glbl_pram_offset;
struct uec_send_queue_mem_region *p_send_q_mem_reg;
u32 send_q_mem_reg_offset;
struct uec_thread_data_tx *p_thread_data_tx;
u32 thread_dat_tx_offset;
struct uec_thread_data_rx *p_thread_data_rx;
u32 thread_dat_rx_offset;
struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl;
u32 rx_bd_qs_tbl_offset;
/* BDs specific */
u8 *p_tx_bd_ring;
u32 tx_bd_ring_offset;
u8 *p_rx_bd_ring;
u32 rx_bd_ring_offset;
u8 *p_rx_buf;
u32 rx_buf_offset;
struct buffer_descriptor *tx_bd;
struct buffer_descriptor *rx_bd;
/* Status */
int mac_tx_enabled;
int mac_rx_enabled;
int grace_stopped_tx;
int grace_stopped_rx;
int the_first_run;
#if !defined(COFIG_DM)
/* PHY specific */
struct uec_mii_info *mii_info;
int oldspeed;
int oldduplex;
int oldlink;
#endif
};
int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
int uec_standard_init(struct bd_info *bis);
#endif /* __UEC_H__ */

7
drivers/pinctrl/Kconfig
View File

@ -205,6 +205,13 @@ config PINCTRL_QCA953X
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_QE
bool "QE based pinctrl driver, like on mpc83xx"
depends on DM
help
This option is to enable the QE pinctrl driver for QE based io
controller.
config PINCTRL_ROCKCHIP_RV1108
bool "Rockchip rv1108 pin control driver"
depends on DM

1
drivers/pinctrl/Makefile
View File

@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_MTK) += mediatek/
obj-$(CONFIG_PINCTRL_MSCC) += mscc/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_ARCH_NEXELL) += nexell/
obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o

255
drivers/pinctrl/pinctrl-qe-io.c Normal file
View File

@ -0,0 +1,255 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
*/
#include <common.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <asm/immap_83xx.h>
#if defined(CONFIG_PINCTRL)
#include <dm.h>
#include <dm/device_compat.h>
#include <dm/pinctrl.h>
#include <linux/ioport.h>
/**
* struct qe_io_platdata
*
* @base: Base register address
* @num_par_io_ports number of io ports
*/
struct qe_io_platdata {
qepio83xx_t *base;
u32 num_io_ports;
};
#endif
#define NUM_OF_PINS 32
/** qe_cfg_iopin configure one io pin setting
*
* @par_io: pointer to parallel I/O base
* @port: io pin port
* @pin: io pin number which get configured
* @dir: direction of io pin 2 bits valid
* 00 = pin disabled
* 01 = output
* 10 = input
* 11 = pin is I/O
* @open_drain: is pin open drain
* @assign: pin assignment registers select the function of the pin
*/
static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
int open_drain, int assign)
{
u32 dbit_mask;
u32 dbit_dir;
u32 dbit_asgn;
u32 bit_mask;
u32 tmp_val;
int offset;
offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
/* Calculate pin location and 2bit mask and dir */
dbit_mask = (u32)(0x3 << offset);
dbit_dir = (u32)(dir << offset);
/* Setup the direction */
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].dir2) :
in_be32(&par_io->ioport[port].dir1);
if (pin > (NUM_OF_PINS / 2) - 1) {
out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
} else {
out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
}
/* Calculate pin location for 1bit mask */
bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
/* Setup the open drain */
tmp_val = in_be32(&par_io->ioport[port].podr);
if (open_drain)
out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
else
out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
/* Setup the assignment */
tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
in_be32(&par_io->ioport[port].ppar2) :
in_be32(&par_io->ioport[port].ppar1);
dbit_asgn = (u32)(assign << offset);
/* Clear and set 2 bits mask */
if (pin > (NUM_OF_PINS / 2) - 1) {
out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
} else {
out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
}
}
#if !defined(CONFIG_PINCTRL)
/** qe_config_iopin configure one io pin setting
*
* @port: io pin port
* @pin: io pin number which get configured
* @dir: direction of io pin 2 bits valid
* 00 = pin disabled
* 01 = output
* 10 = input
* 11 = pin is I/O
* @open_drain: is pin open drain
* @assign: pin assignment registers select the function of the pin
*/
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
}
#else
static int qe_io_ofdata_to_platdata(struct udevice *dev)
{
struct qe_io_platdata *plat = dev->platdata;
fdt_addr_t addr;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->base = (qepio83xx_t *)addr;
if (dev_read_u32(dev, "num-ports", &plat->num_io_ports))
return -EINVAL;
return 0;
}
/**
* par_io_of_config_node config
* @dev: pointer to pinctrl device
* @pio: ofnode of pinconfig property
*/
static int par_io_of_config_node(struct udevice *dev, ofnode pio)
{
struct qe_io_platdata *plat = dev->platdata;
qepio83xx_t *par_io = plat->base;
const unsigned int *pio_map;
int pio_map_len;
pio_map = ofnode_get_property(pio, "pio-map", &pio_map_len);
if (!pio_map)
return -ENOENT;
pio_map_len /= sizeof(unsigned int);
if ((pio_map_len % 6) != 0) {
dev_err(dev, "%s: pio-map format wrong!\n", __func__);
return -EINVAL;
}
while (pio_map_len > 0) {
/*
* column pio_map[5] from linux (has_irq) not
* supported in u-boot yet.
*/
qe_cfg_iopin(par_io, (u8)pio_map[0], (u8)pio_map[1],
(int)pio_map[2], (int)pio_map[3],
(int)pio_map[4]);
pio_map += 6;
pio_map_len -= 6;
}
return 0;
}
int par_io_of_config(struct udevice *dev)
{
u32 phandle;
ofnode pio;
int err;
err = ofnode_read_u32(dev_ofnode(dev), "pio-handle", &phandle);
if (err) {
dev_err(dev, "%s: pio-handle not available\n", __func__);
return err;
}
pio = ofnode_get_by_phandle(phandle);
if (!ofnode_valid(pio)) {
dev_err(dev, "%s: unable to find node\n", __func__);
return -EINVAL;
}
/* To Do: find pinctrl device and pass it */
return par_io_of_config_node(NULL, pio);
}
/*
* This is not nice!
* pinsettings should work with "pinctrl-" properties.
* Unfortunately on mpc83xx powerpc linux device trees
* devices handle this with "pio-handle" properties ...
*
* Even worser, old board code inits all par_io
* pins in one step, if U-Boot uses the device
* or not. So init all par_io definitions here too
* as linux does this also.
*/
static void config_qe_ioports(struct udevice *dev)
{
ofnode ofn;
for (ofn = dev_read_first_subnode(dev); ofnode_valid(ofn);
ofn = dev_read_next_subnode(ofn)) {
/*
* ignore errors here, as may the subnode
* has no pio-handle
*/
par_io_of_config_node(dev, ofn);
}
}
static int par_io_pinctrl_probe(struct udevice *dev)
{
config_qe_ioports(dev);
return 0;
}
static int par_io_pinctrl_set_state(struct udevice *dev, struct udevice *config)
{
return 0;
}
const struct pinctrl_ops par_io_pinctrl_ops = {
.set_state = par_io_pinctrl_set_state,
};
static const struct udevice_id par_io_pinctrl_match[] = {
{ .compatible = "fsl,mpc8360-par_io"},
{ /* sentinel */ }
};
U_BOOT_DRIVER(par_io_pinctrl) = {
.name = "par-io-pinctrl",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(par_io_pinctrl_match),
.probe = par_io_pinctrl_probe,
.ofdata_to_platdata = qe_io_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct qe_io_platdata),
.ops = &par_io_pinctrl_ops,
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.flags = DM_FLAG_PRE_RELOC,
#endif
};
#endif

2
drivers/qe/Kconfig
View File

@ -3,7 +3,7 @@
#
config QE
bool "Enable support for QUICC Engine"
depends on PPC && !DM_ETH
depends on PPC
default y if ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || ARCH_P1021 \
|| ARCH_P1025
help

96
drivers/qe/qe.c
View File

@ -26,7 +26,7 @@
#define MPC85xx_DEVDISR_QE_DISABLE 0x1
qe_map_t *qe_immr = NULL;
qe_map_t *qe_immr;
#ifdef CONFIG_QE
static qe_snum_t snums[QE_NUM_OF_SNUM];
#endif
@ -38,18 +38,16 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
u32 cecr;
if (cmd == QE_RESET) {
out_be32(&qe_immr->cp.cecr,(u32) (cmd | QE_CR_FLG));
out_be32(&qe_immr->cp.cecr, (u32)(cmd | QE_CR_FLG));
} else {
out_be32(&qe_immr->cp.cecdr, cmd_data);
out_be32(&qe_immr->cp.cecr, (sbc | QE_CR_FLG |
((u32) mcn<<QE_CR_PROTOCOL_SHIFT) | cmd));
((u32)mcn << QE_CR_PROTOCOL_SHIFT) | cmd));
}
/* Wait for the QE_CR_FLG to clear */
do {
cecr = in_be32(&qe_immr->cp.cecr);
} while (cecr & QE_CR_FLG);
return;
}
#ifdef CONFIG_QE
@ -66,12 +64,13 @@ uint qe_muram_alloc(uint size, uint align)
if (off != 0)
gd->arch.mp_alloc_base += (align - off);
if ((off = size & align_mask) != 0)
off = size & align_mask;
if (off != 0)
size += (align - off);
if ((gd->arch.mp_alloc_base + size) >= gd->arch.mp_alloc_top) {
gd->arch.mp_alloc_base = savebase;
printf("%s: ran out of ram.\n", __FUNCTION__);
printf("%s: ran out of ram.\n", __func__);
}
retloc = gd->arch.mp_alloc_base;
@ -93,10 +92,10 @@ void *qe_muram_addr(uint offset)
#ifdef CONFIG_QE
static void qe_sdma_init(void)
{
volatile sdma_t *p;
uint sdma_buffer_base;
sdma_t *p;
uint sdma_buffer_base;
p = (volatile sdma_t *)&qe_immr->sdma;
p = (sdma_t *)&qe_immr->sdma;
/* All of DMA transaction in bus 1 */
out_be32(&p->sdaqr, 0);
@ -212,7 +211,7 @@ void qe_init(uint qe_base)
qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
/* enable the microcode in IRAM */
out_be32(&qe_immr->iram.iready,QE_IRAM_READY);
out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
#endif
gd->arch.mp_alloc_base = QE_DATAONLY_BASE;
@ -235,10 +234,12 @@ void u_qe_init(void)
void *addr = (void *)CONFIG_SYS_QE_FW_ADDR;
if (src == BOOT_SOURCE_IFC_NOR)
addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_IFC_BASE);
addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
CONFIG_SYS_FSL_IFC_BASE);
if (src == BOOT_SOURCE_QSPI_NOR)
addr = (void *)(CONFIG_SYS_QE_FW_ADDR + CONFIG_SYS_FSL_QSPI_BASE);
addr = (void *)(CONFIG_SYS_QE_FW_ADDR +
CONFIG_SYS_FSL_QSPI_BASE);
if (src == BOOT_SOURCE_SD_MMC) {
int dev = CONFIG_SYS_MMC_ENV_DEV;
@ -320,7 +321,7 @@ void u_qe_resume(void)
void qe_reset(void)
{
qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
(u8) QE_CR_PROTOCOL_UNSPECIFIED, 0);
(u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
}
#ifdef CONFIG_QE
@ -329,24 +330,22 @@ void qe_assign_page(uint snum, uint para_ram_base)
u32 cecr;
out_be32(&qe_immr->cp.cecdr, para_ram_base);
out_be32(&qe_immr->cp.cecr, ((u32) snum<<QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
out_be32(&qe_immr->cp.cecr, ((u32)snum << QE_CR_ASSIGN_PAGE_SNUM_SHIFT)
| QE_CR_FLG | QE_ASSIGN_PAGE);
/* Wait for the QE_CR_FLG to clear */
do {
cecr = in_be32(&qe_immr->cp.cecr);
} while (cecr & QE_CR_FLG );
return;
} while (cecr & QE_CR_FLG);
}
#endif
/*
* brg: 0~15 as BRG1~BRG16
rate: baud rate
* rate: baud rate
* BRG input clock comes from the BRGCLK (internal clock generated from
the QE clock, it is one-half of the QE clock), If need the clock source
from CLKn pin, we have te change the function.
* the QE clock, it is one-half of the QE clock), If need the clock source
* from CLKn pin, we have te change the function.
*/
#define BRG_CLK (gd->arch.brg_clk)
@ -354,12 +353,14 @@ void qe_assign_page(uint snum, uint para_ram_base)
#ifdef CONFIG_QE
int qe_set_brg(uint brg, uint rate)
{
volatile uint *bp;
u32 divisor;
int div16 = 0;
uint *bp;
u32 divisor;
u32 val;
int div16 = 0;
if (brg >= QE_NUM_OF_BRGS)
return -EINVAL;
bp = (uint *)&qe_immr->brg.brgc1;
bp += brg;
@ -369,33 +370,37 @@ int qe_set_brg(uint brg, uint rate)
divisor /= 16;
}
*bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
__asm__ __volatile__("sync");
/* CHECK TODO */
/*
* was
* *bp = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
* __asm__ __volatile__("sync");
*/
if (div16) {
*bp |= QE_BRGC_DIV16;
__asm__ __volatile__("sync");
}
val = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE;
if (div16)
val |= QE_BRGC_DIV16;
out_be32(bp, val);
return 0;
}
#endif
/* Set ethernet MII clock master
*/
/* Set ethernet MII clock master */
int qe_set_mii_clk_src(int ucc_num)
{
u32 cmxgcr;
/* check if the UCC number is in range. */
if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
printf("%s: ucc num not in ranges\n", __FUNCTION__);
if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
printf("%s: ucc num not in ranges\n", __func__);
return -EINVAL;
}
cmxgcr = in_be32(&qe_immr->qmx.cmxgcr);
cmxgcr &= ~QE_CMXGCR_MII_ENET_MNG_MASK;
cmxgcr |= (ucc_num <<QE_CMXGCR_MII_ENET_MNG_SHIFT);
cmxgcr |= (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
out_be32(&qe_immr->qmx.cmxgcr, cmxgcr);
return 0;
@ -417,7 +422,7 @@ static int qe_firmware_uploaded;
* the actual uploading of the microcode.
*/
static void qe_upload_microcode(const void *base,
const struct qe_microcode *ucode)
const struct qe_microcode *ucode)
{
const u32 *code = base + be32_to_cpu(ucode->code_offset);
unsigned int i;
@ -494,7 +499,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
}
/* Validate some of the fields */
if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
printf("Invalid data\n");
return -EINVAL;
}
@ -522,7 +527,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
* function isn't available unless you turn on JFFS support.
*/
crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
if (crc != (crc32(-1, (const void *) firmware, calc_size) ^ -1)) {
if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
printf("Firmware CRC is invalid\n");
return -EIO;
}
@ -532,12 +537,12 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
*/
if (!firmware->split) {
out_be16(&qe_immr->cp.cercr,
in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
}
if (firmware->soc.model)
printf("Firmware '%s' for %u V%u.%u\n",
firmware->id, be16_to_cpu(firmware->soc.model),
firmware->id, be16_to_cpu(firmware->soc.model),
firmware->soc.major, firmware->soc.minor);
else
printf("Firmware '%s'\n", firmware->id);
@ -550,7 +555,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
strncpy(qe_firmware_info.id, (char *)firmware->id, 62);
qe_firmware_info.extended_modes = firmware->extended_modes;
memcpy(qe_firmware_info.vtraps, firmware->vtraps,
sizeof(firmware->vtraps));
sizeof(firmware->vtraps));
qe_firmware_uploaded = 1;
/* Loop through each microcode. */
@ -634,7 +639,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
}
/* Validate some of the fields */
if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
if (firmware->count < 1 || firmware->count > MAX_QE_RISC) {
printf("Invalid data\n");
return -EINVAL;
}
@ -803,7 +808,7 @@ static int qe_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
if (argc > 3) {
ulong length = simple_strtoul(argv[3], NULL, 16);
struct qe_firmware *firmware = (void *) addr;
struct qe_firmware *firmware = (void *)addr;
if (length != be32_to_cpu(firmware->header.length)) {
printf("Length mismatch\n");
@ -811,7 +816,7 @@ static int qe_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
}
}
return qe_upload_firmware((const struct qe_firmware *) addr);
return qe_upload_firmware((const struct qe_firmware *)addr);
}
return cmd_usage(cmdtp);
@ -820,7 +825,6 @@ static int qe_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
U_BOOT_CMD(
qe, 4, 0, qe_cmd,
"QUICC Engine commands",
"fw <addr> [<length>] - Upload firmware binary at address <addr> to "
"the QE,\n"
"fw <addr> [<length>] - Upload firmware binary at address <addr> to the QE,\n"
"\twith optional length <length> verification."
);

443
drivers/qe/uccf.c
View File

@ -14,7 +14,8 @@
#include "uccf.h"
#include <fsl_qe.h>
void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
#if !defined(CONFIG_DM_ETH)
void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
{
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
}
@ -22,170 +23,271 @@ void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf)
u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
{
switch (ucc_num) {
case 0: return QE_CR_SUBBLOCK_UCCFAST1;
case 1: return QE_CR_SUBBLOCK_UCCFAST2;
case 2: return QE_CR_SUBBLOCK_UCCFAST3;
case 3: return QE_CR_SUBBLOCK_UCCFAST4;
case 4: return QE_CR_SUBBLOCK_UCCFAST5;
case 5: return QE_CR_SUBBLOCK_UCCFAST6;
case 6: return QE_CR_SUBBLOCK_UCCFAST7;
case 7: return QE_CR_SUBBLOCK_UCCFAST8;
default: return QE_CR_SUBBLOCK_INVALID;
case 0:
return QE_CR_SUBBLOCK_UCCFAST1;
case 1:
return QE_CR_SUBBLOCK_UCCFAST2;
case 2:
return QE_CR_SUBBLOCK_UCCFAST3;
case 3:
return QE_CR_SUBBLOCK_UCCFAST4;
case 4:
return QE_CR_SUBBLOCK_UCCFAST5;
case 5:
return QE_CR_SUBBLOCK_UCCFAST6;
case 6:
return QE_CR_SUBBLOCK_UCCFAST7;
case 7:
return QE_CR_SUBBLOCK_UCCFAST8;
default:
return QE_CR_SUBBLOCK_INVALID;
}
}
static void ucc_get_cmxucr_reg(int ucc_num, volatile u32 **p_cmxucr,
u8 *reg_num, u8 *shift)
static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
u8 *reg_num, u8 *shift)
{
switch (ucc_num) {
case 0: /* UCC1 */
*p_cmxucr = &(qe_immr->qmx.cmxucr1);
*reg_num = 1;
*shift = 16;
break;
case 2: /* UCC3 */
*p_cmxucr = &(qe_immr->qmx.cmxucr1);
*reg_num = 1;
*shift = 0;
break;
case 4: /* UCC5 */
*p_cmxucr = &(qe_immr->qmx.cmxucr2);
*reg_num = 2;
*shift = 16;
break;
case 6: /* UCC7 */
*p_cmxucr = &(qe_immr->qmx.cmxucr2);
*reg_num = 2;
*shift = 0;
break;
case 1: /* UCC2 */
*p_cmxucr = &(qe_immr->qmx.cmxucr3);
*reg_num = 3;
*shift = 16;
break;
case 3: /* UCC4 */
*p_cmxucr = &(qe_immr->qmx.cmxucr3);
*reg_num = 3;
*shift = 0;
break;
case 5: /* UCC6 */
*p_cmxucr = &(qe_immr->qmx.cmxucr4);
*reg_num = 4;
*shift = 16;
break;
case 7: /* UCC8 */
*p_cmxucr = &(qe_immr->qmx.cmxucr4);
*reg_num = 4;
*shift = 0;
break;
default:
break;
case 0: /* UCC1 */
*p_cmxucr = &qe_immr->qmx.cmxucr1;
*reg_num = 1;
*shift = 16;
break;
case 2: /* UCC3 */
*p_cmxucr = &qe_immr->qmx.cmxucr1;
*reg_num = 1;
*shift = 0;
break;
case 4: /* UCC5 */
*p_cmxucr = &qe_immr->qmx.cmxucr2;
*reg_num = 2;
*shift = 16;
break;
case 6: /* UCC7 */
*p_cmxucr = &qe_immr->qmx.cmxucr2;
*reg_num = 2;
*shift = 0;
break;
case 1: /* UCC2 */
*p_cmxucr = &qe_immr->qmx.cmxucr3;
*reg_num = 3;
*shift = 16;
break;
case 3: /* UCC4 */
*p_cmxucr = &qe_immr->qmx.cmxucr3;
*reg_num = 3;
*shift = 0;
break;
case 5: /* UCC6 */
*p_cmxucr = &qe_immr->qmx.cmxucr4;
*reg_num = 4;
*shift = 16;
break;
case 7: /* UCC8 */
*p_cmxucr = &qe_immr->qmx.cmxucr4;
*reg_num = 4;
*shift = 0;
break;
default:
break;
}
}
static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
{
volatile u32 *p_cmxucr = NULL;
u8 reg_num = 0;
u8 shift = 0;
u32 clockBits;
u32 clockMask;
int source = -1;
u32 *p_cmxucr = NULL;
u8 reg_num = 0;
u8 shift = 0;
u32 clk_bits;
u32 clk_mask;
int source = -1;
/* check if the UCC number is in range. */
if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
return -EINVAL;
if (! ((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
printf("%s: bad comm mode type passed\n", __FUNCTION__);
if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
printf("%s: bad comm mode type passed\n", __func__);
return -EINVAL;
}
ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
switch (reg_num) {
case 1:
switch (clock) {
case QE_BRG1: source = 1; break;
case QE_BRG2: source = 2; break;
case QE_BRG7: source = 3; break;
case QE_BRG8: source = 4; break;
case QE_CLK9: source = 5; break;
case QE_CLK10: source = 6; break;
case QE_CLK11: source = 7; break;
case QE_CLK12: source = 8; break;
case QE_CLK15: source = 9; break;
case QE_CLK16: source = 10; break;
default: source = -1; break;
}
case 1:
switch (clock) {
case QE_BRG1:
source = 1;
break;
case 2:
switch (clock) {
case QE_BRG5: source = 1; break;
case QE_BRG6: source = 2; break;
case QE_BRG7: source = 3; break;
case QE_BRG8: source = 4; break;
case QE_CLK13: source = 5; break;
case QE_CLK14: source = 6; break;
case QE_CLK19: source = 7; break;
case QE_CLK20: source = 8; break;
case QE_CLK15: source = 9; break;
case QE_CLK16: source = 10; break;
default: source = -1; break;
}
case QE_BRG2:
source = 2;
break;
case 3:
switch (clock) {
case QE_BRG9: source = 1; break;
case QE_BRG10: source = 2; break;
case QE_BRG15: source = 3; break;
case QE_BRG16: source = 4; break;
case QE_CLK3: source = 5; break;
case QE_CLK4: source = 6; break;
case QE_CLK17: source = 7; break;
case QE_CLK18: source = 8; break;
case QE_CLK7: source = 9; break;
case QE_CLK8: source = 10; break;
case QE_CLK16: source = 11; break;
default: source = -1; break;
}
case QE_BRG7:
source = 3;
break;
case 4:
switch (clock) {
case QE_BRG13: source = 1; break;
case QE_BRG14: source = 2; break;
case QE_BRG15: source = 3; break;
case QE_BRG16: source = 4; break;
case QE_CLK5: source = 5; break;
case QE_CLK6: source = 6; break;
case QE_CLK21: source = 7; break;
case QE_CLK22: source = 8; break;
case QE_CLK7: source = 9; break;
case QE_CLK8: source = 10; break;
case QE_CLK16: source = 11; break;
default: source = -1; break;
}
case QE_BRG8:
source = 4;
break;
case QE_CLK9:
source = 5;
break;
case QE_CLK10:
source = 6;
break;
case QE_CLK11:
source = 7;
break;
case QE_CLK12:
source = 8;
break;
case QE_CLK15:
source = 9;
break;
case QE_CLK16:
source = 10;
break;
default:
source = -1;
break;
}
break;
case 2:
switch (clock) {
case QE_BRG5:
source = 1;
break;
case QE_BRG6:
source = 2;
break;
case QE_BRG7:
source = 3;
break;
case QE_BRG8:
source = 4;
break;
case QE_CLK13:
source = 5;
break;
case QE_CLK14:
source = 6;
break;
case QE_CLK19:
source = 7;
break;
case QE_CLK20:
source = 8;
break;
case QE_CLK15:
source = 9;
break;
case QE_CLK16:
source = 10;
break;
default:
source = -1;
break;
}
break;
case 3:
switch (clock) {
case QE_BRG9:
source = 1;
break;
case QE_BRG10:
source = 2;
break;
case QE_BRG15:
source = 3;
break;
case QE_BRG16:
source = 4;
break;
case QE_CLK3:
source = 5;
break;
case QE_CLK4:
source = 6;
break;
case QE_CLK17:
source = 7;
break;
case QE_CLK18:
source = 8;
break;
case QE_CLK7:
source = 9;
break;
case QE_CLK8:
source = 10;
break;
case QE_CLK16:
source = 11;
break;
default:
source = -1;
break;
}
break;
case 4:
switch (clock) {
case QE_BRG13:
source = 1;
break;
case QE_BRG14:
source = 2;
break;
case QE_BRG15:
source = 3;
break;
case QE_BRG16:
source = 4;
break;
case QE_CLK5:
source = 5;
break;
case QE_CLK6:
source = 6;
break;
case QE_CLK21:
source = 7;
break;
case QE_CLK22:
source = 8;
break;
case QE_CLK7:
source = 9;
break;
case QE_CLK8:
source = 10;
break;
case QE_CLK16:
source = 11;
break;
default:
source = -1;
break;
}
break;
default:
source = -1;
break;
}
if (source == -1) {
printf("%s: Bad combination of clock and UCC\n", __FUNCTION__);
printf("%s: Bad combination of clock and UCC\n", __func__);
return -ENOENT;
}
clockBits = (u32) source;
clockMask = QE_CMXUCR_TX_CLK_SRC_MASK;
clk_bits = (u32)source;
clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
if (mode == COMM_DIR_RX) {
clockBits <<= 4; /* Rx field is 4 bits to left of Tx field */
clockMask <<= 4; /* Rx field is 4 bits to left of Tx field */
clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
}
clockBits <<= shift;
clockMask <<= shift;
clk_bits <<= shift;
clk_mask <<= shift;
out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clockMask) | clockBits);
out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
return 0;
}
@ -195,28 +297,45 @@ static uint ucc_get_reg_baseaddr(int ucc_num)
uint base = 0;
/* check if the UCC number is in range */
if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) {
printf("%s: the UCC num not in ranges\n", __FUNCTION__);
if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
printf("%s: the UCC num not in ranges\n", __func__);
return 0;
}
switch (ucc_num) {
case 0: base = 0x00002000; break;
case 1: base = 0x00003000; break;
case 2: base = 0x00002200; break;
case 3: base = 0x00003200; break;
case 4: base = 0x00002400; break;
case 5: base = 0x00003400; break;
case 6: base = 0x00002600; break;
case 7: base = 0x00003600; break;
default: break;
case 0:
base = 0x00002000;
break;
case 1:
base = 0x00003000;
break;
case 2:
base = 0x00002200;
break;
case 3:
base = 0x00003200;
break;
case 4:
base = 0x00002400;
break;
case 5:
base = 0x00003400;
break;
case 6:
base = 0x00002600;
break;
case 7:
base = 0x00003600;
break;
default:
break;
}
base = (uint)qe_immr + base;
return base;
}
void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
{
ucc_fast_t *uf_regs;
u32 gumr;
@ -236,7 +355,7 @@ void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode)
out_be32(&uf_regs->gumr, gumr);
}
void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
{
ucc_fast_t *uf_regs;
u32 gumr;
@ -256,34 +375,35 @@ void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode)
out_be32(&uf_regs->gumr, gumr);
}
int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
int ucc_fast_init(struct ucc_fast_inf *uf_info,
struct ucc_fast_priv **uccf_ret)
{
ucc_fast_private_t *uccf;
struct ucc_fast_priv *uccf;
ucc_fast_t *uf_regs;
if (!uf_info)
return -EINVAL;
if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
printf("%s: Illagal UCC number!\n", __FUNCTION__);
if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
printf("%s: Illagal UCC number!\n", __func__);
return -EINVAL;
}
uccf = (ucc_fast_private_t *)malloc(sizeof(ucc_fast_private_t));
uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
if (!uccf) {
printf("%s: No memory for UCC fast data structure!\n",
__FUNCTION__);
__func__);
return -ENOMEM;
}
memset(uccf, 0, sizeof(ucc_fast_private_t));
memset(uccf, 0, sizeof(struct ucc_fast_priv));
/* Save fast UCC structure */
uccf->uf_info = uf_info;
uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
if (uccf->uf_regs == NULL) {
if (!uccf->uf_regs) {
printf("%s: No memory map for UCC fast controller!\n",
__FUNCTION__);
__func__);
return -ENOMEM;
}
@ -291,8 +411,8 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
uccf->enabled_rx = 0;
uf_regs = uccf->uf_regs;
uccf->p_ucce = (u32 *) &(uf_regs->ucce);
uccf->p_uccm = (u32 *) &(uf_regs->uccm);
uccf->p_ucce = (u32 *)&uf_regs->ucce;
uccf->p_uccm = (u32 *)&uf_regs->uccm;
/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
@ -306,13 +426,13 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* Allocate memory for Rx Virtual Fifo */
uccf->ucc_fast_rx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* utfb, urfb are offsets from MURAM base */
out_be32(&uf_regs->utfb,
@ -334,7 +454,7 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_UTFS_INIT,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* Allocate memory for Rx Virtual Fifo */
uccf->ucc_fast_rx_virtual_fifo_base_offset =
@ -360,9 +480,9 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
/* Rx clock routing */
if (uf_info->rx_clock != QE_CLK_NONE) {
if (ucc_set_clk_src(uf_info->ucc_num,
uf_info->rx_clock, COMM_DIR_RX)) {
uf_info->rx_clock, COMM_DIR_RX)) {
printf("%s: Illegal value for parameter 'RxClock'.\n",
__FUNCTION__);
__func__);
return -EINVAL;
}
}
@ -370,9 +490,9 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
/* Tx clock routing */
if (uf_info->tx_clock != QE_CLK_NONE) {
if (ucc_set_clk_src(uf_info->ucc_num,
uf_info->tx_clock, COMM_DIR_TX)) {
uf_info->tx_clock, COMM_DIR_TX)) {
printf("%s: Illegal value for parameter 'TxClock'.\n",
__FUNCTION__);
__func__);
return -EINVAL;
}
}
@ -386,3 +506,4 @@ int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret)
*uccf_ret = uccf;
return 0;
}
#endif

90
drivers/qe/uccf.h
View File

@ -13,25 +13,23 @@
#include "linux/immap_qe.h"
#include <fsl_qe.h>
/* Fast or Giga ethernet
*/
typedef enum enet_type {
/* Fast or Giga ethernet */
enum enet_type {
FAST_ETH,
GIGA_ETH,
} enet_type_e;
};
/* General UCC Extended Mode Register
*/
/* General UCC Extended Mode Register */
#define UCC_GUEMR_MODE_MASK_RX 0x02
#define UCC_GUEMR_MODE_MASK_TX 0x01
#define UCC_GUEMR_MODE_FAST_RX 0x02
#define UCC_GUEMR_MODE_FAST_TX 0x01
#define UCC_GUEMR_MODE_SLOW_RX 0x00
#define UCC_GUEMR_MODE_SLOW_TX 0x00
#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 must be set 1 */
/* Bit 3 must be set 1 */
#define UCC_GUEMR_SET_RESERVED3 0x10
/* General UCC FAST Mode Register
*/
/* General UCC FAST Mode Register */
#define UCC_FAST_GUMR_TCI 0x20000000
#define UCC_FAST_GUMR_TRX 0x10000000
#define UCC_FAST_GUMR_TTX 0x08000000
@ -46,8 +44,7 @@ typedef enum enet_type {
#define UCC_FAST_GUMR_ENR 0x00000020
#define UCC_FAST_GUMR_ENT 0x00000010
/* GUMR [MODE] bit maps
*/
/* GUMR [MODE] bit maps */
#define UCC_FAST_GUMR_HDLC 0x00000000
#define UCC_FAST_GUMR_QMC 0x00000002
#define UCC_FAST_GUMR_UART 0x00000004
@ -55,50 +52,54 @@ typedef enum enet_type {
#define UCC_FAST_GUMR_ATM 0x0000000a
#define UCC_FAST_GUMR_ETH 0x0000000c
/* Transmit On Demand (UTORD)
*/
/* Transmit On Demand (UTORD) */
#define UCC_SLOW_TOD 0x8000
#define UCC_FAST_TOD 0x8000
/* Fast Ethernet (10/100 Mbps)
*/
#define UCC_GETH_URFS_INIT 512 /* Rx virtual FIFO size */
#define UCC_GETH_URFET_INIT 256 /* 1/2 urfs */
#define UCC_GETH_URFSET_INIT 384 /* 3/4 urfs */
#define UCC_GETH_UTFS_INIT 512 /* Tx virtual FIFO size */
#define UCC_GETH_UTFET_INIT 256 /* 1/2 utfs */
/* Fast Ethernet (10/100 Mbps) */
/* Rx virtual FIFO size */
#define UCC_GETH_URFS_INIT 512
/* 1/2 urfs */
#define UCC_GETH_URFET_INIT 256
/* 3/4 urfs */
#define UCC_GETH_URFSET_INIT 384
/* Tx virtual FIFO size */
#define UCC_GETH_UTFS_INIT 512
/* 1/2 utfs */
#define UCC_GETH_UTFET_INIT 256
#define UCC_GETH_UTFTT_INIT 128
/* Gigabit Ethernet (1000 Mbps)
*/
#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/ /* Rx virtual FIFO size */
#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/ /* 1/2 urfs */
#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/ /* 3/4 urfs */
#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/ /* Tx virtual FIFO size */
#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/ /* 1/2 utfs */
#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/ /* */
/* Gigabit Ethernet (1000 Mbps) */
/* Rx virtual FIFO size */
#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/
/* 1/2 urfs */
#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/
/* 3/4 urfs */
#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/
/* Tx virtual FIFO size */
#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/
/* 1/2 utfs */
#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/
#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/
/* UCC fast alignment
*/
/* UCC fast alignment */
#define UCC_FAST_RX_ALIGN 4
#define UCC_FAST_MRBLR_ALIGNMENT 4
#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
/* Sizes
*/
/* Sizes */
#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8
/* UCC fast structure.
*/
typedef struct ucc_fast_info {
/* UCC fast structure. */
struct ucc_fast_inf {
int ucc_num;
qe_clock_e rx_clock;
qe_clock_e tx_clock;
enet_type_e eth_type;
} ucc_fast_info_t;
enum enet_type eth_type;
};
typedef struct ucc_fast_private {
ucc_fast_info_t *uf_info;
struct ucc_fast_priv {
struct ucc_fast_inf *uf_info;
ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */
u32 *p_ucce; /* a pointer to the event register */
u32 *p_uccm; /* a pointer to the mask register */
@ -106,12 +107,13 @@ typedef struct ucc_fast_private {
int enabled_rx; /* whether UCC is enabled for Rx (ENR) */
u32 ucc_fast_tx_virtual_fifo_base_offset;
u32 ucc_fast_rx_virtual_fifo_base_offset;
} ucc_fast_private_t;
};
void ucc_fast_transmit_on_demand(ucc_fast_private_t *uccf);
void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
void ucc_fast_enable(ucc_fast_private_t *uccf, comm_dir_e mode);
void ucc_fast_disable(ucc_fast_private_t *uccf, comm_dir_e mode);
int ucc_fast_init(ucc_fast_info_t *uf_info, ucc_fast_private_t **uccf_ret);
void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
int ucc_fast_init(struct ucc_fast_inf *uf_info,
struct ucc_fast_priv **uccf_ret);
#endif /* __UCCF_H__ */

598
drivers/qe/uec.c
View File

File diff suppressed because it is too large Load Diff

367
drivers/qe/uec.h
View File

@ -76,8 +76,7 @@
#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
/* UEC Event Register
*/
/* UEC Event Register */
#define UCCE_MPD 0x80000000
#define UCCE_SCAR 0x40000000
#define UCCE_GRA 0x20000000
@ -120,26 +119,24 @@
#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
UCCE_RXC | UCCE_TXC | UCCE_TXE)
/* UEC TEMODR Register
*/
/* UEC TEMODR Register */
#define TEMODER_SCHEDULER_ENABLE 0x2000
#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
#define TEMODER_RMON_STATISTICS 0x0100
#define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
#define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15)
#define TEMODER_INIT_VALUE 0xc000
/* UEC REMODR Register
*/
/* UEC REMODR Register */
#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
#define REMODER_RX_EXTENDED_FEATURES 0x80000000
#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
#define REMODER_RX_QOS_MODE_SHIFT (31-15)
#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9)
#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10)
#define REMODER_RX_QOS_MODE_SHIFT (31 - 15)
#define REMODER_RMON_STATISTICS 0x00001000
#define REMODER_RX_EXTENDED_FILTERING 0x00000800
#define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
#define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23)
#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
#define REMODER_IP_CHECKSUM_CHECK 0x00000002
@ -213,35 +210,31 @@
#define UESCR_SCOV_SHIFT (15 - 15)
/****** Tx data struct collection ******/
/* Tx thread data, each Tx thread has one this struct.
*/
typedef struct uec_thread_data_tx {
/* Tx thread data, each Tx thread has one this struct. */
struct uec_thread_data_tx {
u8 res0[136];
} __attribute__ ((packed)) uec_thread_data_tx_t;
} __packed;
/* Tx thread parameter, each Tx thread has one this struct.
*/
typedef struct uec_thread_tx_pram {
/* Tx thread parameter, each Tx thread has one this struct. */
struct uec_thread_tx_pram {
u8 res0[64];
} __attribute__ ((packed)) uec_thread_tx_pram_t;
} __packed;
/* Send queue queue-descriptor, each Tx queue has one this QD
*/
typedef struct uec_send_queue_qd {
/* Send queue queue-descriptor, each Tx queue has one this QD */
struct uec_send_queue_qd {
u32 bd_ring_base; /* pointer to BD ring base address */
u8 res0[0x8];
u32 last_bd_completed_address; /* last entry in BD ring */
u8 res1[0x30];
} __attribute__ ((packed)) uec_send_queue_qd_t;
} __packed;
/* Send queue memory region */
typedef struct uec_send_queue_mem_region {
uec_send_queue_qd_t sqqd[MAX_TX_QUEUES];
} __attribute__ ((packed)) uec_send_queue_mem_region_t;
struct uec_send_queue_mem_region {
struct uec_send_queue_qd sqqd[MAX_TX_QUEUES];
} __packed;
/* Scheduler struct
*/
typedef struct uec_scheduler {
/* Scheduler struct */
struct uec_scheduler {
u16 cpucount0; /* CPU packet counter */
u16 cpucount1; /* CPU packet counter */
u16 cecount0; /* QE packet counter */
@ -272,12 +265,11 @@ typedef struct uec_scheduler {
u8 oldwfqmask; /* temporary variable handled by QE */
u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
u32 minw; /* temporary variable handled by QE */
u8 res1[0x70-0x64];
} __attribute__ ((packed)) uec_scheduler_t;
u8 res1[0x70 - 0x64];
} __packed;
/* Tx firmware counters
*/
typedef struct uec_tx_firmware_statistics_pram {
/* Tx firmware counters */
struct uec_tx_firmware_statistics_pram {
u32 sicoltx; /* single collision */
u32 mulcoltx; /* multiple collision */
u32 latecoltxfr; /* late collision */
@ -290,13 +282,12 @@ typedef struct uec_tx_firmware_statistics_pram {
u32 txpkts512; /* total packets(including bad) 512~1023B */
u32 txpkts1024; /* total packets(including bad) 1024~1518B */
u32 txpktsjumbo; /* total packets(including bad) >1024 */
} __attribute__ ((packed)) uec_tx_firmware_statistics_pram_t;
} __packed;
/* Tx global parameter table
*/
typedef struct uec_tx_global_pram {
/* Tx global parameter table */
struct uec_tx_global_pram {
u16 temoder;
u8 res0[0x38-0x02];
u8 res0[0x38 - 0x02];
u32 sqptr;
u32 schedulerbasepointer;
u32 txrmonbaseptr;
@ -304,26 +295,22 @@ typedef struct uec_tx_global_pram {
u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
u32 vtagtable[0x8];
u32 tqptr;
u8 res2[0x80-0x74];
} __attribute__ ((packed)) uec_tx_global_pram_t;
u8 res2[0x80 - 0x74];
} __packed;
/****** Rx data struct collection ******/
/* Rx thread data, each Rx thread has one this struct.
*/
typedef struct uec_thread_data_rx {
/* Rx thread data, each Rx thread has one this struct. */
struct uec_thread_data_rx {
u8 res0[40];
} __attribute__ ((packed)) uec_thread_data_rx_t;
} __packed;
/* Rx thread parameter, each Rx thread has one this struct.
*/
typedef struct uec_thread_rx_pram {
/* Rx thread parameter, each Rx thread has one this struct. */
struct uec_thread_rx_pram {
u8 res0[128];
} __attribute__ ((packed)) uec_thread_rx_pram_t;
} __packed;
/* Rx firmware counters
*/
typedef struct uec_rx_firmware_statistics_pram {
/* Rx firmware counters */
struct uec_rx_firmware_statistics_pram {
u32 frrxfcser; /* frames with crc error */
u32 fraligner; /* frames with alignment error */
u32 inrangelenrxer; /* in range length error */
@ -346,44 +333,41 @@ typedef struct uec_rx_firmware_statistics_pram {
u32 removevlan;
u32 replacevlan;
u32 insertvlan;
} __attribute__ ((packed)) uec_rx_firmware_statistics_pram_t;
} __packed;
/* Rx interrupt coalescing entry, each Rx queue has one this entry.
*/
typedef struct uec_rx_interrupt_coalescing_entry {
/* Rx interrupt coalescing entry, each Rx queue has one this entry. */
struct uec_rx_interrupt_coalescing_entry {
u32 maxvalue;
u32 counter;
} __attribute__ ((packed)) uec_rx_interrupt_coalescing_entry_t;
} __packed;
typedef struct uec_rx_interrupt_coalescing_table {
uec_rx_interrupt_coalescing_entry_t entry[MAX_RX_QUEUES];
} __attribute__ ((packed)) uec_rx_interrupt_coalescing_table_t;
struct uec_rx_interrupt_coalescing_table {
struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES];
} __packed;
/* RxBD queue entry, each Rx queue has one this entry.
*/
typedef struct uec_rx_bd_queues_entry {
/* RxBD queue entry, each Rx queue has one this entry. */
struct uec_rx_bd_queues_entry {
u32 bdbaseptr; /* BD base pointer */
u32 bdptr; /* BD pointer */
u32 externalbdbaseptr; /* external BD base pointer */
u32 externalbdptr; /* external BD pointer */
} __attribute__ ((packed)) uec_rx_bd_queues_entry_t;
} __packed;
/* Rx global paramter table
*/
typedef struct uec_rx_global_pram {
/* Rx global parameter table */
struct uec_rx_global_pram {
u32 remoder; /* ethernet mode reg. */
u32 rqptr; /* base pointer to the Rx Queues */
u32 res0[0x1];
u8 res1[0x20-0xC];
u8 res1[0x20 - 0xc];
u16 typeorlen;
u8 res2[0x1];
u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
u32 rxrmonbaseptr; /* Rx RMON statistics base */
u8 res3[0x30-0x28];
u8 res3[0x30 - 0x28];
u32 intcoalescingptr; /* Interrupt coalescing table pointer */
u8 res4[0x36-0x34];
u8 res4[0x36 - 0x34];
u8 rstate;
u8 res5[0x46-0x37];
u8 res5[0x46 - 0x37];
u16 mrblr; /* max receive buffer length reg. */
u32 rbdqptr; /* RxBD parameter table description */
u16 mflr; /* max frame length reg. */
@ -396,17 +380,15 @@ typedef struct uec_rx_global_pram {
u16 vlantype; /* vlan type */
u16 vlantci; /* default vlan tci */
u8 addressfiltering[64];/* address filtering data structure */
u32 exfGlobalParam; /* extended filtering global parameters */
u8 res6[0x100-0xC4]; /* Initialize to zero */
} __attribute__ ((packed)) uec_rx_global_pram_t;
u32 exf_global_param; /* extended filtering global parameters */
u8 res6[0x100 - 0xc4]; /* Initialize to zero */
} __packed;
#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
/****** UEC common ******/
/* UCC statistics - hardware counters
*/
typedef struct uec_hardware_statistics {
/* UCC statistics - hardware counters */
struct uec_hardware_statistics {
u32 tx64;
u32 tx127;
u32 tx255;
@ -422,11 +404,10 @@ typedef struct uec_hardware_statistics {
u32 rbyt;
u32 rmca;
u32 rbca;
} __attribute__ ((packed)) uec_hardware_statistics_t;
} __packed;
/* InitEnet command parameter
*/
typedef struct uec_init_cmd_pram {
/* InitEnet command parameter */
struct uec_init_cmd_pram {
u8 resinit0;
u8 resinit1;
u8 resinit2;
@ -440,7 +421,7 @@ typedef struct uec_init_cmd_pram {
u32 txglobal; /* tx global */
u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
u8 res3[0x1];
} __attribute__ ((packed)) uec_init_cmd_pram_t;
} __packed;
#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
@ -456,105 +437,96 @@ typedef struct uec_init_cmd_pram {
#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
/* structure representing 82xx Address Filtering Enet Address in PRAM
*/
typedef struct uec_82xx_enet_address {
/* structure representing 82xx Address Filtering Enet Address in PRAM */
struct uec_82xx_enet_addr {
u8 res1[0x2];
u16 h; /* address (MSB) */
u16 m; /* address */
u16 l; /* address (LSB) */
} __attribute__ ((packed)) uec_82xx_enet_address_t;
} __packed;
/* structure representing 82xx Address Filtering PRAM
*/
typedef struct uec_82xx_address_filtering_pram {
/* structure representing 82xx Address Filtering PRAM */
struct uec_82xx_add_filtering_pram {
u32 iaddr_h; /* individual address filter, high */
u32 iaddr_l; /* individual address filter, low */
u32 gaddr_h; /* group address filter, high */
u32 gaddr_l; /* group address filter, low */
uec_82xx_enet_address_t taddr;
uec_82xx_enet_address_t paddr[4];
u8 res0[0x40-0x38];
} __attribute__ ((packed)) uec_82xx_address_filtering_pram_t;
struct uec_82xx_enet_addr taddr;
struct uec_82xx_enet_addr paddr[4];
u8 res0[0x40 - 0x38];
} __packed;
/* Buffer Descriptor
*/
typedef struct buffer_descriptor {
/* Buffer Descriptor */
struct buffer_descriptor {
u16 status;
u16 len;
u32 data;
} __attribute__ ((packed)) qe_bd_t, *p_bd_t;
} __packed;
#define SIZEOFBD sizeof(qe_bd_t)
#define SIZEOFBD sizeof(struct buffer_descriptor)
/* Common BD flags
*/
/* Common BD flags */
#define BD_WRAP 0x2000
#define BD_INT 0x1000
#define BD_LAST 0x0800
#define BD_CLEAN 0x3000
/* TxBD status flags
*/
#define TxBD_READY 0x8000
#define TxBD_PADCRC 0x4000
#define TxBD_WRAP BD_WRAP
#define TxBD_INT BD_INT
#define TxBD_LAST BD_LAST
#define TxBD_TXCRC 0x0400
#define TxBD_DEF 0x0200
#define TxBD_PP 0x0100
#define TxBD_LC 0x0080
#define TxBD_RL 0x0040
#define TxBD_RC 0x003C
#define TxBD_UNDERRUN 0x0002
#define TxBD_TRUNC 0x0001
/* TxBD status flags */
#define TX_BD_READY 0x8000
#define TX_BD_PADCRC 0x4000
#define TX_BD_WRAP BD_WRAP
#define TX_BD_INT BD_INT
#define TX_BD_LAST BD_LAST
#define TX_BD_TXCRC 0x0400
#define TX_BD_DEF 0x0200
#define TX_BD_PP 0x0100
#define TX_BD_LC 0x0080
#define TX_BD_RL 0x0040
#define TX_BD_RC 0x003C
#define TX_BD_UNDERRUN 0x0002
#define TX_BD_TRUNC 0x0001
#define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC)
#define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC)
/* RxBD status flags
*/
#define RxBD_EMPTY 0x8000
#define RxBD_OWNER 0x4000
#define RxBD_WRAP BD_WRAP
#define RxBD_INT BD_INT
#define RxBD_LAST BD_LAST
#define RxBD_FIRST 0x0400
#define RxBD_CMR 0x0200
#define RxBD_MISS 0x0100
#define RxBD_BCAST 0x0080
#define RxBD_MCAST 0x0040
#define RxBD_LG 0x0020
#define RxBD_NO 0x0010
#define RxBD_SHORT 0x0008
#define RxBD_CRCERR 0x0004
#define RxBD_OVERRUN 0x0002
#define RxBD_IPCH 0x0001
/* RxBD status flags */
#define RX_BD_EMPTY 0x8000
#define RX_BD_OWNER 0x4000
#define RX_BD_WRAP BD_WRAP
#define RX_BD_INT BD_INT
#define RX_BD_LAST BD_LAST
#define RX_BD_FIRST 0x0400
#define RX_BD_CMR 0x0200
#define RX_BD_MISS 0x0100
#define RX_BD_BCAST 0x0080
#define RX_BD_MCAST 0x0040
#define RX_BD_LG 0x0020
#define RX_BD_NO 0x0010
#define RX_BD_SHORT 0x0008
#define RX_BD_CRCERR 0x0004
#define RX_BD_OVERRUN 0x0002
#define RX_BD_IPCH 0x0001
#define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \
RxBD_CRCERR | RxBD_OVERRUN)
#define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
RX_BD_CRCERR | RX_BD_OVERRUN)
/* BD access macros
*/
#define BD_STATUS(_bd) (((p_bd_t)(_bd))->status)
#define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val)
#define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len)
#define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val)
#define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0)
#define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data)
#define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data))
#define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data))
#define BD_ADVANCE(_bd,_status,_base) \
(((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
/* BD access macros */
#define BD_STATUS(_bd) (in_be16(&((_bd)->status)))
#define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v))
#define BD_LENGTH(_bd) (in_be16(&((_bd)->len)))
#define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v))
#define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0))
#define BD_DATA(_bd) ((u8 *)(((_bd)->data)))
#define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data))
#define BD_ADVANCE(_bd, _status, _base) \
(((_status) & BD_WRAP) ? (_bd) = \
((struct buffer_descriptor *)(_base)) : ++(_bd))
/* Rx Prefetched BDs
*/
typedef struct uec_rx_prefetched_bds {
qe_bd_t bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
} __attribute__ ((packed)) uec_rx_prefetched_bds_t;
/* Rx Prefetched BDs */
struct uec_rx_pref_bds {
struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
} __packed;
/* Alignments
*/
/* Alignments */
#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
#define UEC_THREAD_RX_PRAM_ALIGNMENT 128
@ -581,25 +553,8 @@ typedef struct uec_rx_prefetched_bds {
#define UEC_RX_BD_RING_SIZE_MIN 8
#define UEC_TX_BD_RING_SIZE_MIN 2
/* Ethernet speed
*/
typedef enum enet_speed {
ENET_SPEED_10BT, /* 10 Base T */
ENET_SPEED_100BT, /* 100 Base T */
ENET_SPEED_1000BT /* 1000 Base T */
} enet_speed_e;
/* Ethernet Address Type.
*/
typedef enum enet_addr_type {
ENET_ADDR_TYPE_INDIVIDUAL,
ENET_ADDR_TYPE_GROUP,
ENET_ADDR_TYPE_BROADCAST
} enet_addr_type_e;
/* TBI / MII Set Register
*/
typedef enum enet_tbi_mii_reg {
/* TBI / MII Set Register */
enum enet_tbi_mii_reg {
ENET_TBI_MII_CR = 0x00,
ENET_TBI_MII_SR = 0x01,
ENET_TBI_MII_ANA = 0x04,
@ -610,7 +565,7 @@ typedef enum enet_tbi_mii_reg {
ENET_TBI_MII_EXST = 0x0F,
ENET_TBI_MII_JD = 0x10,
ENET_TBI_MII_TBICON = 0x11
} enet_tbi_mii_reg_e;
};
/* TBI MDIO register bit fields*/
#define TBICON_CLK_SELECT 0x0020
@ -637,18 +592,16 @@ typedef enum enet_tbi_mii_reg {
| TBICR_SPEED1_SET \
)
/* UEC number of threads
*/
typedef enum uec_num_of_threads {
/* UEC number of threads */
enum uec_num_of_threads {
UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
} uec_num_of_threads_e;
};
/* UEC initialization info struct
*/
/* UEC initialization info struct */
#define STD_UEC_INFO(num) \
{ \
.uf_info = { \
@ -668,10 +621,10 @@ typedef enum uec_num_of_threads {
.speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \
}
typedef struct uec_info {
ucc_fast_info_t uf_info;
uec_num_of_threads_e num_threads_tx;
uec_num_of_threads_e num_threads_rx;
struct uec_inf {
struct ucc_fast_inf uf_info;
enum uec_num_of_threads num_threads_tx;
enum uec_num_of_threads num_threads_rx;
unsigned int risc_tx;
unsigned int risc_rx;
u16 rx_bd_ring_len;
@ -679,39 +632,37 @@ typedef struct uec_info {
u8 phy_address;
phy_interface_t enet_interface_type;
int speed;
} uec_info_t;
};
/* UEC driver initialized info
*/
/* UEC driver initialized info */
#define MAX_RXBUF_LEN 1536
#define MAX_FRAME_LEN 1518
#define MIN_FRAME_LEN 64
#define MAX_DMA1_LEN 1520
#define MAX_DMA2_LEN 1520
/* UEC driver private struct
*/
typedef struct uec_private {
uec_info_t *uec_info;
ucc_fast_private_t *uccf;
/* UEC driver private struct */
struct uec_priv {
struct uec_inf *uec_info;
struct ucc_fast_priv *uccf;
struct eth_device *dev;
uec_t *uec_regs;
uec_mii_t *uec_mii_regs;
/* enet init command parameter */
uec_init_cmd_pram_t *p_init_enet_param;
struct uec_init_cmd_pram *p_init_enet_param;
u32 init_enet_param_offset;
/* Rx and Tx paramter */
uec_rx_global_pram_t *p_rx_glbl_pram;
/* Rx and Tx parameter */
struct uec_rx_global_pram *p_rx_glbl_pram;
u32 rx_glbl_pram_offset;
uec_tx_global_pram_t *p_tx_glbl_pram;
struct uec_tx_global_pram *p_tx_glbl_pram;
u32 tx_glbl_pram_offset;
uec_send_queue_mem_region_t *p_send_q_mem_reg;
struct uec_send_queue_mem_region *p_send_q_mem_reg;
u32 send_q_mem_reg_offset;
uec_thread_data_tx_t *p_thread_data_tx;
struct uec_thread_data_tx *p_thread_data_tx;
u32 thread_dat_tx_offset;
uec_thread_data_rx_t *p_thread_data_rx;
struct uec_thread_data_rx *p_thread_data_rx;
u32 thread_dat_rx_offset;
uec_rx_bd_queues_entry_t *p_rx_bd_qs_tbl;
struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl;
u32 rx_bd_qs_tbl_offset;
/* BDs specific */
u8 *p_tx_bd_ring;
@ -720,8 +671,8 @@ typedef struct uec_private {
u32 rx_bd_ring_offset;
u8 *p_rx_buf;
u32 rx_buf_offset;
volatile qe_bd_t *txBd;
volatile qe_bd_t *rxBd;
struct buffer_descriptor *tx_bd;
struct buffer_descriptor *rx_bd;
/* Status */
int mac_tx_enabled;
int mac_rx_enabled;
@ -733,9 +684,9 @@ typedef struct uec_private {
int oldspeed;
int oldduplex;
int oldlink;
} uec_private_t;
};
int uec_initialize(struct bd_info *bis, uec_info_t *uec_info);
int uec_eth_init(struct bd_info *bis, uec_info_t *uecs, int num);
int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
int uec_standard_init(struct bd_info *bis);
#endif /* __UEC_H__ */

330
drivers/qe/uec_phy.c
View File

@ -23,17 +23,19 @@
#include <fsl_qe.h>
#include <phy.h>
#if !defined(CONFIG_DM_ETH)
#define ugphy_printk(format, arg...) \
printf(format "\n", ## arg)
#define ugphy_dbg(format, arg...) \
ugphy_printk(format , ## arg)
ugphy_printk(format, ## arg)
#define ugphy_err(format, arg...) \
ugphy_printk(format , ## arg)
ugphy_printk(format, ## arg)
#define ugphy_info(format, arg...) \
ugphy_printk(format , ## arg)
ugphy_printk(format, ## arg)
#define ugphy_warn(format, arg...) \
ugphy_printk(format , ## arg)
ugphy_printk(format, ## arg)
#ifdef UEC_VERBOSE_DEBUG
#define ugphy_vdbg ugphy_dbg
@ -41,13 +43,13 @@
#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
#endif /* UEC_VERBOSE_DEBUG */
/*--------------------------------------------------------------------+
/*
* --------------------------------------------------------------------
* Fixed PHY (PHY-less) support for Ethernet Ports.
*
* Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
*--------------------------------------------------------------------*/
/*
*--------------------------------------------------------------------
*
* Some boards do not have a PHY for each ethernet port. These ports are known
* as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
* CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
@ -90,54 +92,58 @@ static const struct fixed_phy_port fixed_phy_port[] = {
CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
};
/*--------------------------------------------------------------------+
/*
* -------------------------------------------------------------------
* BitBang MII support for ethernet ports
*
* Based from MPC8560ADS implementation
*--------------------------------------------------------------------*/
/*
*--------------------------------------------------------------------
*
* Example board header file to define bitbang ethernet ports:
*
* #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
* #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
*/
*/
#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
#endif
#if defined(CONFIG_BITBANGMII)
static const char *bitbang_phy_port[] = {
static const char * const bitbang_phy_port[] = {
CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
};
#endif /* CONFIG_BITBANGMII */
static void config_genmii_advert (struct uec_mii_info *mii_info);
static void genmii_setup_forced (struct uec_mii_info *mii_info);
static void genmii_restart_aneg (struct uec_mii_info *mii_info);
static int gbit_config_aneg (struct uec_mii_info *mii_info);
static int genmii_config_aneg (struct uec_mii_info *mii_info);
static int genmii_update_link (struct uec_mii_info *mii_info);
static int genmii_read_status (struct uec_mii_info *mii_info);
u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
static void config_genmii_advert(struct uec_mii_info *mii_info);
static void genmii_setup_forced(struct uec_mii_info *mii_info);
static void genmii_restart_aneg(struct uec_mii_info *mii_info);
static int gbit_config_aneg(struct uec_mii_info *mii_info);
static int genmii_config_aneg(struct uec_mii_info *mii_info);
static int genmii_update_link(struct uec_mii_info *mii_info);
static int genmii_read_status(struct uec_mii_info *mii_info);
static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum,
u16 val);
/* Write value to the PHY for this device to the register at regnum, */
/* waiting until the write is done before it returns. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
/*
* Write value to the PHY for this device to the register at regnum,
* waiting until the write is done before it returns. All PHY
* configuration has to be done through the TSEC1 MIIM regs
*/
void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
int value)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
u32 tmp_reg;
#if defined(CONFIG_BITBANGMII)
u32 i = 0;
for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
if (strncmp(dev->name, bitbang_phy_port[i],
sizeof(dev->name)) == 0) {
sizeof(dev->name)) == 0) {
(void)bb_miiphy_write(NULL, mii_id, regnum, value);
return;
}
@ -148,46 +154,48 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu
/* Stop the MII management read cycle */
out_be32 (&ug_regs->miimcom, 0);
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
/* Setting up the MII Management Address Register */
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
out_be32 (&ug_regs->miimadd, tmp_reg);
/* Setting up the MII Mangement Control Register with the value */
out_be32 (&ug_regs->miimcon, (u32) value);
/* Setting up the MII Management Control Register with the value */
out_be32 (&ug_regs->miimcon, (u32)value);
sync();
/* Wait till MII management write is complete */
while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY)
;
}
/* Reads from register regnum in the PHY for device dev, */
/* returning the value. Clears miimcom first. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
/*
* Reads from register regnum in the PHY for device dev,
* returning the value. Clears miimcom first. All PHY
* configuration has to be done through the TSEC1 MIIM regs
*/
int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
u32 tmp_reg;
u16 value;
#if defined(CONFIG_BITBANGMII)
u32 i = 0;
for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
if (strncmp(dev->name, bitbang_phy_port[i],
sizeof(dev->name)) == 0) {
sizeof(dev->name)) == 0) {
(void)bb_miiphy_read(NULL, mii_id, regnum, &value);
return (value);
return value;
}
}
#endif /* CONFIG_BITBANGMII */
ug_regs = ugeth->uec_mii_regs;
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
/* Setting up the MII Management Address Register */
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
out_be32 (&ug_regs->miimadd, tmp_reg);
/* clear MII management command cycle */
@ -199,37 +207,38 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
/* Wait till MII management write is complete */
while ((in_be32 (&ug_regs->miimind)) &
(MIIMIND_NOT_VALID | MIIMIND_BUSY));
(MIIMIND_NOT_VALID | MIIMIND_BUSY))
;
/* Read MII management status */
value = (u16) in_be32 (&ug_regs->miimstat);
value = (u16)in_be32 (&ug_regs->miimstat);
if (value == 0xffff)
ugphy_vdbg
("read wrong value : mii_id %d,mii_reg %d, base %08x",
mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
mii_id, mii_reg, (u32)&ug_regs->miimcfg);
return (value);
return value;
}
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
{
if (mii_info->phyinfo->ack_interrupt)
mii_info->phyinfo->ack_interrupt (mii_info);
mii_info->phyinfo->ack_interrupt(mii_info);
}
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
u32 interrupts)
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
u32 interrupts)
{
mii_info->interrupts = interrupts;
if (mii_info->phyinfo->config_intr)
mii_info->phyinfo->config_intr (mii_info);
mii_info->phyinfo->config_intr(mii_info);
}
/* Writes MII_ADVERTISE with the appropriate values, after
* sanitizing advertise to make sure only supported features
* are advertised
*/
static void config_genmii_advert (struct uec_mii_info *mii_info)
static void config_genmii_advert(struct uec_mii_info *mii_info)
{
u32 advertise;
u16 adv;
@ -252,7 +261,7 @@ static void config_genmii_advert (struct uec_mii_info *mii_info)
uec_phy_write(mii_info, MII_ADVERTISE, adv);
}
static void genmii_setup_forced (struct uec_mii_info *mii_info)
static void genmii_setup_forced(struct uec_mii_info *mii_info)
{
u16 ctrl;
u32 features = mii_info->phyinfo->features;
@ -283,7 +292,7 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info)
| SUPPORTED_10baseT_Full))
break;
default: /* Unsupported speed! */
ugphy_err ("%s: Bad speed!", mii_info->dev->name);
ugphy_err("%s: Bad speed!", mii_info->dev->name);
break;
}
@ -291,7 +300,7 @@ static void genmii_setup_forced (struct uec_mii_info *mii_info)
}
/* Enable and Restart Autonegotiation */
static void genmii_restart_aneg (struct uec_mii_info *mii_info)
static void genmii_restart_aneg(struct uec_mii_info *mii_info)
{
u16 ctl;
@ -300,14 +309,14 @@ static void genmii_restart_aneg (struct uec_mii_info *mii_info)
uec_phy_write(mii_info, MII_BMCR, ctl);
}
static int gbit_config_aneg (struct uec_mii_info *mii_info)
static int gbit_config_aneg(struct uec_mii_info *mii_info)
{
u16 adv;
u32 advertise;
if (mii_info->autoneg) {
/* Configure the ADVERTISE register */
config_genmii_advert (mii_info);
config_genmii_advert(mii_info);
advertise = mii_info->advertising;
adv = uec_phy_read(mii_info, MII_CTRL1000);
@ -320,18 +329,21 @@ static int gbit_config_aneg (struct uec_mii_info *mii_info)
uec_phy_write(mii_info, MII_CTRL1000, adv);
/* Start/Restart aneg */
genmii_restart_aneg (mii_info);
} else
genmii_setup_forced (mii_info);
genmii_restart_aneg(mii_info);
} else {
genmii_setup_forced(mii_info);
}
return 0;
}
static int marvell_config_aneg (struct uec_mii_info *mii_info)
static int marvell_config_aneg(struct uec_mii_info *mii_info)
{
/* The Marvell PHY has an errata which requires
/*
* The Marvell PHY has an errata which requires
* that certain registers get written in order
* to restart autonegotiation */
* to restart autonegotiation
*/
uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
uec_phy_write(mii_info, 0x1d, 0x1f);
@ -340,16 +352,18 @@ static int marvell_config_aneg (struct uec_mii_info *mii_info)
uec_phy_write(mii_info, 0x1e, 0);
uec_phy_write(mii_info, 0x1e, 0x100);
gbit_config_aneg (mii_info);
gbit_config_aneg(mii_info);
return 0;
}
static int genmii_config_aneg (struct uec_mii_info *mii_info)
static int genmii_config_aneg(struct uec_mii_info *mii_info)
{
if (mii_info->autoneg) {
/* Speed up the common case, if link is already up, speed and
duplex match, skip auto neg as it already matches */
/*
* Speed up the common case, if link is already up, speed and
* duplex match, skip auto neg as it already matches
*/
if (!genmii_read_status(mii_info) && mii_info->link)
if (mii_info->duplex == DUPLEX_FULL &&
mii_info->speed == SPEED_100)
@ -357,15 +371,16 @@ static int genmii_config_aneg (struct uec_mii_info *mii_info)
ADVERTISED_100baseT_Full)
return 0;
config_genmii_advert (mii_info);
genmii_restart_aneg (mii_info);
} else
genmii_setup_forced (mii_info);
config_genmii_advert(mii_info);
genmii_restart_aneg(mii_info);
} else {
genmii_setup_forced(mii_info);
}
return 0;
}
static int genmii_update_link (struct uec_mii_info *mii_info)
static int genmii_update_link(struct uec_mii_info *mii_info)
{
u16 status;
@ -377,8 +392,8 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
* (ie - we're capable and it's not done)
*/
status = uec_phy_read(mii_info, MII_BMSR);
if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE)
&& !(status & BMSR_ANEGCOMPLETE)) {
if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) &&
!(status & BMSR_ANEGCOMPLETE)) {
int i = 0;
while (!(status & BMSR_ANEGCOMPLETE)) {
@ -405,14 +420,13 @@ static int genmii_update_link (struct uec_mii_info *mii_info)
return 0;
}
static int genmii_read_status (struct uec_mii_info *mii_info)
static int genmii_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there
* was an error */
err = genmii_update_link (mii_info);
/* Update the link, but return if there was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
@ -449,13 +463,13 @@ static int genmii_read_status (struct uec_mii_info *mii_info)
static int bcm_init(struct uec_mii_info *mii_info)
{
struct eth_device *edev = mii_info->dev;
uec_private_t *uec = edev->priv;
struct uec_priv *uec = edev->priv;
gbit_config_aneg(mii_info);
if ((uec->uec_info->enet_interface_type ==
PHY_INTERFACE_MODE_RGMII_RXID) &&
(uec->uec_info->speed == SPEED_1000)) {
if (uec->uec_info->enet_interface_type ==
PHY_INTERFACE_MODE_RGMII_RXID &&
uec->uec_info->speed == SPEED_1000) {
u16 val;
int cnt = 50;
@ -476,18 +490,18 @@ static int bcm_init(struct uec_mii_info *mii_info)
uec_phy_write(mii_info, 0x18, val);
}
return 0;
return 0;
}
static int uec_marvell_init(struct uec_mii_info *mii_info)
{
struct eth_device *edev = mii_info->dev;
uec_private_t *uec = edev->priv;
struct uec_priv *uec = edev->priv;
phy_interface_t iface = uec->uec_info->enet_interface_type;
int speed = uec->uec_info->speed;
if ((speed == SPEED_1000) &&
(iface == PHY_INTERFACE_MODE_RGMII_ID ||
if (speed == SPEED_1000 &&
(iface == PHY_INTERFACE_MODE_RGMII_ID ||
iface == PHY_INTERFACE_MODE_RGMII_RXID ||
iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
int temp;
@ -515,20 +529,21 @@ static int uec_marvell_init(struct uec_mii_info *mii_info)
return 0;
}
static int marvell_read_status (struct uec_mii_info *mii_info)
static int marvell_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there
* was an error */
err = genmii_update_link (mii_info);
/* Update the link, but return if there was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
/* If the link is up, read the speed and duplex */
/* If we aren't autonegotiating, assume speeds
* are as set */
/*
* If the link is up, read the speed and duplex
* If we aren't autonegotiating, assume speeds
* are as set
*/
if (mii_info->autoneg && mii_info->link) {
int speed;
@ -559,7 +574,7 @@ static int marvell_read_status (struct uec_mii_info *mii_info)
return 0;
}
static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
{
/* Clear the interrupts by reading the reg */
uec_phy_read(mii_info, MII_M1011_IEVENT);
@ -567,18 +582,18 @@ static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
return 0;
}
static int marvell_config_intr (struct uec_mii_info *mii_info)
static int marvell_config_intr(struct uec_mii_info *mii_info)
{
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
else
uec_phy_write(mii_info, MII_M1011_IMASK,
MII_M1011_IMASK_CLEAR);
MII_M1011_IMASK_CLEAR);
return 0;
}
static int dm9161_init (struct uec_mii_info *mii_info)
static int dm9161_init(struct uec_mii_info *mii_info)
{
/* Reset the PHY */
uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
@ -589,29 +604,31 @@ static int dm9161_init (struct uec_mii_info *mii_info)
uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
config_genmii_advert (mii_info);
config_genmii_advert(mii_info);
/* Start/restart aneg */
genmii_config_aneg (mii_info);
genmii_config_aneg(mii_info);
return 0;
}
static int dm9161_config_aneg (struct uec_mii_info *mii_info)
static int dm9161_config_aneg(struct uec_mii_info *mii_info)
{
return 0;
}
static int dm9161_read_status (struct uec_mii_info *mii_info)
static int dm9161_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there was an error */
err = genmii_update_link (mii_info);
err = genmii_update_link(mii_info);
if (err)
return err;
/* If the link is up, read the speed and duplex
If we aren't autonegotiating assume speeds are as set */
/*
* If the link is up, read the speed and duplex
* If we aren't autonegotiating assume speeds are as set
*/
if (mii_info->autoneg && mii_info->link) {
status = uec_phy_read(mii_info, MII_DM9161_SCSR);
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
@ -628,7 +645,7 @@ static int dm9161_read_status (struct uec_mii_info *mii_info)
return 0;
}
static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
{
/* Clear the interrupt by reading the reg */
uec_phy_read(mii_info, MII_DM9161_INTR);
@ -636,7 +653,7 @@ static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
return 0;
}
static int dm9161_config_intr (struct uec_mii_info *mii_info)
static int dm9161_config_intr(struct uec_mii_info *mii_info)
{
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
@ -646,23 +663,23 @@ static int dm9161_config_intr (struct uec_mii_info *mii_info)
return 0;
}
static void dm9161_close (struct uec_mii_info *mii_info)
static void dm9161_close(struct uec_mii_info *mii_info)
{
}
static int fixed_phy_aneg (struct uec_mii_info *mii_info)
static int fixed_phy_aneg(struct uec_mii_info *mii_info)
{
mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
return 0;
}
static int fixed_phy_read_status (struct uec_mii_info *mii_info)
static int fixed_phy_read_status(struct uec_mii_info *mii_info)
{
int i = 0;
for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
strlen(mii_info->dev->name)) == 0) {
strlen(mii_info->dev->name)) == 0) {
mii_info->speed = fixed_phy_port[i].speed;
mii_info->duplex = fixed_phy_port[i].duplex;
mii_info->link = 1; /* Link is always UP */
@ -673,25 +690,26 @@ static int fixed_phy_read_status (struct uec_mii_info *mii_info)
return 0;
}
static int smsc_config_aneg (struct uec_mii_info *mii_info)
static int smsc_config_aneg(struct uec_mii_info *mii_info)
{
return 0;
}
static int smsc_read_status (struct uec_mii_info *mii_info)
static int smsc_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there
* was an error */
err = genmii_update_link (mii_info);
/* Update the link, but return if there was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
/* If the link is up, read the speed and duplex */
/* If we aren't autonegotiating, assume speeds
* are as set */
/*
* If the link is up, read the speed and duplex
* If we aren't autonegotiating, assume speeds
* are as set
*/
if (mii_info->autoneg && mii_info->link) {
int val;
@ -699,22 +717,22 @@ static int smsc_read_status (struct uec_mii_info *mii_info)
val = (status & 0x1c) >> 2;
switch (val) {
case 1:
mii_info->duplex = DUPLEX_HALF;
mii_info->speed = SPEED_10;
break;
case 5:
mii_info->duplex = DUPLEX_FULL;
mii_info->speed = SPEED_10;
break;
case 2:
mii_info->duplex = DUPLEX_HALF;
mii_info->speed = SPEED_100;
break;
case 6:
mii_info->duplex = DUPLEX_FULL;
mii_info->speed = SPEED_100;
break;
case 1:
mii_info->duplex = DUPLEX_HALF;
mii_info->speed = SPEED_10;
break;
case 5:
mii_info->duplex = DUPLEX_FULL;
mii_info->speed = SPEED_10;
break;
case 2:
mii_info->duplex = DUPLEX_HALF;
mii_info->speed = SPEED_100;
break;
case 6:
mii_info->duplex = DUPLEX_FULL;
mii_info->speed = SPEED_100;
break;
}
mii_info->pause = 0;
}
@ -803,25 +821,25 @@ static struct phy_info *phy_info[] = {
NULL
};
u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
{
return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
}
void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
{
mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
}
/* Use the PHY ID registers to determine what type of PHY is attached
* to device dev. return a struct phy_info structure describing that PHY
*/
struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info)
{
u16 phy_reg;
u32 phy_ID;
int i;
struct phy_info *theInfo = NULL;
struct phy_info *info = NULL;
/* Grab the bits from PHYIR1, and put them in the upper half */
phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
@ -836,30 +854,29 @@ struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
for (i = 0; phy_info[i]; i++)
if (phy_info[i]->phy_id ==
(phy_ID & phy_info[i]->phy_id_mask)) {
theInfo = phy_info[i];
info = phy_info[i];
break;
}
/* This shouldn't happen, as we have generic PHY support */
if (theInfo == NULL) {
ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
if (!info) {
ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
return NULL;
} else {
ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
}
ugphy_info("UEC: PHY is %s (%x)", info->name, phy_ID);
return theInfo;
return info;
}
void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
int speed)
int speed)
{
uec_private_t *uec = (uec_private_t *) dev->priv;
struct uec_priv *uec = (struct uec_priv *)dev->priv;
struct uec_mii_info *mii_info;
u16 status;
if (!uec->mii_info) {
printf ("%s: the PHY not initialized\n", __FUNCTION__);
printf("%s: the PHY not initialized\n", __func__);
return;
}
mii_info = uec->mii_info;
@ -903,10 +920,11 @@ void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
/* now the B2 will correctly report autoneg completion status */
}
void change_phy_interface_mode (struct eth_device *dev,
phy_interface_t type, int speed)
void change_phy_interface_mode(struct eth_device *dev,
phy_interface_t type, int speed)
{
#ifdef CONFIG_PHY_MODE_NEED_CHANGE
marvell_phy_interface_mode (dev, type, speed);
marvell_phy_interface_mode(dev, type, speed);
#endif
}
#endif

71
drivers/qe/uec_phy.h
View File

@ -11,6 +11,8 @@
#ifndef __UEC_PHY_H__
#define __UEC_PHY_H__
#include <linux/bitops.h>
#define MII_end ((u32)-2)
#define MII_read ((u32)-1)
@ -93,8 +95,8 @@
#define MII_DM9161_INTR_LINK_CHANGE 0x0004
#define MII_DM9161_INTR_INIT 0x0000
#define MII_DM9161_INTR_STOP \
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
| MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
/* DM9161 10BT Configuration/Status */
#define MII_DM9161_10BTCSR 0x12
@ -125,35 +127,6 @@
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
/* Indicates what features are supported by the interface. */
#define SUPPORTED_10baseT_Half (1 << 0)
#define SUPPORTED_10baseT_Full (1 << 1)
#define SUPPORTED_100baseT_Half (1 << 2)
#define SUPPORTED_100baseT_Full (1 << 3)
#define SUPPORTED_1000baseT_Half (1 << 4)
#define SUPPORTED_1000baseT_Full (1 << 5)
#define SUPPORTED_Autoneg (1 << 6)
#define SUPPORTED_TP (1 << 7)
#define SUPPORTED_AUI (1 << 8)
#define SUPPORTED_MII (1 << 9)
#define SUPPORTED_FIBRE (1 << 10)
#define SUPPORTED_BNC (1 << 11)
#define SUPPORTED_10000baseT_Full (1 << 12)
#define ADVERTISED_10baseT_Half (1 << 0)
#define ADVERTISED_10baseT_Full (1 << 1)
#define ADVERTISED_100baseT_Half (1 << 2)
#define ADVERTISED_100baseT_Full (1 << 3)
#define ADVERTISED_1000baseT_Half (1 << 4)
#define ADVERTISED_1000baseT_Full (1 << 5)
#define ADVERTISED_Autoneg (1 << 6)
#define ADVERTISED_TP (1 << 7)
#define ADVERTISED_AUI (1 << 8)
#define ADVERTISED_MII (1 << 9)
#define ADVERTISED_FIBRE (1 << 10)
#define ADVERTISED_BNC (1 << 11)
#define ADVERTISED_10000baseT_Full (1 << 12)
/* Taken from mii_if_info and sungem_phy.h */
struct uec_mii_info {
/* Information about the PHY type */
@ -184,9 +157,9 @@ struct uec_mii_info {
void *priv;
/* Provided by ethernet driver */
int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
int val);
int (*mdio_read)(struct eth_device *dev, int mii_id, int reg);
void (*mdio_write)(struct eth_device *dev, int mii_id, int reg,
int val);
};
/* struct phy_info: a structure which defines attributes for a PHY
@ -208,32 +181,34 @@ struct phy_info {
u32 features;
/* Called to initialize the PHY */
int (*init) (struct uec_mii_info * mii_info);
int (*init)(struct uec_mii_info *mii_info);
/* Called to suspend the PHY for power */
int (*suspend) (struct uec_mii_info * mii_info);
int (*suspend)(struct uec_mii_info *mii_info);
/* Reconfigures autonegotiation (or disables it) */
int (*config_aneg) (struct uec_mii_info * mii_info);
int (*config_aneg)(struct uec_mii_info *mii_info);
/* Determines the negotiated speed and duplex */
int (*read_status) (struct uec_mii_info * mii_info);
int (*read_status)(struct uec_mii_info *mii_info);
/* Clears any pending interrupts */
int (*ack_interrupt) (struct uec_mii_info * mii_info);
int (*ack_interrupt)(struct uec_mii_info *mii_info);
/* Enables or disables interrupts */
int (*config_intr) (struct uec_mii_info * mii_info);
int (*config_intr)(struct uec_mii_info *mii_info);
/* Clears up any memory if needed */
void (*close) (struct uec_mii_info * mii_info);
void (*close)(struct uec_mii_info *mii_info);
};
struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
int value);
int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
u32 interrupts);
struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info);
void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
int value);
int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
u32 interrupts);
void change_phy_interface_mode(struct eth_device *dev,
phy_interface_t type, int speed);
#endif /* __UEC_PHY_H__ */

14
include/configs/km/km-mpc832x.h
View File

@ -10,20 +10,6 @@
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
/*
* System IO Config
*/

14
include/configs/km/km-mpc8360.h
View File

@ -6,20 +6,6 @@
* High Level Configuration Options
*/
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
/*
* System IO Setup
*/

10
include/configs/km/km-mpc83xx.h
View File

@ -61,16 +61,6 @@
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_NUM_I2C_BUSES 4

3
include/fsl_qe.h
View File

@ -296,4 +296,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware,
qe_map_t *qe_immrr);
#endif
#if defined(CONFIG_PINCTRL)
int par_io_of_config(struct udevice *dev);
#endif
#endif /* __QE_H__ */