fsl_esdhc: Add the workaround for erratum ESDHC136 (enable on P4080)
False multi-bit ECC errors will be reported by the eSDHC buffer which can trigger a reset request. We disable all ECC error checking on SDHC. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -55,6 +55,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
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puts("Work-around for Erratum ESDHC135 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
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puts("Work-around for Erratum ESDHC136 enabled\n");
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#endif
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return 0;
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}
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@ -394,6 +394,14 @@ int cpu_init_r(void)
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setup_mp();
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
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{
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void *p;
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p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
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setbits_be32(p, 1 << (31 - 14));
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}
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#endif
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#ifdef CONFIG_SYS_LBC_LCRR
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/*
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* Modify the CLKDIV field of LCRR register to improve the writing
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@ -37,6 +37,7 @@
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
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#define CONFIG_SYS_P4080_ERRATUM_CPU22
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#define CONFIG_SYS_P4080_ERRATUM_SERDES8
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