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x86: crownbay: Add SPI flash support

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The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2014-12-17 15:50:44 +08:00 committed by Simon Glass
parent 63faf2507d
commit adfe3b247a
3 changed files with 42 additions and 1 deletions
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26
arch/x86/cpu/queensbay/tnc.c
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@ -6,18 +6,42 @@
#include <common.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/arch/tnc.h>
#include <asm/arch/fsp/fsp_support.h>
#include <asm/processor.h>
static void unprotect_spi_flash(void)
{
u32 bc;
bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
bc |= 0x1; /* unprotect the flash */
pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
}
int arch_cpu_init(void)
{
struct pci_controller *hose;
int ret;
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
return x86_cpu_init_f();
ret = x86_cpu_init_f();
if (ret)
return ret;
ret = pci_early_init_hose(&hose);
if (ret)
return ret;
unprotect_spi_flash();
return 0;
}
int print_cpuinfo(void)

15
arch/x86/include/asm/arch-queensbay/tnc.h Normal file
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@ -0,0 +1,15 @@
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _X86_ARCH_TNC_H_
#define _X86_ARCH_TNC_H_
#include <pci.h>
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
#endif /* _X86_ARCH_TNC_H_ */

2
include/configs/crownbay.h
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@ -45,6 +45,8 @@
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
#define CONFIG_SPI_FLASH_SST
/* Video is not supported */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE