board: topic-miamiplus: Run IO PLL at 1000 MHz
The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so change it to run at 1000 and adjust the divisors accordingly. Also set the GEM0 clock source to MIO instead of EMIO. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -24,8 +24,8 @@ static unsigned long ps7_pll_init_data_3_0[] = {
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EMIT_MASKPOLL(0XF800010C, 0x00000002U),
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EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
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EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
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EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x00113220U),
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EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00024000U),
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EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001452C0U),
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EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x0001E000U),
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EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
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EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
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EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
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@ -37,20 +37,18 @@ static unsigned long ps7_pll_init_data_3_0[] = {
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static unsigned long ps7_clock_init_data_3_0[] = {
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EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
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EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00302301U),
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EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000011U),
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EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00700F01U),
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EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
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EMIT_MASKWRITE(0XF800013C, 0x00000011U, 0x00000011U),
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EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100141U),
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EMIT_MASKWRITE(0XF8000144, 0x03F03F71U, 0x00100141U),
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EMIT_MASKWRITE(0XF8000148, 0x00003F31U, 0x00000C01U),
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EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000601U),
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EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001803U),
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EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000C03U),
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EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000601U),
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EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000601U),
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EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100C00U),
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EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100C00U),
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EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100600U),
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EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
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EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
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EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
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EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A03U),
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EMIT_MASKWRITE(0XF8000158, 0x00003F33U, 0x00000501U),
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EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
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EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00200500U),
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EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
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EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
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EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101800U),
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EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
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EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01FC4C4DU),
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@ -88,7 +86,7 @@ static unsigned long ps7_ddr_init_data_3_0[] = {
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EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
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EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
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EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
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EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
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EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB52U),
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EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
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EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
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EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
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