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MIPS: Fix invalidate_dcache_range to operate on L1 Dcache

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Commit fb64cda579 ("MIPS: Abstract cache op loops with a macro")
accidentally modified invalidate_dcache_range to operate on the L1
Icache instead of the Dcache. Fix the cache op used to operate on the
Dcache.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Fixes: fb64cda579 ("MIPS: Abstract cache op loops with a macro")
This commit is contained in:
Paul Burton 2016-06-09 13:09:51 +01:00 committed by Daniel Schwierzeck
parent 6b3943f1b0
commit a95800e881
1 changed files with 1 additions and 1 deletions
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2
arch/mips/lib/cache.c
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@ -91,5 +91,5 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
if (start_addr == stop)
return;
cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_I);
cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
}