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x86: qemu: Enable writing MP table

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Enable writing MP table for QEMU boads (i440fx and q35).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2015-07-22 01:21:13 -07:00 committed by Simon Glass
parent c77b8912d8
commit a8ebf283e9
4 changed files with 58 additions and 3 deletions
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34
arch/x86/cpu/qemu/pci.c
View File

@ -13,6 +13,8 @@
DECLARE_GLOBAL_DATA_PTR;
static bool i440fx;
void board_pci_setup_hose(struct pci_controller *hose)
{
hose->first_busno = 0;
@ -61,7 +63,8 @@ int board_pci_post_scan(struct pci_controller *hose)
* PCI device ID.
*/
device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID);
pam = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_PAM : Q35_PAM;
i440fx = (device == PCI_DEVICE_ID_INTEL_82441);
pam = i440fx ? I440FX_PAM : Q35_PAM;
/*
* Initialize Programmable Attribute Map (PAM) Registers
@ -71,7 +74,7 @@ int board_pci_post_scan(struct pci_controller *hose)
for (i = 0; i < PAM_NUM; i++)
x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW);
if (device == PCI_DEVICE_ID_INTEL_82441) {
if (i440fx) {
/*
* Enable legacy IDE I/O ports decode
*
@ -97,10 +100,35 @@ int board_pci_post_scan(struct pci_controller *hose)
* board, it shows as device 2, while for Q35 and ICH9 chipset board,
* it shows as device 1.
*/
vga = (device == PCI_DEVICE_ID_INTEL_82441) ? I440FX_VGA : Q35_VGA;
vga = i440fx ? I440FX_VGA : Q35_VGA;
start = get_timer(0);
ret = pci_run_vga_bios(vga, NULL, PCI_ROM_USE_NATIVE);
debug("BIOS ran in %lums\n", get_timer(start));
return ret;
}
#ifdef CONFIG_GENERATE_MP_TABLE
int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq)
{
u8 irq;
if (i440fx) {
/*
* Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not
* connected to I/O APIC INTPIN#16-19. Instead they are routed
* to an irq number controled by the PIRQ routing register.
*/
irq = x86_pci_read_config8(PCI_BDF(bus, dev, func),
PCI_INTERRUPT_LINE);
} else {
/*
* ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7.
* PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11].
*/
irq = pirq < 8 ? pirq + 16 : pirq + 12;
}
return irq;
}
#endif

12
arch/x86/dts/qemu-x86_i440fx.dts
View File

@ -24,6 +24,18 @@
stdout-path = "/serial";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "cpu-x86";
reg = <0>;
intel,apic-id = <0>;
};
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

12
arch/x86/dts/qemu-x86_q35.dts
View File

@ -35,6 +35,18 @@
stdout-path = "/serial";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "cpu-x86";
reg = <0>;
intel,apic-id = <0>;
};
};
pci {
compatible = "pci-x86";
#address-cells = <3>;

3
configs/qemu-x86_defconfig
View File

@ -1,6 +1,8 @@
CONFIG_X86=y
CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
@ -9,6 +11,7 @@ CONFIG_BOOTSTAGE=y
CONFIG_BOOTSTAGE_REPORT=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_CONTROL=y
CONFIG_CPU=y
CONFIG_SPI_FLASH=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y