leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

Browse Source
This commit is contained in:
Tom Rini 2012-11-28 08:30:21 -07:00
commit a86fcff695
46 changed files with 1207 additions and 109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -24,6 +24,109 @@
#include <command.h>
#include <linux/compiler.h>
#include <asm/processor.h>
#include "fsl_corenet_serdes.h"
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/*
* This work-around is implemented in PBI, so just check to see if the
* work-around was actually applied. To do this, we check for specific data
* at specific addresses in DCSR.
*
* Array offsets[] contains a list of offsets within DCSR. According to the
* erratum document, the value at each offset should be 2.
*/
static void check_erratum_a4849(uint32_t svr)
{
void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
unsigned int i;
#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
static const uint8_t offsets[] = {
0x50, 0x54, 0x58, 0x90, 0x94, 0x98
};
#endif
#ifdef CONFIG_PPC_P4080
static const uint8_t offsets[] = {
0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
};
#endif
uint32_t x108; /* The value that should be at offset 0x108 */
for (i = 0; i < ARRAY_SIZE(offsets); i++) {
if (in_be32(dcsr + offsets[i]) != 2) {
printf("Work-around for Erratum A004849 is not enabled\n");
return;
}
}
#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
x108 = 0x12;
#endif
#ifdef CONFIG_PPC_P4080
/*
* For P4080, the erratum document says that the value at offset 0x108
* should be 0x12 on rev2, or 0x1c on rev3.
*/
if (SVR_MAJ(svr) == 2)
x108 = 0x12;
if (SVR_MAJ(svr) == 3)
x108 = 0x1c;
#endif
if (in_be32(dcsr + 0x108) != x108) {
printf("Work-around for Erratum A004849 is not enabled\n");
return;
}
/* Everything matches, so the erratum work-around was applied */
printf("Work-around for Erratum A004849 enabled\n");
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
/*
* This work-around is implemented in PBI, so just check to see if the
* work-around was actually applied. To do this, we check for specific data
* at specific addresses in the SerDes register block.
*
* The work-around says that for each SerDes lane, write BnTTLCRy0 =
* 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
*/
static void check_erratum_a4580(uint32_t svr)
{
const serdes_corenet_t __iomem *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned int lane;
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
if (serdes_lane_enabled(lane)) {
const struct serdes_lane __iomem *srds_lane =
&srds_regs->lane[serdes_get_lane_idx(lane)];
/*
* Verify that the values we were supposed to write in
* the PBI are actually there. Also, the lower 15
* bits of res4[3] should be the same as the upper 15
* bits of res4[1].
*/
if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
(in_be32(&srds_lane->res4[1]) != 0x880000) ||
(in_be32(&srds_lane->res4[3]) != 0x40000044)) {
printf("Work-around for Erratum A004580 is "
"not enabled\n");
return;
}
}
}
/* Everything matches, so the erratum work-around was applied */
printf("Work-around for Erratum A004580 enabled\n");
}
#endif
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@ -136,6 +239,17 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
puts("Work-around for Erratum A004934 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4580(svr);
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
puts("Work-around for Erratum PCIe-A003 enabled\n");
#endif
return 0;
}

14
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -451,21 +451,21 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
break;
#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
break;
#endif
default:

12
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -350,6 +350,10 @@ int cpu_init_r(void)
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
extern int spin_table_compat;
const char *spin;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
@ -395,6 +399,14 @@ int cpu_init_r(void)
}
#endif
#if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
spin = getenv("spin_table_compat");
if (spin && (*spin == 'n'))
spin_table_compat = 0;
else
spin_table_compat = 1;
#endif
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)

4
arch/powerpc/cpu/mpc85xx/ddr-gen1.c
View File

@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
if (ctrl_num != 0) {
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@ -73,7 +73,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
void
ddr_enable_ecc(unsigned int dram_size)
{
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);

9
arch/powerpc/cpu/mpc85xx/ddr-gen2.c
View File

@ -19,14 +19,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
unsigned int ctrl_num)
{
unsigned int i;
#ifdef CONFIG_MPC83xx
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
#else
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
uint svr;
#endif
#endif
if (ctrl_num) {

14
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
View File

@ -32,21 +32,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
break;
#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
case 1:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
case 2:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
case 3:
ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
break;
#endif
default:

20
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@ -714,9 +714,13 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
/*
* Set BnTTLCRy0[FLT_SEL] = 000011 and set BnTTLCRy0[17] = 1 for
* each of the SerDes lanes selected as SGMII, XAUI, SRIO, or
* AURORA before the device is initialized.
* Set BnTTLCRy0[FLT_SEL] = 011011 and set BnTTLCRy0[31] = 1
* for each of the SerDes lanes selected as SGMII, XAUI, SRIO,
* or AURORA before the device is initialized.
*
* Note that this part of the SERDES-9 work-around is
* redundant if the work-around for A-4580 has already been
* applied via PBI.
*/
switch (lane_prtcl) {
case SGMII_FM1_DTSEC1:
@ -733,10 +737,12 @@ void fsl_serdes_init(void)
case SRIO1:
case SRIO2:
case AURORA:
clrsetbits_be32(&srds_regs->lane[idx].ttlcr0,
SRDS_TTLCR0_FLT_SEL_MASK,
SRDS_TTLCR0_FLT_SEL_750PPM |
SRDS_TTLCR0_PM_DIS);
out_be32(&srds_regs->lane[idx].ttlcr0,
SRDS_TTLCR0_FLT_SEL_KFR_26 |
SRDS_TTLCR0_FLT_SEL_KPH_28 |
SRDS_TTLCR0_FLT_SEL_750PPM |
SRDS_TTLCR0_FREQOVD_EN);
break;
default:
break;
}

35
arch/powerpc/cpu/mpc85xx/release.S
View File

@ -351,6 +351,13 @@ __secondary_reset_vector:
.align L1_CACHE_SHIFT
.global __second_half_boot_page
__second_half_boot_page:
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
lis r3,(spin_table_compat - __second_half_boot_page)@h
ori r3,r3,(spin_table_compat - __second_half_boot_page)@l
add r3,r3,r11 /* r11 has the address of __second_half_boot_page */
lwz r14,0(r3)
#endif
#define EPAPR_MAGIC 0x45504150
#define ENTRY_ADDR_UPPER 0
#define ENTRY_ADDR_LOWER 4
@ -383,7 +390,24 @@ __second_half_boot_page:
stw r8,ENTRY_ADDR_LOWER(r10)
/* spin waiting for addr */
3: lwz r4,ENTRY_ADDR_LOWER(r10)
3:
/*
* To comply with ePAPR 1.1, the spin table has been moved to cache-enabled
* memory. Old OS may not work with this change. A patch is waiting to be
* accepted for Linux kernel. Other OS needs similar fix to spin table.
* For OSes with old spin table code, we can enable this temporary fix by
* setting environmental variable "spin_table_compat". For new OSes, set
* "spin_table_compat=no". After Linux is fixed, we can remove this macro
* and related code. For now, it is enabled by default.
*/
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
cmpwi r14,0
beq 4f
dcbf 0, r10
sync
4:
#endif
lwz r4,ENTRY_ADDR_LOWER(r10)
andi. r11,r4,1
bne 3b
isync
@ -460,5 +484,14 @@ __second_half_boot_page:
.globl __spin_table
__spin_table:
.space CONFIG_MAX_CPUS*ENTRY_SIZE
#ifdef CONFIG_PPC_SPINTABLE_COMPATIBLE
.align L1_CACHE_SHIFT
.global spin_table_compat
spin_table_compat:
.long 1
#endif
__spin_table_end:
.space 4096 - (__spin_table_end - __spin_table)

4
arch/powerpc/cpu/mpc86xx/ddr-8641.c
View File

@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) {
case 0:
ddr = (void *)CONFIG_SYS_MPC86xx_DDR_ADDR;
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
break;
case 1:
ddr = (void *)CONFIG_SYS_MPC86xx_DDR2_ADDR;
ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
break;
default:
printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);

10
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -18,15 +18,7 @@
#include "ddr.h"
#ifdef CONFIG_MPC83xx
#define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
#elif defined(CONFIG_MPC85xx)
#define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
#elif defined(CONFIG_MPC86xx)
#define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
#else
#error "Undefined _DDR_ADDR"
#endif
#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
static u32 fsl_ddr_get_version(void)
{

14
arch/powerpc/cpu/mpc8xxx/ddr/util.c
View File

@ -133,14 +133,8 @@ u32 fsl_ddr_get_intl3r(void)
void board_add_ram_info(int use_default)
{
#if defined(CONFIG_MPC83xx)
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
ccsr_ddr_t *ddr = (void *)&immap->ddr;
#elif defined(CONFIG_MPC85xx)
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
#elif defined(CONFIG_MPC86xx)
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
#endif
ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
#endif
@ -152,13 +146,13 @@ void board_add_ram_info(int use_default)
#if CONFIG_NUM_DDR_CONTROLLERS >= 2
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
}
#endif
#if CONFIG_NUM_DDR_CONTROLLERS >= 3
if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
sdram_cfg = in_be32(&ddr->sdram_cfg);
}
#endif

6
arch/powerpc/cpu/mpc8xxx/fdt.c
View File

@ -217,7 +217,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
#if CONFIG_SYS_FSL_SEC_COMPAT == 2 /* SEC 2.x/3.x */
void fdt_fixup_crypto_node(void *blob, int sec_rev)
{
const struct sec_rev_prop {
static const struct sec_rev_prop {
u32 sec_rev;
u32 num_channels;
u32 channel_fifo_len;
@ -232,8 +232,8 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
{ 0x0301, 4, 24, 0xbfe, 0x03ab0ebf }, /* SEC 3.1 */
{ 0x0303, 4, 24, 0x97c, 0x03a30abf }, /* SEC 3.3 */
};
char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
sizeof("fsl,secX.Y")];
static char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
sizeof("fsl,secX.Y")];
int crypto_node, sec_idx, err;
char *p;
u32 val;

20
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -27,6 +27,12 @@
#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
#endif
/*
* This macro should be removed when we no longer care about backwards
* compatibility with older operating systems.
*/
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
#define FSL_DDR_VER_4_7 47
/* Number of TLB CAM entries we have on FSL Book-E chips */
@ -131,7 +137,6 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@ -175,7 +180,6 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -188,7 +192,6 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
@ -242,7 +245,6 @@
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@ -318,7 +320,6 @@
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
@ -343,6 +344,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_A004849
#elif defined(CONFIG_PPC_P3041)
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@ -350,7 +352,6 @@
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
@ -375,6 +376,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_A004849
#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
@ -417,6 +419,9 @@
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#define CONFIG_SYS_FSL_ERRATUM_A004849
#define CONFIG_SYS_FSL_ERRATUM_A004580
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
#define CONFIG_SYS_PPC64 /* 64-bit core */
@ -425,7 +430,6 @@
#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
#define CONFIG_SYS_FSL_NUM_LAWS 32
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
@ -449,6 +453,7 @@
#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
#elif defined(CONFIG_PPC_P5040)
#define CONFIG_SYS_PPC64
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
@ -472,7 +477,6 @@
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_ERRATUM_A004699
#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
#define CONFIG_SYS_FSL_ERRATUM_A004510
#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000

6
arch/powerpc/include/asm/immap_83xx.h
View File

@ -1035,9 +1035,9 @@ typedef struct immap {
} immap_t;
#endif
#define CONFIG_SYS_MPC83xx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_MPC83xx_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CONFIG_SYS_MPC83xx_DMA_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)

27
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2619,7 +2619,7 @@ typedef struct serdes_corenet {
#define SRDS_PCCR2_RST_XGMII1 0x00800000
#define SRDS_PCCR2_RST_XGMII2 0x00400000
u32 res5[197];
struct {
struct serdes_lane {
u32 gcr0; /* General Control Register 0 */
#define SRDS_GCR0_RRST 0x00400000
#define SRDS_GCR0_1STLANE 0x00010000
@ -2637,8 +2637,11 @@ typedef struct serdes_corenet {
u32 res3;
u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
#define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
#define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
#define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
#define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
#define SRDS_TTLCR0_PM_DIS 0x00004000
#define SRDS_TTLCR0_FREQOVD_EN 0x00000001
u32 res4[7];
} lane[24];
u32 res6[384];
@ -2867,9 +2870,9 @@ struct ccsr_pman {
#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
#endif
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000
#define CONFIG_SYS_MPC85xx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
@ -2929,9 +2932,9 @@ struct ccsr_pman {
#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
@ -2998,12 +3001,12 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CONFIG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
#define CONFIG_SYS_MPC85xx_DDR3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR3_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
#define CONFIG_SYS_IFC_ADDR \

8
arch/powerpc/include/asm/immap_86xx.h
View File

@ -1252,10 +1252,10 @@ typedef struct immap {
extern immap_t *immr;
#define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
#define CONFIG_SYS_MPC8xxx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
#define CONFIG_SYS_MPC8xxx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000

2
board/exmeritus/hww1u1a/hww1u1a.c
View File

@ -105,7 +105,7 @@ int checkboard(void)
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");

2
board/freescale/common/Makefile
View File

@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o
COBJS-$(CONFIG_P3041DS) += ics307_clk.o
COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS) += ics307_clk.o
COBJS-$(CONFIG_P5040DS) += ics307_clk.o
COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
# deal with common files for P-series corenet based devices
@ -60,6 +61,7 @@ SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o
SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))

2
board/freescale/common/ngpixis.h
View File

@ -45,7 +45,7 @@ typedef struct ngpixis {
struct {
u8 sw;
u8 en;
} s[8];
} s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */
} __attribute__ ((packed)) ngpixis_t;
/* Pointer to the PIXIS register set */

2
board/freescale/corenet_ds/Makefile
View File

@ -31,9 +31,11 @@ COBJS-y += ddr.o
COBJS-$(CONFIG_P3041DS) += eth_hydra.o
COBJS-$(CONFIG_P4080DS) += eth_p4080.o
COBJS-$(CONFIG_P5020DS) += eth_hydra.o
COBJS-$(CONFIG_P5040DS) += eth_superhydra.o
COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o
COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o
COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o
COBJS-$(CONFIG_P5040DS) += p5040ds_ddr.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))

22
board/freescale/corenet_ds/corenet_ds.c
View File

@ -45,6 +45,7 @@ int checkboard (void)
struct cpu_type *cpu = gd->cpu;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
unsigned int i;
static const char * const freq[] = {"100", "125", "156.25", "212.5" };
printf("Board: %sDS, ", cpu->name);
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
@ -83,20 +84,28 @@ int checkboard (void)
* don't match.
*/
puts("SERDES Reference Clocks: ");
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
|| defined(CONFIG_P5040DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
static const char *freq[] = {"100", "125", "156.25", "212.5" };
unsigned int clock = (sw >> (6 - (2 * i))) & 3;
printf("Bank%u=%sMhz ", i+1, freq[clock]);
}
#ifdef CONFIG_P5040DS
/* On P5040DS, SW11[7:8] determines the Bank 4 frequency */
sw = in_8(&PIXIS_SW(9));
printf("Bank4=%sMhz ", freq[sw & 3]);
#endif
puts("\n");
#else
sw = in_8(&PIXIS_SW(3));
printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100);
printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125");
printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125");
/* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */
/* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */
/* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */
printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]);
printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]);
printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]);
#endif
return 0;
@ -168,7 +177,8 @@ int misc_init_r(void)
unsigned int i;
u8 sw;
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS)
#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \
|| defined(CONFIG_P5040DS)
sw = in_8(&PIXIS_SW(5));
for (i = 0; i < 3; i++) {
unsigned int clock = (sw >> (6 - (2 * i))) & 3;

4
board/freescale/corenet_ds/ddr.c
View File

@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = {
{2, 1250, 4, 6, 0xff, 2, 0},
{2, 1350, 5, 7, 0xff, 2, 0},
{2, 1666, 5, 8, 0xff, 2, 0},
{1, 850, 4, 5, 0xff, 2, 0},
{1, 950, 4, 7, 0xff, 2, 0},
{1, 1250, 4, 6, 0xff, 2, 0},
{1, 1335, 4, 7, 0xff, 2, 0},
{1, 1666, 4, 8, 0xff, 2, 0},
{}
};

722
board/freescale/corenet_ds/eth_superhydra.c Normal file
View File

@ -0,0 +1,722 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
* Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* This file handles the board muxing between the Fman Ethernet MACs and
* the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference
* board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
* provided by the standard Freescale four-port SGMII riser card. The 10Gb
* XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
* and 5 1G interfaces and 10G interface per FMan. Based on the options in
* the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time.
*
* Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
* muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
* always the same (0). The value for SGMII depends on which slot the riser is
* inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
* the value is based on which slot the XAUI is inserted in.
*
* The SERDES configuration is used to determine where the SGMII and XAUI cards
* exist, and also which Fman's MACs are routed to which PHYs. So for a given
* Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
* to PHYs dynamically.
*
*
* This file also updates the device tree in three ways:
*
* 1) The status of each virtual MDIO node that is referenced by an Ethernet
* node is set to "okay".
*
* 2) The phy-handle property of each active Ethernet MAC node is set to the
* appropriate PHY node.
*
* 3) The "mux value" for each virtual MDIO node is set to the correct value,
* if necessary. Some virtual MDIO nodes do not have configurable mux
* values, so those values are hard-coded in the DTS. On the HYDRA board,
* the virtual MDIO node for the SGMII card needs to be updated.
*
* For all this to work, the device tree needs to have the following:
*
* 1) An alias for each PHY node that an Ethernet node could be routed to.
*
* 2) An alias for each real and virtual MDIO node that is disabled by default
* and might need to be enabled, and also might need to have its mux-value
* updated.
*/
#include <common.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
#include <asm/fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
#ifdef CONFIG_FMAN_ENET
#define BRDCFG1_EMI1_SEL_MASK 0x70
#define BRDCFG1_EMI1_SEL_SLOT1 0x10
#define BRDCFG1_EMI1_SEL_SLOT2 0x20
#define BRDCFG1_EMI1_SEL_SLOT5 0x30
#define BRDCFG1_EMI1_SEL_SLOT6 0x40
#define BRDCFG1_EMI1_SEL_SLOT7 0x50
#define BRDCFG1_EMI1_SEL_SLOT3 0x60
#define BRDCFG1_EMI1_SEL_RGMII 0x00
#define BRDCFG1_EMI1_EN 0x08
#define BRDCFG1_EMI2_SEL_MASK 0x06
#define BRDCFG1_EMI2_SEL_SLOT1 0x00
#define BRDCFG1_EMI2_SEL_SLOT2 0x02
#define BRDCFG2_REG_GPIO_SEL 0x20
/*
* BRDCFG1 mask and value for each MAC
*
* This array contains the BRDCFG1 values (in mask/val format) that route the
* MDIO bus to a particular RGMII or SGMII PHY.
*/
static struct {
u8 mask;
u8 val;
} mdio_mux[NUM_FM_PORTS];
/*
* Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
* that the mapping must be determined dynamically, or that the lane maps to
* something other than a board slot
*/
static u8 lane_to_slot[] = {
7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0
};
/*
* Set the board muxing for a given MAC
*
* The MDIO layer calls this function every time it wants to talk to a PHY.
*/
void super_hydra_mux_mdio(u8 mask, u8 val)
{
clrsetbits_8(&pixis->brdcfg1, mask, val);
}
struct super_hydra_mdio {
u8 mask;
u8 val;
struct mii_dev *realbus;
};
static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct super_hydra_mdio *priv = bus->priv;
super_hydra_mux_mdio(priv->mask, priv->val);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct super_hydra_mdio *priv = bus->priv;
super_hydra_mux_mdio(priv->mask, priv->val);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int super_hydra_mdio_reset(struct mii_dev *bus)
{
struct super_hydra_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val)
{
struct mii_dev *bus = miiphy_get_dev_by_name(name);
struct super_hydra_mdio *priv = bus->priv;
priv->mask = mask;
priv->val = val;
}
static int super_hydra_mdio_init(char *realbusname, char *fakebusname)
{
struct super_hydra_mdio *hmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate Hydra MDIO bus\n");
return -1;
}
hmdio = malloc(sizeof(*hmdio));
if (!hmdio) {
printf("Failed to allocate Hydra private data\n");
free(bus);
return -1;
}
bus->read = super_hydra_mdio_read;
bus->write = super_hydra_mdio_write;
bus->reset = super_hydra_mdio_reset;
sprintf(bus->name, fakebusname);
hmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!hmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(hmdio);
return -1;
}
bus->priv = hmdio;
return mdio_register(bus);
}
/*
* Given the following ...
*
* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
* compatible string and 'addr' physical address)
*
* 2) An Fman port
*
* ... update the phy-handle property of the Ethernet node to point to the
* right PHY. This assumes that we already know the PHY for each port. That
* information is stored in mdio_mux[].
*
* The offset of the Fman Ethernet node is also passed in for convenience, but
* it is not used.
*
* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
* Inside the Fman, "ports" are things that connect to MACs. We only call them
* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
* and ports are the same thing.
*/
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
enum srds_prtcl device;
int lane, slot, phy;
char alias[32];
/* RGMII and XGMII are already mapped correctly in the DTS */
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
device = serdes_device_from_fm_port(port);
lane = serdes_get_first_lane(device);
slot = lane_to_slot[lane];
phy = fm_info_get_phy_address(port);
sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
}
}
#define PIXIS_SW2_LANE_23_SEL 0x80
#define PIXIS_SW2_LANE_45_SEL 0x40
#define PIXIS_SW2_LANE_67_SEL_MASK 0x30
#define PIXIS_SW2_LANE_67_SEL_5 0x00
#define PIXIS_SW2_LANE_67_SEL_6 0x20
#define PIXIS_SW2_LANE_67_SEL_7 0x10
#define PIXIS_SW2_LANE_8_SEL 0x08
#define PIXIS_SW2_LANE_1617_SEL 0x04
#define PIXIS_SW11_LANE_9_SEL 0x04
/*
* Initialize the lane_to_slot[] array.
*
* On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
* slots is hard-coded. On the Hydra board, however, the mapping is controlled
* by board switch SW2, so the lane_to_slot[] array needs to be dynamically
* initialized.
*/
static void initialize_lane_to_slot(void)
{
u8 sw2 = in_8(&PIXIS_SW(2));
/* SW11 appears in the programming model as SW9 */
u8 sw11 = in_8(&PIXIS_SW(9));
lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
lane_to_slot[3] = lane_to_slot[2];
lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
lane_to_slot[5] = lane_to_slot[4];
switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
case PIXIS_SW2_LANE_67_SEL_5:
lane_to_slot[6] = 5;
break;
case PIXIS_SW2_LANE_67_SEL_6:
lane_to_slot[6] = 6;
break;
case PIXIS_SW2_LANE_67_SEL_7:
lane_to_slot[6] = 7;
break;
}
lane_to_slot[7] = lane_to_slot[6];
lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3;
lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
lane_to_slot[17] = lane_to_slot[16];
}
#endif /* #ifdef CONFIG_FMAN_ENET */
/*
* Configure the status for the virtual MDIO nodes
*
* Rather than create the virtual MDIO nodes from scratch for each active
* virtual MDIO, we expect the DTS to have the nodes defined already, and we
* only enable the ones that are actually active.
*
* We assume that the DTS already hard-codes the status for all the
* virtual MDIO nodes to "disabled", so all we need to do is enable the
* active ones.
*/
void fdt_fixup_board_enet(void *fdt)
{
#ifdef CONFIG_FMAN_ENET
enum fm_port i;
int lane, slot;
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane >= 0) {
char alias[32];
slot = lane_to_slot[lane];
sprintf(alias, "hydra_sg_slot%u", slot);
fdt_status_okay_by_alias(fdt, alias);
debug("Enabled MDIO node %s (slot %i)\n",
alias, slot);
}
break;
case PHY_INTERFACE_MODE_RGMII:
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
default:
break;
}
}
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
char alias[32];
slot = lane_to_slot[lane];
sprintf(alias, "hydra_xg_slot%u", slot);
fdt_status_okay_by_alias(fdt, alias);
debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
}
#if CONFIG_SYS_NUM_FMAN == 2
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
int idx = i - FM2_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
if (lane >= 0) {
char alias[32];
slot = lane_to_slot[lane];
sprintf(alias, "hydra_sg_slot%u", slot);
fdt_status_okay_by_alias(fdt, alias);
debug("Enabled MDIO node %s (slot %i)\n",
alias, slot);
}
break;
case PHY_INTERFACE_MODE_RGMII:
fdt_status_okay_by_alias(fdt, "hydra_rg");
debug("Enabled MDIO node hydra_rg\n");
break;
default:
break;
}
}
lane = serdes_get_first_lane(XAUI_FM2);
if (lane >= 0) {
char alias[32];
slot = lane_to_slot[lane];
sprintf(alias, "hydra_xg_slot%u", slot);
fdt_status_okay_by_alias(fdt, alias);
debug("Enabled MDIO node %s (slot %i)\n", alias, slot);
}
#endif /* CONFIG_SYS_NUM_FMAN == 2 */
#endif /* CONFIG_FMAN_ENET */
}
/*
* Mapping of SerDes Protocol to MDIO MUX value and PHY address.
*
* Fman 1:
* DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
* Mux Phy | Mux Phy | Mux Phy | Mux Phy
* Value Addr | Value Addr | Value Addr | Value Addr
* 0x00 2 1c | 2 1d | 2 1e | 2 1f
* 0x01 | | 6 1c |
* 0x02 | | 3 1c | 3 1d
* 0x03 2 1c | 2 1d | 2 1e | 2 1f
* 0x04 2 1c | 2 1d | 2 1e | 2 1f
* 0x05 | | 3 1c | 3 1d
* 0x06 2 1c | 2 1d | 2 1e | 2 1f
* 0x07 | | 6 1c |
* 0x11 2 1c | 2 1d | 2 1e | 2 1f
* 0x2a 2 | | 2 1e | 2 1f
* 0x34 6 1c | 6 1d | 4 1e | 4 1f
* 0x35 | | 3 1c | 3 1d
* 0x36 6 1c | 6 1d | 4 1e | 4 1f
* | | |
* Fman 2: | | |
* DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4
* EMI1 | EMI1 | EMI1 | EMI1
* Mux Phy | Mux Phy | Mux Phy | Mux Phy
* Value Addr | Value Addr | Value Addr | Value Addr
* 0x00 | | 6 1c | 6 1d
* 0x01 | | |
* 0x02 | | 6 1c | 6 1d
* 0x03 3 1c | 3 1d | 6 1c | 6 1d
* 0x04 3 1c | 3 1d | 6 1c | 6 1d
* 0x05 | | 6 1c | 6 1d
* 0x06 | | 6 1c | 6 1d
* 0x07 | | |
* 0x11 | | |
* 0x2a | | |
* 0x34 | | |
* 0x35 | | |
* 0x36 | | |
*/
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
printf("Initializing Fman\n");
initialize_lane_to_slot();
/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
memset(mdio_mux, 0, sizeof(mdio_mux));
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_tgec_mdio_init(bis, &tgec_mdio_info);
/* Register the three virtual MDIO front-ends */
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
"SUPER_HYDRA_RGMII_MDIO");
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
"SUPER_HYDRA_FM1_SGMII_MDIO");
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
"SUPER_HYDRA_FM2_SGMII_MDIO");
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
"SUPER_HYDRA_FM1_TGEC_MDIO");
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
"SUPER_HYDRA_FM2_TGEC_MDIO");
/*
* Program the DTSEC PHY addresses assuming that they are all SGMII.
* For any DTSEC that's RGMII, we'll override its PHY address later.
* We assume that DTSEC5 is only used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
#if (CONFIG_SYS_NUM_FMAN == 2)
fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
#endif
switch (srds_prtcl) {
case 0:
case 3:
case 4:
case 6:
case 0x11:
case 0x2a:
case 0x34:
case 0x36:
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
break;
case 1:
case 2:
case 5:
case 7:
case 0x35:
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
break;
default:
printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
switch (slot) {
case 1:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
BRDCFG1_EMI1_EN;
break;
case 2:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
BRDCFG1_EMI1_EN;
break;
case 3:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
BRDCFG1_EMI1_EN;
break;
case 5:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
BRDCFG1_EMI1_EN;
break;
case 6:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
BRDCFG1_EMI1_EN;
break;
case 7:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
BRDCFG1_EMI1_EN;
break;
};
super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
* second on-board RGMII port. The other DTSECs cannot
* be routed to RGMII.
*/
debug("FM1@DTSEC%u is RGMII at address %u\n",
idx + 1, 0);
fm_info_set_phy_address(i, 0);
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
BRDCFG1_EMI1_EN;
super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
/*
* For 10G, we only support one XAUI card per Fman. If present, then we
* force its routing and never touch those bits again, which removes the
* need for Linux to do any muxing. This works because of the way
* BRDCFG1 is defined, but it's a bit hackish.
*
* The PHY address for the XAUI card depends on which slot it's in. The
* macros we use imply that the PHY address is based on which FM, but
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we
* check the actual slot and just use the macros as-is, even though
* the P3041 and P5020 only have one Fman.
*/
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2;
super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
}
fm_info_set_mdio(FM1_10GEC1,
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
#if (CONFIG_SYS_NUM_FMAN == 2)
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
int idx = i - FM2_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
debug("FM2@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
switch (slot) {
case 1:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
BRDCFG1_EMI1_EN;
break;
case 2:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
BRDCFG1_EMI1_EN;
break;
case 3:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
BRDCFG1_EMI1_EN;
break;
case 5:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
BRDCFG1_EMI1_EN;
break;
case 6:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
BRDCFG1_EMI1_EN;
break;
case 7:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
BRDCFG1_EMI1_EN;
break;
};
super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
* second on-board RGMII port. The other DTSECs cannot
* be routed to RGMII.
*/
debug("FM2@DTSEC%u is RGMII at address %u\n",
idx + 1, 1);
fm_info_set_phy_address(i, 1);
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
BRDCFG1_EMI1_EN;
super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman2: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
/*
* For 10G, we only support one XAUI card per Fman. If present, then we
* force its routing and never touch those bits again, which removes the
* need for Linux to do any muxing. This works because of the way
* BRDCFG1 is defined, but it's a bit hackish.
*
* The PHY address for the XAUI card depends on which slot it's in. The
* macros we use imply that the PHY address is based on which FM, but
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we
* check the actual slot and just use the macros as-is, even though
* the P3041 and P5020 only have one Fman.
*/
lane = serdes_get_first_lane(XAUI_FM2);
if (lane >= 0) {
debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1;
super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
}
fm_info_set_mdio(FM2_10GEC1,
miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
#endif
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}

18
board/freescale/corenet_ds/p5040ds_ddr.c Normal file
View File

@ -0,0 +1,18 @@
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* Version 2 as published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{0, 0, NULL}
};

2
board/freescale/mpc8540ads/mpc8540ads.c
View File

@ -184,7 +184,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

2
board/freescale/mpc8560ads/mpc8560ads.c
View File

@ -389,7 +389,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

2
board/freescale/mpc8569mds/mpc8569mds.c
View File

@ -247,7 +247,7 @@ int checkboard (void)
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);

2
board/freescale/p1023rds/p1023rds.c
View File

@ -74,7 +74,7 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);

2
board/freescale/p1_p2_rdb_pc/spl_minimal.c
View File

@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);

2
board/freescale/p2020ds/p2020ds.c
View File

@ -84,7 +84,7 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

2
board/sbc8548/ddr.c
View File

@ -91,7 +91,7 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
*/
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);

2
board/socrates/sdram.c
View File

@ -41,7 +41,7 @@
*/
phys_size_t fixed_sdram(void)
{
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
/*
* Disable memory controller.

1
boards.cfg
View File

@ -849,6 +849,7 @@ P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
P5040DS powerpc mpc85xx corenet_ds freescale
BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa

1
drivers/net/fm/Makefile
View File

@ -44,6 +44,7 @@ COBJS-$(CONFIG_PPC_P2041) += p5020.o
COBJS-$(CONFIG_PPC_P3041) += p5020.o
COBJS-$(CONFIG_PPC_P4080) += p4080.o
COBJS-$(CONFIG_PPC_P5020) += p5020.o
COBJS-$(CONFIG_PPC_P5040) += p5040.o
COBJS-$(CONFIG_PPC_T4240) += t4240.o
COBJS-$(CONFIG_PPC_B4860) += b4860.o
endif

113
drivers/net/fm/p5040.c Normal file
View File

@ -0,0 +1,113 @@
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
[FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1,
[FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2,
[FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3,
[FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4,
[FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5,
[FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2,
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */
if (port == FM1_DTSEC1)
return;
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2)))
return PHY_INTERFACE_MODE_XGMII;
/* handle RGMII first */
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII))
return PHY_INTERFACE_MODE_MII;
if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII))
return PHY_INTERFACE_MODE_MII;
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
case FM1_DTSEC5:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
case FM2_DTSEC1:
case FM2_DTSEC2:
case FM2_DTSEC3:
case FM2_DTSEC4:
case FM2_DTSEC5:
if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
break;
default:
return PHY_INTERFACE_MODE_NONE;
}
return PHY_INTERFACE_MODE_NONE;
}

22
drivers/pci/fsl_pci_init.c
View File

@ -470,6 +470,28 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
}
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
temp32 = in_be32(&srds_regs->srdspccr0);
if ((temp32 >> 28) == 3) {
int i;
out_be32(&srds_regs->srdspccr0, 2 << 28);
setbits_be32(&pci->pdb_stat, 0x08000000);
in_be32(&pci->pdb_stat);
udelay(100);
clrbits_be32(&pci->pdb_stat, 0x08000000);
asm("sync;isync");
for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
udelay(1000);
}
enabled = ltssm >= PCI_LTSSM_L0;
}
}
#endif
if (!enabled) {
/* Let the user know there's no PCIe link */
printf("no link, regs @ 0x%lx\n", pci_info->regs);

1
include/configs/P1010RDB.h
View File

@ -553,6 +553,7 @@ extern unsigned long get_sdram_size(void);
/* SATA */
#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2
#define CONFIG_LIBATA
#ifdef CONFIG_FSL_SATA

1
include/configs/P1022DS.h
View File

@ -360,6 +360,7 @@
/* SATA */
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SATA_MAX_DEVICE 2
#define CONFIG_SATA1

2
include/configs/P1023RDS.h
View File

@ -524,7 +524,7 @@ extern unsigned long get_clock_freq(void);
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000

20
include/configs/P2041RDB.h
View File

@ -202,15 +202,21 @@ unsigned long get_board_sys_clk(unsigned long dummy);
/* Set the local bus clock 1/8 of platform clock */
#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */
/*
* This board doesn't have a promjet connector.
* However, it uses commone corenet board LAW and TLB.
* It is necessary to use the same start address with proper offset.
*/
#define CONFIG_SYS_FLASH_BASE 0xe0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_FLASH_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
BR_PS_16 | BR_V)
#define CONFIG_SYS_FLASH_OR_PRELIM \
((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
@ -294,7 +300,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
@ -539,7 +545,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
@ -560,8 +566,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#endif /* CONFIG_PCI */
/* SATA */
#define CONFIG_FSL_SATA_V2
#ifdef CONFIG_FSL_SATA_V2
#define CONFIG_FSL_SATA
#ifdef CONFIG_FSL_SATA
#define CONFIG_LIBATA
#define CONFIG_SYS_SATA_MAX_DEVICE 2

1
include/configs/P3041DS.h
View File

@ -32,6 +32,7 @@
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_DPAA_RMAN

1
include/configs/P5020DS.h
View File

@ -32,6 +32,7 @@
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_FSL_SATA_V2
#define CONFIG_PCIE3
#define CONFIG_PCIE4
#define CONFIG_SYS_FSL_RAID_ENGINE

40
include/configs/P5040DS.h Normal file
View File

@ -0,0 +1,40 @@
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* P5040 DS board configuration file
*
*/
#define CONFIG_P5040DS
#define CONFIG_PHYS_64BIT
#define CONFIG_PPC_P5040
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
#define CONFIG_MMC
#define CONFIG_NAND_FSL_ELBC
#define CONFIG_PCIE3
#define CONFIG_SYS_FSL_RAID_ENGINE
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h"

2
include/configs/corenet_ds.h
View File

@ -549,7 +549,7 @@
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
#else
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000
#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)

2
nand_spl/board/freescale/p1010rdb/nand_boot.c
View File

@ -35,7 +35,7 @@ unsigned long ddr_freq_mhz;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
/* mask off E bit */
u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));

2
nand_spl/board/freescale/p1023rds/nand_boot.c
View File

@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
/* Fixed sdram init -- doesn't use serial presence detect. */
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);