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x86: Enable ICH6 GPIO controller for coreboot

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Coreboot uses this controller to implement GPIO access.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2012-12-02 03:44:44 +00:00
parent 55ae10f8db
commit a7e6d5496c
1 changed files with 4 additions and 0 deletions
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4
include/configs/coreboot.h
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@ -138,6 +138,9 @@
#undef CONFIG_VIDEO #undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE #undef CONFIG_CFB_CONSOLE
/* x86 GPIOs are accessed through a PCI device */
#define CONFIG_INTEL_ICH6_GPIO
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Command line configuration. * Command line configuration.
*/ */
@ -150,6 +153,7 @@
#define CONFIG_CMD_ECHO #define CONFIG_CMD_ECHO
#undef CONFIG_CMD_FLASH #undef CONFIG_CMD_FLASH
#define CONFIG_CMD_FPGA #define CONFIG_CMD_FPGA
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_IMI #define CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS #undef CONFIG_CMD_IMLS
#define CONFIG_CMD_IRQ #define CONFIG_CMD_IRQ