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Fix wrong QSPI clock calculation for AM4372

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On AM4372 the SPI_GCLK input gets its clock from the PRCM module which
divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4.
See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration.

The QSPI_FCLK therefore needs to take this factor into account and
becomes (192000000 / 4).

Signed-off-by: Stefan Mätje <stefan.maetje@esd.eu>
This commit is contained in:
Stefan Mätje 2021-11-30 01:06:56 +01:00 committed by Tom Rini
parent 5ce7df1078
commit a6e562fe36
1 changed files with 2 additions and 1 deletions
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3
drivers/spi/ti_qspi.c
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@ -30,7 +30,8 @@ DECLARE_GLOBAL_DATA_PTR;
/* ti qpsi register bit masks */
#define QSPI_TIMEOUT 2000000
#define QSPI_FCLK 192000000
/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */
#define QSPI_FCLK (192000000 / 4)
#define QSPI_DRA7XX_FCLK 76800000
#define QSPI_WLEN_MAX_BITS 128
#define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3)