soc: keystone_serdes: create a separate SGMII SerDes driver
This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
This commit is contained in:
Khoronzhuk, Ivan
Tom Rini
parent
497e9e0321
commit
a43febde44
15
arch/arm/include/asm/ti-common/keystone_serdes.h
Normal file
15
arch/arm/include/asm/ti-common/keystone_serdes.h
Normal file
@ -0,0 +1,15 @@
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/*
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* Texas Instruments Keystone SerDes driver
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __TI_KEYSTONE_SERDES_H__
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#define __TI_KEYSTONE_SERDES_H__
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void ks2_serdes_sgmii_156p25mhz_setup(void);
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#endif /* __TI_KEYSTONE_SERDES_H__ */
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@ -19,3 +19,5 @@ obj-$(CONFIG_QE) += qe/
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obj-y += memory/
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obj-y += pwm/
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obj-y += input/
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# SOC specific infrastructure drivers.
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obj-y += soc/
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@ -14,6 +14,7 @@
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#include <malloc.h>
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#include <asm/ti-common/keystone_nav.h>
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#include <asm/ti-common/keystone_net.h>
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#include <asm/ti-common/keystone_serdes.h>
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unsigned int emac_open;
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static unsigned int sys_has_mdio = 1;
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@ -38,6 +39,7 @@ struct rx_buff_desc net_rx_buffs = {
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};
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static void keystone2_eth_mdio_enable(void);
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static void keystone2_net_serdes_setup(void);
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static int gen_get_link_speed(int phy_addr);
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@ -406,7 +408,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis)
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sys_has_mdio =
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(eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0;
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sgmii_serdes_setup_156p25mhz();
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keystone2_net_serdes_setup();
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if (sys_has_mdio)
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keystone2_eth_mdio_enable();
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@ -552,142 +554,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv)
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return 0;
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}
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void sgmii_serdes_setup_156p25mhz(void)
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static void keystone2_net_serdes_setup(void)
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{
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unsigned int cnt;
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/*
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* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
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* hardware vendor published only register addresses and their values
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* to be used for configuring SerDes. So had to use hardcoded values
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* below.
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*/
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clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
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clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
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clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
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clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
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clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
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clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
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clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
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clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
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clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
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clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
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clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
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clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
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clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
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clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
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clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
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clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
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clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
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clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
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clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
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clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
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clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
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clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
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clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
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clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
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clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
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clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
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clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
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clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
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clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
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clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
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/*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
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clrbits_le32(0x0232a010, 1 << 28);
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/* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
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clrbits_le32(0x0232a228, 1 << 29);
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writel(0xF800F8C0, 0x0232bfe0);
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clrbits_le32(0x0232a428, 1 << 29);
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writel(0xF800F8C0, 0x0232bfe4);
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clrbits_le32(0x0232a628, 1 << 29);
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writel(0xF800F8C0, 0x0232bfe8);
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clrbits_le32(0x0232a828, 1 << 29);
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writel(0xF800F8C0, 0x0232bfec);
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/*Enable pll via the pll_ctrl 0x0014*/
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writel(0xe0000000, 0x0232bff4)
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;
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/*Waiting for SGMII Serdes PLL lock.*/
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for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--)
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;
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for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--)
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;
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for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--)
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;
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for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--)
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;
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udelay(45000);
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}
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void sgmii_serdes_shutdown(void)
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{
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/*
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* shutdown SerDes hardware. SerDes hardware vendor published only
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* register addresses and their values. So had to use hardcoded
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* values below.
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*/
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clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13);
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setbits_le32(0x02320228, 1 << 29);
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clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13);
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setbits_le32(0x02320428, 1 << 29);
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clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13);
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setbits_le32(0x02320628, 1 << 29);
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clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13);
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setbits_le32(0x02320828, 1 << 29);
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clrbits_le32(0x02320034, 3 << 29);
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setbits_le32(0x02320010, 1 << 28);
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ks2_serdes_sgmii_156p25mhz_setup();
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}
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5
drivers/soc/Makefile
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5
drivers/soc/Makefile
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@ -0,0 +1,5 @@
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#
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# Makefile for the U-boot SOC specific device drivers.
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#
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obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
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1
drivers/soc/keystone/Makefile
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1
drivers/soc/keystone/Makefile
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@ -0,0 +1 @@
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obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o
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127
drivers/soc/keystone/keystone_serdes.c
Normal file
127
drivers/soc/keystone/keystone_serdes.c
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@ -0,0 +1,127 @@
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/*
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* TI serdes driver for keystone2.
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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void ks2_serdes_sgmii_156p25mhz_setup(void)
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{
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unsigned int cnt;
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/*
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* configure Serializer/Deserializer (SerDes) hardware. SerDes IP
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* hardware vendor published only register addresses and their values
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* to be used for configuring SerDes. So had to use hardcoded values
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* below.
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*/
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clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000);
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clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282);
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clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438);
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clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700);
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clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000);
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clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080);
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clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000);
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clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000);
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clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000);
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clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8);
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clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4);
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clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400);
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clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800);
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clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082);
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clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385);
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clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800);
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clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000);
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clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00);
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clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600);
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clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000);
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clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000);
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clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000);
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clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b);
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clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000);
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clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e);
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clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003);
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clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f);
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clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00);
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clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72);
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clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100);
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clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060);
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clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000);
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clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220);
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clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602);
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clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1);
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clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989);
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clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001);
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clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000);
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clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000);
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clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d);
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/*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/
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clrbits_le32(0x0232a010, 1 << 28);
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/* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */
|
||||
clrbits_le32(0x0232a228, 1 << 29);
|
||||
writel(0xF800F8C0, 0x0232bfe0);
|
||||
clrbits_le32(0x0232a428, 1 << 29);
|
||||
writel(0xF800F8C0, 0x0232bfe4);
|
||||
clrbits_le32(0x0232a628, 1 << 29);
|
||||
writel(0xF800F8C0, 0x0232bfe8);
|
||||
clrbits_le32(0x0232a828, 1 << 29);
|
||||
writel(0xF800F8C0, 0x0232bfec);
|
||||
|
||||
/*Enable pll via the pll_ctrl 0x0014*/
|
||||
writel(0xe0000000, 0x0232bff4)
|
||||
;
|
||||
|
||||
/*Waiting for SGMII Serdes PLL lock.*/
|
||||
for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--)
|
||||
;
|
||||
for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--)
|
||||
;
|
||||
for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--)
|
||||
;
|
||||
for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--)
|
||||
;
|
||||
|
||||
udelay(45000);
|
||||
}
|
||||
@ -41,4 +41,7 @@
|
||||
#define CONFIG_KSNET_NETCP_V1_0
|
||||
#define CONFIG_KSNET_CPSW_NUM_PORTS 5
|
||||
|
||||
/* SerDes */
|
||||
#define CONFIG_TI_KEYSTONE_SERDES
|
||||
|
||||
#endif /* __CONFIG_K2HK_EVM_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user