mtd: rawnand: stm32_fmc2: remove useless inline comments
Remove inline comments that are useless since function label are self explanatory. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
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@ -179,7 +179,6 @@ static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base)
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return container_of(base, struct stm32_fmc2_nfc, base);
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}
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/* Timings configuration */
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static void stm32_fmc2_timings_init(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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@ -211,7 +210,6 @@ static void stm32_fmc2_timings_init(struct nand_chip *chip)
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writel(patt, fmc2->io_base + FMC2_PATT);
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}
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/* Controller configuration */
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static void stm32_fmc2_setup(struct nand_chip *chip)
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{
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struct stm32_fmc2_nfc *fmc2 = to_stm32_nfc(chip->controller);
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@ -239,7 +237,6 @@ static void stm32_fmc2_setup(struct nand_chip *chip)
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writel(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Select target */
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static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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@ -256,14 +253,10 @@ static void stm32_fmc2_select_chip(struct mtd_info *mtd, int chipnr)
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chip->IO_ADDR_R = fmc2->data_base[fmc2->cs_sel];
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chip->IO_ADDR_W = fmc2->data_base[fmc2->cs_sel];
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/* FMC2 setup routine */
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stm32_fmc2_setup(chip);
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/* Apply timings */
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stm32_fmc2_timings_init(chip);
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}
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/* Set bus width to 16-bit or 8-bit */
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static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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@ -274,7 +267,6 @@ static void stm32_fmc2_set_buswidth_16(struct stm32_fmc2_nfc *fmc2, bool set)
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writel(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Enable/disable ECC */
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static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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@ -285,13 +277,11 @@ static void stm32_fmc2_set_ecc(struct stm32_fmc2_nfc *fmc2, bool enable)
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writel(pcr, fmc2->io_base + FMC2_PCR);
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}
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/* Clear irq sources in case of bch is used */
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static inline void stm32_fmc2_clear_bch_irq(struct stm32_fmc2_nfc *fmc2)
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{
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writel(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
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}
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/* Send command and address cycles */
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static void stm32_fmc2_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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@ -361,7 +351,6 @@ static int stm32_fmc2_ham_calculate(struct mtd_info *mtd, const u8 *data,
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ecc[1] = heccr >> 8;
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ecc[2] = heccr >> 16;
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/* Disable ecc */
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stm32_fmc2_set_ecc(fmc2, false);
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return 0;
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@ -466,13 +455,11 @@ static int stm32_fmc2_bch_calculate(struct mtd_info *mtd, const u8 *data,
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ecc[12] = bchpbr;
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}
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/* Disable ecc */
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stm32_fmc2_set_ecc(fmc2, false);
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return 0;
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}
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/* BCH algorithm correction */
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static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
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u8 *read_ecc, u8 *calc_ecc)
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{
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@ -497,7 +484,6 @@ static int stm32_fmc2_bch_correct(struct mtd_info *mtd, u8 *dat,
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bchdsr3 = readl(fmc2->io_base + FMC2_BCHDSR3);
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bchdsr4 = readl(fmc2->io_base + FMC2_BCHDSR4);
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/* Disable ECC */
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stm32_fmc2_set_ecc(fmc2, false);
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/* No errors found */
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@ -579,7 +565,6 @@ static int stm32_fmc2_read_page(struct mtd_info *mtd,
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return max_bitflips;
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}
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/* Controller initialization */
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static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
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{
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u32 pcr = readl(fmc2->io_base + FMC2_PCR);
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@ -622,7 +607,6 @@ static void stm32_fmc2_init(struct stm32_fmc2_nfc *fmc2)
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writel(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
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}
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/* Controller timings */
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static void stm32_fmc2_calc_timings(struct nand_chip *chip,
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const struct nand_sdr_timings *sdrt)
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{
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@ -768,13 +752,11 @@ static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr,
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stm32_fmc2_calc_timings(chip, sdrt);
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/* Apply timings */
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stm32_fmc2_timings_init(chip);
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return 0;
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}
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/* NAND callbacks setup */
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static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
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{
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chip->ecc.hwctl = stm32_fmc2_hwctl;
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@ -803,7 +785,6 @@ static void stm32_fmc2_nand_callbacks_setup(struct nand_chip *chip)
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chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7;
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}
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/* FMC2 caps */
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static int stm32_fmc2_calc_ecc_bytes(int step_size, int strength)
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{
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/* Hamming */
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@ -822,7 +803,6 @@ NAND_ECC_CAPS_SINGLE(stm32_fmc2_ecc_caps, stm32_fmc2_calc_ecc_bytes,
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FMC2_ECC_STEP_SIZE,
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FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8);
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/* FMC2 probe */
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static int stm32_fmc2_parse_child(struct stm32_fmc2_nfc *fmc2,
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ofnode node)
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{
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@ -969,7 +949,6 @@ static int stm32_fmc2_probe(struct udevice *dev)
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reset_deassert(&reset);
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}
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/* FMC2 init routine */
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stm32_fmc2_init(fmc2);
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chip->controller = &fmc2->base;
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@ -985,7 +964,6 @@ static int stm32_fmc2_probe(struct udevice *dev)
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chip->ecc.size = FMC2_ECC_STEP_SIZE;
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chip->ecc.strength = FMC2_ECC_BCH8;
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/* Scan to find existence of the device */
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ret = nand_scan_ident(mtd, nand->ncs, NULL);
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if (ret)
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return ret;
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@ -1012,7 +990,6 @@ static int stm32_fmc2_probe(struct udevice *dev)
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if (chip->bbt_options & NAND_BBT_USE_FLASH)
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chip->bbt_options |= NAND_BBT_NO_OOB;
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/* NAND callbacks setup */
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stm32_fmc2_nand_callbacks_setup(chip);
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/* Define ECC layout */
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@ -1026,11 +1003,9 @@ static int stm32_fmc2_probe(struct udevice *dev)
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ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset;
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chip->ecc.layout = ecclayout;
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/* Configure bus width to 16-bit */
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if (chip->options & NAND_BUSWIDTH_16)
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stm32_fmc2_set_buswidth_16(fmc2, true);
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/* Scan the device to fill MTD data-structures */
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ret = nand_scan_tail(mtd);
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if (ret)
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return ret;
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