m68k: add board stmark2, mcf5441x based
Sysam stmark2 board is a generic and fully (hw and sw) open board, with a mcf54415 Coldfire CPU, 128MB of DDR2, 16MB of SPI flash and SD card as non volatile memories, and a wifi module included on-board. The board is actually used mainly for Coldfire custodian testing activity related to the mcf5441x Coldfire family. For further information please see: http://sysam.it/cff_stmark2.html Signed-off-by: Angelo Dureghello <angelo@sysam.it> --- Changes in v2: - remove CMD_REGINFO - add board information in commit message
This commit is contained in:
Angelo Dureghello
parent
02a6eddaba
commit
a373024e7f
@ -200,6 +200,10 @@ config TARGET_AMCORE
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bool "Support AMCORE"
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select M5307
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config TARGET_STMARK2
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bool "Support stmark2"
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select M54418
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endchoice
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source "board/BuS/eb_cpu5282/Kconfig"
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@ -223,5 +227,6 @@ source "board/freescale/m54455evb/Kconfig"
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source "board/freescale/m547xevb/Kconfig"
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source "board/freescale/m548xevb/Kconfig"
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source "board/sysam/amcore/Kconfig"
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source "board/sysam/stmark2/Kconfig"
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endmenu
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15
board/sysam/stmark2/Kconfig
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15
board/sysam/stmark2/Kconfig
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@ -0,0 +1,15 @@
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if TARGET_STMARK2
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config SYS_CPU
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default "mcf5445x"
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config SYS_BOARD
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default "stmark2"
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config SYS_VENDOR
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default "sysam"
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config SYS_CONFIG_NAME
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default "stmark2"
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endif
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6
board/sysam/stmark2/MAINTAINERS
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6
board/sysam/stmark2/MAINTAINERS
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@ -0,0 +1,6 @@
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STMARK2 BOARD
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M: Angelo Dureghello <angelo@sysam.it>
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S: Maintained
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F: board/sysam/stmark2/
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F: include/configs/stmark2.h
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F: configs/stmark2_defconfig
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8
board/sysam/stmark2/Makefile
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8
board/sysam/stmark2/Makefile
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@ -0,0 +1,8 @@
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#
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# (C) Copyright 2014 Angelo Dureghello <angelo@sysam.it>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = stmark2.o
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extra-y += sbf_dram_init.o
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119
board/sysam/stmark2/sbf_dram_init.S
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119
board/sysam/stmark2/sbf_dram_init.S
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@ -0,0 +1,119 @@
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/*
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* Board-specific early ddr/sdram init.
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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.equ PPMCR0, 0xfc04002d
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.equ MSCR_SDRAMC, 0xec094060
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.equ MISCCR2, 0xec09001a
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.equ DDR_RCR, 0xfc0b8180
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.equ DDR_PADCR, 0xfc0b81ac
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.equ DDR_CR00, 0xfc0b8000
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.equ DDR_CR06, 0xfc0b8018
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.equ DDR_CR09, 0xfc0b8024
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.equ DDR_CR40, 0xfc0b80a0
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.equ DDR_CR45, 0xfc0b80b4
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.equ DDR_CR56, 0xfc0b80e0
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.global sbf_dram_init
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.text
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sbf_dram_init:
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/* CD46 = DDR on */
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move.l #PPMCR0, %a1
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move.b #46, (%a1)
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/* stmark 2, max drive strength */
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move.l #MSCR_SDRAMC, %a1
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move.b #1, (%a1)
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/*
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* use cpu clock, seems more realiable
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*
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* DDR2 clock is serviced from DDR controller as input clock / 2
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* so, if clock comes from
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* vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
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* cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
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*
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* .
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* / \ DDR2 can't be clocked lower than 125Mhz
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* / ! \ DDR2 init must pass further i/dcache enable test
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* /_____\
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* WARNING
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*/
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/* cpu / 2 = 125 Mhz for 480 Mhz pll */
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move.l #MISCCR2, %a1
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move.w #0xa01d, (%a1)
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/* DDR force sw reset settings */
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move.l #DDR_RCR, %a1
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move.l #0x00000000, (%a1)
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move.l #0x40000000, (%a1)
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/*
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* PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
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* 500/700 mV are ok
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*/
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move.l #DDR_PADCR, %a1
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move.l #0x01030203, (%a1) /* as freescale tower */
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move.l #DDR_CR00, %a1
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move.l #0x01010101, (%a1)+ /* 0x00 */
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move.l #0x00000101, (%a1)+ /* 0x04 */
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move.l #0x01010100, (%a1)+ /* 0x08 */
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move.l #0x01010000, (%a1)+ /* 0x0C */
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move.l #0x00010101, (%a1)+ /* 0x10 */
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move.l #DDR_CR06, %a1
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move.l #0x00010100, (%a1)+ /* 0x18 */
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move.l #0x00000001, (%a1)+ /* 0x1C */
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move.l #0x01000001, (%a1)+ /* 0x20 */
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move.l #0x00000100, (%a1)+ /* 0x24 */
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move.l #0x00010001, (%a1)+ /* 0x28 */
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move.l #0x00000200, (%a1)+ /* 0x2C */
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move.l #0x01000002, (%a1)+ /* 0x30 */
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move.l #0x00000000, (%a1)+ /* 0x34 */
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move.l #0x00000100, (%a1)+ /* 0x38 */
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move.l #0x02000100, (%a1)+ /* 0x3C */
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move.l #0x02000407, (%a1)+ /* 0x40 */
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move.l #0x02030007, (%a1)+ /* 0x44 */
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move.l #0x02000100, (%a1)+ /* 0x48 */
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move.l #0x0A030203, (%a1)+ /* 0x4C */
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move.l #0x00020708, (%a1)+ /* 0x50 */
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move.l #0x00050008, (%a1)+ /* 0x54 */
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move.l #0x04030002, (%a1)+ /* 0x58 */
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move.l #0x00000004, (%a1)+ /* 0x5C */
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move.l #0x020A0000, (%a1)+ /* 0x60 */
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move.l #0x0C00000E, (%a1)+ /* 0x64 */
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move.l #0x00002004, (%a1)+ /* 0x68 */
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move.l #0x00000000, (%a1)+ /* 0x6C */
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move.l #0x00100010, (%a1)+ /* 0x70 */
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move.l #0x00100010, (%a1)+ /* 0x74 */
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move.l #0x00000000, (%a1)+ /* 0x78 */
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move.l #0x07990000, (%a1)+ /* 0x7C */
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move.l #DDR_CR40, %a1
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move.l #0x00000000, (%a1)+ /* 0xA0 */
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move.l #0x00C80064, (%a1)+ /* 0xA4 */
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move.l #0x44520002, (%a1)+ /* 0xA8 */
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move.l #0x00C80023, (%a1)+ /* 0xAC */
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move.l #DDR_CR45, %a1
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move.l #0x0000C350, (%a1) /* 0xB4 */
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move.l #DDR_CR56, %a1
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move.l #0x04000000, (%a1)+ /* 0xE0 */
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move.l #0x03000304, (%a1)+ /* 0xE4 */
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move.l #0x40040000, (%a1)+ /* 0xE8 */
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move.l #0xC0004004, (%a1)+ /* 0xEC */
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move.l #0x0642C000, (%a1)+ /* 0xF0 */
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move.l #0x00000642, (%a1)+ /* 0xF4 */
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move.l #DDR_CR09, %a1
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tpf
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move.l #0x01000100, (%a1) /* 0x24 */
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move.l #0x2000, %d1
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bsr asm_delay
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rts
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47
board/sysam/stmark2/stmark2.c
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47
board/sysam/stmark2/stmark2.c
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@ -0,0 +1,47 @@
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/*
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* Board-specific init.
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <asm/immap.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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/*
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* need to to:
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* Check serial flash size. if 2mb evb, else 8mb demo
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*/
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puts("Board: ");
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puts("Sysam stmark2\n");
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return 0;
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}
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int dram_init(void)
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{
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u32 dramsize;
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/*
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* Serial Boot: The dram is already initialized in start.S
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* only require to return DRAM size
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*/
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
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gd->ram_size = dramsize;
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return 0;
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}
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int testdram(void)
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{
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return 0;
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}
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26
configs/stmark2_defconfig
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26
configs/stmark2_defconfig
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@ -0,0 +1,26 @@
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CONFIG_M68K=y
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CONFIG_SYS_TEXT_BASE=0x47E00000
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CONFIG_TARGET_STMARK2=y
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CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000"
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# CONFIG_DISPLAY_BOARDINFO is not set
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# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="stmark2 $ "
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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CONFIG_CMD_LOADB=y
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# CONFIG_CMD_LOADS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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# CONFIG_CMD_FPGA is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NET is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_CACHE=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_REGEX=y
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199
include/configs/stmark2.h
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199
include/configs/stmark2.h
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@ -0,0 +1,199 @@
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/*
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* Sysam stmark2 board configuration
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*
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* (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __STMARK2_CONFIG_H
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#define __STMARK2_CONFIG_H
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#define CONFIG_STMARK2
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#define CONFIG_HOSTNAME stmark2
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#define CONFIG_MCFUART
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#define CONFIG_SYS_UART_PORT 0
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
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#define LDS_BOARD_TEXT \
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board/sysam/stmark2/sbf_dram_init.o (.text*)
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTARGS \
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"console=ttyS0,115200 root=/dev/ram0 rw " \
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"rootfstype=ramfs " \
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"rdinit=/bin/init " \
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"devtmpfs.mount=1"
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#define CONFIG_BOOTCOMMAND \
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"sf probe 0:1 50000000; " \
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"sf read ${loadaddr} 0x100000 ${kern_size}; " \
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"bootm ${loadaddr}"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"kern_size=0x700000\0" \
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"loadaddr=0x40001000\0" \
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"-(rootfs)\0" \
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"update_uboot=loady ${loadaddr}; " \
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"sf probe 0:1 50000000; " \
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"sf erase 0 0x80000; " \
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"sf write ${loadaddr} 0 ${filesize}\0" \
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"update_kernel=loady ${loadaddr}; " \
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"setenv kern_size ${filesize}; saveenv; " \
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"sf probe 0:1 50000000; " \
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"sf erase 0x100000 0x700000; " \
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"sf write ${loadaddr} 0x100000 ${filesize}\0" \
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"update_rootfs=loady ${loadaddr}; " \
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"sf probe 0:1 50000000; " \
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"sf erase 0x00800000 0x100000; " \
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"sf write ${loadaddr} 0x00800000 ${filesize}\0" \
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""
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/* Realtime clock */
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#undef CONFIG_MCFRTC
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#define CONFIG_RTC_MCFRRTC
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#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
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/* spi not partitions */
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_DEV "nor0"
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#define MTDIDS_DEFAULT "nor0=spi-flash.0"
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#define MTDPARTS_DEFAULT \
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"mtdparts=spi-flash.0:" \
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"1m(u-boot)," \
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"7m(kernel)," \
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"-(rootfs)"
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/* Timer */
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#define CONFIG_MCFTMR
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#undef CONFIG_MCFPIT
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/* DSPI and Serial Flash */
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#define CONFIG_CF_SPI
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#define CONFIG_CF_DSPI
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#define CONFIG_SF_DEFAULT_SPEED 50000000
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#define CONFIG_SERIAL_FLASH
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#define CONFIG_HARD_SPI
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#define CONFIG_SPI_FLASH_ISSI
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 1
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#define CONFIG_SYS_SBFHDR_SIZE 0x7
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#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
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DSPI_CTAR_PCSSCK_1CLK | \
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DSPI_CTAR_PASC(0) | \
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DSPI_CTAR_PDT(0) | \
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DSPI_CTAR_CSSCK(0) | \
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DSPI_CTAR_ASC(0) | \
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DSPI_CTAR_DT(1) | \
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DSPI_CTAR_BR(6))
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#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
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#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
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/* Input, PCI, Flexbus, and VCO */
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#define CONFIG_EXTRA_CLOCK
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#define CONFIG_PRAM 2048 /* 2048 KB */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_MAXARGS 16
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
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#define CONFIG_SYS_MBAR 0xFC000000
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/*
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* Definitions for initial stack pointer and data area (in internal SRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
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/* End of used area in internal SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
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#define CONFIG_SYS_INIT_RAM_CTRL 0x221
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#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE) - 32)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
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/*
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
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#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
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#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
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#define CONFIG_SYS_DRAM_TEST
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#if defined(CONFIG_CF_SBF)
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#define CONFIG_SERIAL_BOOT
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#endif
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#if defined(CONFIG_SERIAL_BOOT)
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
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#else
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#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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#endif
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#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
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/* Reserve 256 kB for Monitor */
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#define CONFIG_SYS_MONITOR_LEN (256 << 10)
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/* Reserve 256 kB for malloc() */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization ??
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*/
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
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(CONFIG_SYS_SDRAM_SIZE << 20))
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/* Configuration for environment
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* Environment is embedded in u-boot in the second sector of the flash
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*/
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#if defined(CONFIG_CF_SBF)
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#define CONFIG_ENV_IS_IN_SPI_FLASH 1
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#define CONFIG_ENV_SPI_CS 1
|
||||
#define CONFIG_ENV_OFFSET 0x40000
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x10000
|
||||
#endif
|
||||
|
||||
#undef CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - 8)
|
||||
#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - 4)
|
||||
#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
|
||||
#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
|
||||
#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
|
||||
CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
|
||||
CF_ACR_EN | CF_ACR_SM_ALL)
|
||||
#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
|
||||
CF_CACR_ICINVA | CF_CACR_EUSP)
|
||||
#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
|
||||
CF_CACR_DEC | CF_CACR_DDCM_P | \
|
||||
CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
|
||||
|
||||
#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
|
||||
CONFIG_SYS_INIT_RAM_SIZE - 12)
|
||||
|
||||
#endif /* __STMARK2_CONFIG_H */
|
||||
@ -2294,6 +2294,7 @@ CONFIG_STM32_GPIO
|
||||
CONFIG_STM32_HSE_HZ
|
||||
CONFIG_STM32_HZ
|
||||
CONFIG_STM32_SERIAL
|
||||
CONFIG_STMARK2
|
||||
CONFIG_STRIDER
|
||||
CONFIG_STRIDER_CON
|
||||
CONFIG_STRIDER_CON_DP
|
||||
|
||||
Loading…
Reference in New Issue
Block a user