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x86: Add Intel Cougar Canyon 2 board

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This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2016-02-17 00:16:25 -08:00
parent 87077e97d1
commit a2e3b05e16
12 changed files with 298 additions and 0 deletions
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4
arch/x86/cpu/ivybridge/Kconfig
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@ -79,4 +79,8 @@ config FSP_USE_UPD
bool
default n
config FSP_BROKEN_HOB
bool
default y
endif

1
arch/x86/dts/Makefile
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@ -5,6 +5,7 @@
dtb-y += bayleybay.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
cougarcanyon2.dtb \
crownbay.dtb \
efi.dtb \
galileo.dtb \

104
arch/x86/dts/cougarcanyon2.dts Normal file
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@ -0,0 +1,104 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "keyboard.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
/ {
model = "Intel Cougar Canyon 2";
compatible = "intel,cougarcanyon2", "intel,chiefriver";
aliases {
spi0 = &spi0;
};
config {
silent_console = <0>;
};
chosen {
stdout-path = "/serial";
};
microcode {
update@0 {
#include "microcode/m12306a2_00000008.dtsi"
};
update@1 {
#include "microcode/m12306a4_00000007.dtsi"
};
update@2 {
#include "microcode/m12306a5_00000007.dtsi"
};
update@3 {
#include "microcode/m12306a8_00000010.dtsi"
};
update@4 {
#include "microcode/m12306a9_0000001b.dtsi"
};
};
fsp {
compatible = "intel,ivybridge-fsp";
fsp,enable-ht;
};
pci {
#address-cells = <3>;
#size-cells = <2>;
compatible = "pci-x86";
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,bd82x6x";
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
spi0: spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
spi-flash@0 {
reg = <0>;
compatible = "winbond,w25q64bv", "spi-flash";
memory-map = <0xff800000 0x00800000>;
};
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
bank-name = "C";
};
};
};
};

9
board/intel/Kconfig
View File

@ -18,6 +18,14 @@ config TARGET_BAYLEYBAY
4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,
PCIe and some other sensor interfaces.
config TARGET_COUGARCANYON2
bool "Cougar Canyon 2"
help
This is the Intel Cougar Canyon 2 Customer Reference Board. It
is built on the Chief River platform with Intel Ivybridge Processor
and Panther Point chipset. The board has 4GB RAM, with some other
peripheral connectors for PCIe/SATA/USB2/USB3/LAN/UART/PS2/VGA/HDMI.
config TARGET_CROWNBAY
bool "Crown Bay"
help
@ -54,6 +62,7 @@ config TARGET_MINNOWMAX
endchoice
source "board/intel/bayleybay/Kconfig"
source "board/intel/cougarcanyon2/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/galileo/Kconfig"
source "board/intel/minnowmax/Kconfig"

25
board/intel/cougarcanyon2/Kconfig Normal file
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@ -0,0 +1,25 @@
if TARGET_COUGARCANYON2
config SYS_BOARD
default "cougarcanyon2"
config SYS_VENDOR
default "intel"
config SYS_SOC
default "ivybridge"
config SYS_CONFIG_NAME
default "cougarcanyon2"
config SYS_TEXT_BASE
default 0xffe00000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
select NORTHBRIDGE_INTEL_IVYBRIDGE
select HAVE_FSP
select BOARD_ROMSIZE_KB_2048
endif

6
board/intel/cougarcanyon2/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
INTEL COUGAR CANYON 2 BOARD
M: Bin Meng <bmeng.cn@gmail.com>
S: Maintained
F: board/intel/cougarcanyon2/
F: include/configs/cougarcanyon2.h
F: configs/cougarcanyon2_defconfig

7
board/intel/cougarcanyon2/Makefile Normal file
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@ -0,0 +1,7 @@
#
# Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += cougarcanyon2.o start.o

58
board/intel/cougarcanyon2/cougarcanyon2.c Normal file
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@ -0,0 +1,58 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <pci.h>
#include <smsc_sio1007.h>
#include <asm/ibmpc.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>
#define SIO1007_RUNTIME_IOPORT 0x180
int board_early_init_f(void)
{
struct udevice *pch;
int ret;
ret = uclass_first_device(UCLASS_PCH, &pch);
if (ret)
return ret;
if (!pch)
return -ENODEV;
/* Initialize LPC interface to turn on superio chipset decode range */
dm_pci_write_config16(pch, LPC_IO_DEC, COMA_DEC_RANGE | COMB_DEC_RANGE);
dm_pci_write_config16(pch, LPC_EN, KBC_LPC_EN | COMA_LPC_EN);
dm_pci_write_config32(pch, LPC_GEN1_DEC, GEN_DEC_RANGE_256B |
(SIO1007_IOPORT3 & 0xff00) | GEN_DEC_RANGE_EN);
dm_pci_write_config32(pch, LPC_GEN2_DEC, GEN_DEC_RANGE_16B |
SIO1007_RUNTIME_IOPORT | GEN_DEC_RANGE_EN);
/* Enable legacy serial port at 0x3f8 */
sio1007_enable_serial(SIO1007_IOPORT3, 0, UART0_BASE, UART0_IRQ);
/* Enable SIO1007 runtime I/O port at 0x180 */
sio1007_enable_runtime(SIO1007_IOPORT3, SIO1007_RUNTIME_IOPORT);
/*
* On Cougar Canyon 2 board, the RS232 transiver connected to serial
* port 0 (0x3f8) is controlled by a GPIO pin (GPIO10) on the SIO1007.
* Set the pin value to 1 to enable the RS232 transiver.
*/
sio1007_gpio_config(SIO1007_IOPORT3, 0, GPIO_DIR_OUTPUT,
GPIO_POL_NO_INVERT, GPIO_TYPE_PUSH_PULL);
sio1007_gpio_set_value(SIO1007_RUNTIME_IOPORT, 0, 1);
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

9
board/intel/cougarcanyon2/start.S Normal file
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@ -0,0 +1,9 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
.globl early_board_init
early_board_init:
jmp early_board_init_ret

20
configs/cougarcanyon2_defconfig Normal file
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@ -0,0 +1,20 @@
CONFIG_X86=y
CONFIG_VENDOR_INTEL=y
CONFIG_DEFAULT_DEVICE_TREE="cougarcanyon2"
CONFIG_TARGET_COUGARCANYON2=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_OF_CONTROL=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_ICH_SPI=y
CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y

21
doc/README.x86
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@ -133,6 +133,27 @@ $ make all
---
Intel Cougar Canyon 2 specific instructions for bare mode:
This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors
with mobile Intel HM76 and QM77 chipsets platform. Download it from Intel FSP
website and put the .fd file (CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd at the
time of writing) in the board directory and rename it to fsp.bin.
Now build U-Boot and obtain u-boot.rom
$ make cougarcanyon2_defconfig
$ make all
The board has two 8MB SPI flashes mounted, which are called SPI-0 and SPI-1 in
the board manual. The SPI-0 flash should have flash descriptor plus ME firmware
and SPI-1 flash is used to store U-Boot. For convenience, the complete 8MB SPI-0
flash image is included in the FSP package (named Rom00_8M_MB_PPT.bin). Program
this image to the SPI-0 flash according to the board manual just once and we are
all set. For programming U-Boot we just need to program SPI-1 flash.
---
Intel Minnowboard Max instructions for bare mode:
This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.

34
include/configs/cougarcanyon2.h Normal file
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@ -0,0 +1,34 @@
/*
* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#define CONFIG_SYS_MONITOR_LEN (2 << 20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SMSC_SIO1007
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x5ff000
/* Video is not supported for now */
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
#endif /* __CONFIG_H */