ColdFire: Add SBF support for M52277EVB

Add serial boot support

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

Makefile

@@ -1932,7 +1932,27 @@ ZPC1900_config: unconfig
 ## Coldfire
 #########################################################################
 
-M52277EVB_config:	unconfig
+M52277EVB_config \
+M52277EVB_spansion_config \
+M52277EVB_stmicro_config :	unconfig
+	@case "$@" in \
+	M52277EVB_config)		FLASH=SPANSION;; \
+	M52277EVB_spansion_config)	FLASH=SPANSION;; \
+	M52277EVB_stmicro_config)	FLASH=STMICRO;; \
+	esac; \
+	if [ "$${FLASH}" = "SPANSION" ] ; then \
+		echo "#define CONFIG_SYS_SPANSION_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+		cp $(obj)board/freescale/m52277evb/u-boot.spa $(obj)board/freescale/m52277evb/u-boot.lds ; \
+		$(XECHO) "... with SPANSION boot..." ; \
+	fi; \
+	if [ "$${FLASH}" = "STMICRO" ] ; then \
+		echo "#define CONFIG_CF_SBF"	>> $(obj)include/config.h ; \
+		echo "#define CONFIG_SYS_STMICRO_BOOT"	>> $(obj)include/config.h ; \
+		echo "TEXT_BASE = 0x43E00000" > $(obj)board/freescale/m52277evb/config.tmp ; \
+		cp $(obj)board/freescale/m52277evb/u-boot.stm $(obj)board/freescale/m52277evb/u-boot.lds ; \
+		$(XECHO) "... with ST Micro boot..." ; \
+	fi
 	@$(MKCONFIG) -a M52277EVB m68k mcf5227x m52277evb freescale
 
 M5235EVB_config \

board/freescale/m52277evb/config.mk

@@ -22,4 +22,6 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)

board/freescale/m52277evb/m52277evb.c

@@ -38,8 +38,18 @@ int checkboard(void)
 
 phys_size_t initdram(int board_type)
 {
+	u32 dramsize;
+
+#ifdef CONFIG_CF_SBF
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+#else
 	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
-	u32 dramsize, i;
+	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
+	u32 i;
 
 	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
@@ -49,6 +59,8 @@ phys_size_t initdram(int board_type)
 	}
 	i--;
 
+	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
+
 	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
 
 	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
@@ -56,24 +68,30 @@ phys_size_t initdram(int board_type)
 
 	/* Issue PALL */
 	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	__asm__("nop");
 
 	/* Issue LEMR */
-	/*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
 	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
+	__asm__("nop");
+	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
+	__asm__("nop");
 
 	udelay(1000);
 
 	/* Issue PALL */
 	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
+	__asm__("nop");
 
 	/* Perform two refresh cycles */
 	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	__asm__("nop");
 	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	__asm__("nop");
 
-	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
 
 	udelay(100);
-
+#endif
 	return (dramsize);
 };
 

board/freescale/m52277evb/u-boot.stm

@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(m68k)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    /* WARNING - the following is hand-optimized to fit within	*/
+    /* the sector layout of our flash chips!	XXX FIXME XXX	*/
+
+    cpu/mcf5227x/start.o		(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+
+  .reloc   :
+  {
+    __got_start = .;
+    *(.got)
+    __got_end = .;
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   _sbss = .;
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+   _ebss = .;
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}

cpu/mcf5227x/Makefile

@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o dspi.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

cpu/mcf5227x/cpu_init.c

@@ -45,6 +45,7 @@ void cpu_init_f(void)
 	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
 
+#if !defined(CONFIG_CF_SBF)
 	/* Workaround, must place before fbcs */
 	pll->psr = 0x12;
 
@@ -58,37 +59,44 @@ void cpu_init_f(void)
 	scm1->pacrg = 0;
 	scm1->pacri = 0;
 
-#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
 	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
 	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
 	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
 #endif
+#endif				/* CONFIG_CF_SBF */
 
-#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
 	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
 	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
 	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
 	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
 	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
 	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
 	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
 	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
 	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
 	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
 	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
 	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
 #endif
 
-#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
 	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
 	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
 	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;

cpu/mcf5227x/dspi.c

@@ -0,0 +1,261 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+
+void dspi_init(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	gpio->par_dspi =
+	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	    GPIO_PAR_DSPI_SCK_SCK;
+
+	dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+	    DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+#ifdef CONFIG_SYS_DSPI_DCTAR0
+	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR1
+	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR2
+	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR3
+	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR4
+	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR5
+	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR6
+	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR7
+	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
+#endif
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+	dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	while ((dspi->dsr & 0x000000F0) == 0) ;
+
+	return (dspi->drfr & 0xFFFF);
+}
+
+#if defined(CONFIG_CMD_SPI)
+void spi_init_f(void)
+{
+}
+
+void spi_init_r(void)
+{
+}
+
+void spi_init(void)
+{
+	dspi_init();
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct spi_slave *slave;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+		break;
+	}
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	switch (slave->cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		break;
+	}
+
+	free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	static int bWrite = 0;
+	u8 *spi_rd, *spi_wr;
+	int len = bitlen >> 3;
+
+	spi_rd = (u8 *) din;
+	spi_wr = (u8 *) dout;
+
+	/* command handling */
+	if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
+		switch (*spi_wr) {
+		case 0x02:	/* Page Prog */
+			bWrite = 1;
+			dspi_tx(slave->cs, 0x80, spi_wr[0]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[1]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[2]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[3]);
+			dspi_rx();
+			return 0;
+		case 0x05:	/* Read Status */
+			if (len == 4)
+				if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
+				    && (spi_wr[3] == 0xFF)) {
+					dspi_tx(slave->cs, 0x80, *spi_wr);
+					dspi_rx();
+				}
+			return 0;
+		case 0x06:	/* WREN */
+			dspi_tx(slave->cs, 0x00, *spi_wr);
+			dspi_rx();
+			return 0;
+		case 0x0B:	/* Fast read */
+			if ((len == 5) && (spi_wr[4] == 0)) {
+				dspi_tx(slave->cs, 0x80, spi_wr[0]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[1]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[2]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[3]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[4]);
+				dspi_rx();
+			}
+			return 0;
+		case 0x9F:	/* RDID */
+			dspi_tx(slave->cs, 0x80, *spi_wr);
+			dspi_rx();
+			return 0;
+		case 0xD8:	/* Sector erase */
+			if (len == 4)
+				if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
+					dspi_tx(slave->cs, 0x80, spi_wr[0]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x80, spi_wr[1]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x80, spi_wr[2]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x00, spi_wr[3]);
+					dspi_rx();
+				}
+			return 0;
+		}
+	}
+
+	if (bWrite)
+		len--;
+
+	while (len--) {
+		if (dout != NULL) {
+			dspi_tx(slave->cs, 0x80, *spi_wr);
+			dspi_rx();
+			spi_wr++;
+		}
+
+		if (din != NULL) {
+			dspi_tx(slave->cs, 0x80, 0);
+			*spi_rd = dspi_rx();
+			spi_rd++;
+		}
+	}
+
+	if (flags == SPI_XFER_END) {
+		if (bWrite) {
+			dspi_tx(slave->cs, 0x00, *spi_wr);
+			dspi_rx();
+			bWrite = 0;
+		} else {
+			dspi_tx(slave->cs, 0x00, 0);
+			dspi_rx();
+		}
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_CMD_SPI */
+
+#endif				/* CONFIG_CF_DSPI */

cpu/mcf5227x/speed.c

@@ -90,17 +90,33 @@ int get_clocks(void)
 	int vco, temp, pcrvalue, pfdr;
 	u8 bootmode;
 
-	bootmode = (ccm->ccr & 0x000C) >> 2;
-
 	pcrvalue = pll->pcr & 0xFF0F0FFF;
 	pfdr = pcrvalue >> 24;
 
-	if (pfdr != 0x1E) {
+	if (pfdr == 0x1E)
+		bootmode = 0;	/* Normal Mode */
+
+#ifdef CONFIG_CF_SBF
+	bootmode = 3;		/* Serial Mode */
+#endif
+
+	if (bootmode == 0) {
+		/* Normal mode */
+		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+			/* Default value */
+			pcrvalue = (pll->pcr & 0x00FFFFFF);
+			pcrvalue |= 0x1E << 24;
+			pll->pcr = pcrvalue;
+			vco =
+			    ((pll->pcr & 0xFF000000) >> 24) *
+			    CONFIG_SYS_INPUT_CLKSRC;
+		}
+		gd->vco_clk = vco;	/* Vco clock */
+	} else if (bootmode == 3) {
 		/* serial mode */
-	} else {
+		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
-		/* Normal Mode */
+		gd->vco_clk = vco;	/* Vco clock */
-		vco = pfdr * CONFIG_SYS_INPUT_CLKSRC;
-		gd->vco_clk = vco;
 	}
 
 	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {

cpu/mcf5227x/start.S

@@ -46,6 +46,11 @@
 	addl	#60,%sp;		/* space for 15 regs */ \
 	rte;
 
+#if defined(CONFIG_CF_SBF)
+#define ASM_DRAMINIT	(asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+
 .text
 /*
  *	Vector table. This is used for initial platform startup.
@@ -53,8 +58,14 @@
  */
 _vectors:
 
-INITSP:		.long	0x00000000	/* Initial SP	*/
+#if defined(CONFIG_CF_SBF)
+INITSP:		.long	0		/* Initial SP	*/
+INITPC:		.long	ASM_DRAMINIT	/* Initial PC 	*/
+#else
+INITSP:		.long	0	/* Initial SP	*/
 INITPC:		.long	_START	/* Initial PC 		*/
+#endif
+
 vector02:	.long	_FAULT	/* Access Error		*/
 vector03:	.long	_FAULT	/* Address Error	*/
 vector04:	.long	_FAULT	/* Illegal Instruction	*/
@@ -83,6 +94,7 @@ vector1D:	.long	_FAULT	/* Autovector Level 5	*/
 vector1E:	.long	_FAULT	/* Autovector Level 6	*/
 vector1F:	.long	_FAULT	/* Autovector Level 7	*/
 
+#if !defined(CONFIG_CF_SBF)
 /* TRAP #0 - #15 */
 vector20_2F:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -122,9 +134,231 @@ vector192_255:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+#endif
+
+#if defined(CONFIG_CF_SBF)
+	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
+asm_sbf_img_hdr:
+	.long	0x00000000	/* checksum, not yet implemented */
+	.long	0x00020000	/* image length */
+	.long	TEXT_BASE	/* image to be relocated at */
+
+asm_dram_init:
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1	/* init Rambar */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+
+	/*
+	 * Dram Initialization
+	 * a1, a2, and d0
+	 */
+	/* mscr sdram */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
+
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
+	nop
+
+	move.l	#1000, %d0
+wait1000:
+	nop
+	subq.l	#1, %d0
+	bne	wait1000
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
+	and.l	#0x7FFFFFFF, %d0
+	or.l	#0x10000c00, %d0
+	move.l	%d0, (%a2)
+	nop
+
+	/*
+	 * DSPI Initialization
+	 * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
+	 * a1 - dspi status
+	 * a2 - dtfr
+	 * a3 - drfr
+	 * a4 - Dst addr
+	 */
+
+	/* Enable pins for DSPI mode - chip-selects are enabled later */
+	move.l	#0xFC0A4036, %a0
+	move.b	#0x3F, %d0
+	move.b	%d0, (%a0)
+
+	/* DSPI CS */
+#ifdef CONFIG_SYS_DSPI_CS0
+	move.b	(%a0), %d0
+	or.l	#0xC0, %d0
+	move.b	%d0, (%a0)
+#endif
+#ifdef CONFIG_SYS_DSPI_CS2
+	move.l	#0xFC0A4037, %a0
+	move.b	(%a0), %d0
+	or.l	#0x10, %d0
+	move.b	%d0, (%a0)
+#endif
+	nop
+
+	/* Configure DSPI module */
+	move.l	#0xFC05C000, %a0
+	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
+
+	move.l	#0xFC05C00C, %a0
+	move.l	#0x3E000011, (%a0)
+
+	move.l	#0xFC05C034, %a2	/* dtfr */
+	move.l	#0xFC05C03B, %a3	/* drfr */
+
+	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
+	move.l	(%a1)+, %d5
+	move.l	(%a1), %a4
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
+
+	move.l	#0xFC05C02C, %a1	/* dspi status */
+
+	/* Issue commands and address */
+	move.l	#0x8004000B, %d2	/* Fast Read Cmd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 2 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 1 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 0 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Dummy Wr and Rd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* Transfer serial boot header to sram */
+asm_dspi_rd_loop1:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a0)		/* read, copy to dst */
+
+	add.l	#1, %a0			/* inc dst by 1 */
+	sub.l	#1, %d4			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop1
+
+	/* Transfer u-boot from serial flash to memory */
+asm_dspi_rd_loop2:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a4)		/* read, copy to dst */
+
+	add.l	#1, %a4			/* inc dst by 1 */
+	sub.l	#1, %d5			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop2
+
+	move.l	#0x00040000, %d2	/* Terminate */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* jump to memory and execute */
+	move.l	#(TEXT_BASE + 0x400), %a0
+	move.l	%a0, (%a1)
+	jmp	(%a0)
+
+asm_dspi_wr_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x0000F000, %d0
+	cmp.l	#0x00003000, %d0
+	bgt	asm_dspi_wr_status
+
+	move.l	%d2, (%a2)
+	rts
+
+asm_dspi_rd_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x000000F0, %d0
+	lsr.l	#4, %d0
+	cmp.l	#0, %d0
+	beq	asm_dspi_rd_status
+
+	move.b	(%a3), %d1
+	rts
+#endif			/* CONFIG_CF_SBF */
 
 	.text
-
+	. = 0x400
 	.globl	_start
 _start:
 	nop
@@ -132,11 +366,16 @@ _start:
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
+#if defined(CONFIG_CF_SBF)
+	move.l	#TEXT_BASE, %d0
+	movec	%d0, %VBR
+#else
 	move.l	#CONFIG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
+#endif
 
 	/* initialize general use internal ram */
 	move.l #0, %d0

include/asm-m68k/m5227x.h

@@ -282,8 +282,8 @@
 
 /* Bit definitions and macros for PAR_DSPI */
 #define GPIO_PAR_DSPI_PCS0_MASK		(0x3F)
-#define GPIO_PAR_DSPI_PCS0_PCS0		(0x80)
+#define GPIO_PAR_DSPI_PCS0_PCS0		(0xC0)
-#define GPIO_PAR_DSPI_PCS0_U2RTS	(0x40)
+#define GPIO_PAR_DSPI_PCS0_U2RTS	(0x80)
 #define GPIO_PAR_DSPI_PCS0_GPIO		(0x00)
 #define GPIO_PAR_DSPI_SIN_MASK		(0xCF)
 #define GPIO_PAR_DSPI_SIN_SIN		(0x30)

include/configs/M52277EVB.h

@@ -72,19 +72,48 @@
 #define CONFIG_CMD_REGINFO
 #undef CONFIG_CMD_USB
 #undef CONFIG_CMD_BMP
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
 
 #define CONFIG_HOSTNAME			M52277EVB
+#define CONFIG_SYS_UBOOT_END		0x3FFFF
+#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
+#ifdef CONFIG_SYS_STMICRO_BOOT
+/* ST Micro serial flash */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
-	"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0"	\
+	"loadaddr=0x40010000\0"			\
-	"u-boot=u-boot.bin\0"			\
+	"uboot=u-boot.bin\0"			\
-	"load=tftp ${loadaddr) ${u-boot}\0"	\
+	"load=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
 	"upd=run load; run prog\0"		\
-	"prog=prot off 0 0x3ffff;"		\
+	"prog=sf probe 0:2 10000 1;"		\
-	"era 0 3ffff;"				\
+	"sf erase 0 30000;"			\
-	"cp.b ${loadaddr} 0 ${filesize};"	\
+	"sf write ${loadaddr} 0 30000;"		\
 	"save\0"				\
 	""
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
+	"loadaddr=0x40010000\0"			\
+	"uboot=u-boot.bin\0"			\
+	"load=loadb ${loadaddr} ${baudrate}\0"	\
+	"upd=run load; run prog\0"		\
+	"prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE)	\
+	" " MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
+	"era " MK_STR(CONFIG_SYS_FLASH_BASE) " "	\
+	MK_STR(CONFIG_SYS_UBOOT_END) ";"		\
+	"cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE)	\
+	" ${filesize}; save\0"			\
+	"updsbf=run loadsbf; run progsbf\0"	\
+	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
+	"loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
+	"progsbf=sf probe 0:2 10000 1;"		\
+	"sf erase 0 30000;"			\
+	"sf write ${loadaddr} 0 30000;"		\
+	""
+#endif
 
 #define CONFIG_BOOTDELAY		3	/* autoboot after 3 seconds */
 /* LCD */
@@ -124,12 +153,35 @@
 #define CONFIG_SYS_I2C_OFFSET		0x58000
 #define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR
 
+/* DSPI and Serial Flash */
+#define CONFIG_CF_DSPI
+#define CONFIG_HARD_SPI
+#define CONFIG_SYS_SER_FLASH_BASE	0x01000000
+#define CONFIG_SYS_SBFHDR_SIZE		0x7
+#ifdef CONFIG_CMD_SPI
+#	define CONFIG_SYS_DSPI_CS2
+#	define CONFIG_SPI_FLASH
+#	define CONFIG_SPI_FLASH_STMICRO
+
+#	define CONFIG_SYS_DSPI_DCTAR0	(DSPI_DCTAR_TRSZ(7) | \
+					 DSPI_DCTAR_CPOL | \
+					 DSPI_DCTAR_CPHA | \
+					 DSPI_DCTAR_PCSSCK_1CLK | \
+					 DSPI_DCTAR_PASC(0) | \
+					 DSPI_DCTAR_PDT(0) | \
+					 DSPI_DCTAR_CSSCK(0) | \
+					 DSPI_DCTAR_ASC(0) | \
+					 DSPI_DCTAR_PBR(0) | \
+					 DSPI_DCTAR_DT(1) | \
+					 DSPI_DCTAR_BR(1))
+#endif
+
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
 
 #define CONFIG_SYS_INPUT_CLKSRC	16000000
 
-#define CONFIG_PRAM		512	/* 512 KB */
+#define CONFIG_PRAM		2048	/* 2048 KB */
 
 #define CONFIG_SYS_PROMPT	"-> "
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
@@ -155,17 +207,18 @@
  * You should know what you are doing if you make changes here.
  */
 
-/*-----------------------------------------------------------------------
+/*
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
 #define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x21
+#define CONFIG_SYS_INIT_RAM_CTRL	0x221
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 16)
+#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
+#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)
 
-/*-----------------------------------------------------------------------
+/*
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
@@ -177,11 +230,16 @@
 #define CONFIG_SYS_SDRAM_CTRL		0xE1092000
 #define CONFIG_SYS_SDRAM_EMOD		0x81810000
 #define CONFIG_SYS_SDRAM_MODE		0x00CD0000
+#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00
 
 #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
 #define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
-#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
+#else
+#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
+#endif
 #define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
 #define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */
@@ -189,24 +247,40 @@
 /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 
-/* Configuration for environment
+/*
+ * Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
-#define CONFIG_ENV_IS_IN_FLASH	1
+#ifdef CONFIG_CF_SBF
+#	define CONFIG_ENV_IS_IN_SPI_FLASH
+#	define CONFIG_ENV_SPI_CS	2
+#else
+#	define CONFIG_ENV_IS_IN_FLASH	1
+#endif
 #define CONFIG_ENV_OVERWRITE		1
 #undef CONFIG_ENV_IS_EMBEDDED
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#ifdef CONFIG_SYS_STMICRO_BOOT
-#define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_SER_FLASH_BASE
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000)
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_SER_FLASH_BASE
-#define CONFIG_ENV_SECT_SIZE	0x8000
+#	define CONFIG_SYS_FLASH1_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_OFFSET	0x30000
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x10000
+#endif
+#ifdef CONFIG_SYS_SPANSION_BOOT
+#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
+#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000)
+#	define CONFIG_ENV_SIZE		0x1000
+#	define CONFIG_ENV_SECT_SIZE	0x8000
+#endif
 
 #define CONFIG_SYS_FLASH_CFI
 #ifdef CONFIG_SYS_FLASH_CFI
-
 #	define CONFIG_FLASH_CFI_DRIVER	1
 #	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
 #	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
@@ -214,6 +288,7 @@
 #	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
 #	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
 #	define CONFIG_SYS_FLASH_CHECKSUM
+#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
 #endif
 
 /*
@@ -243,8 +318,14 @@
  * CS5 - Available
  */
 
+#ifdef CONFIG_CF_SBF
+#define CONFIG_SYS_CS0_BASE		0x04000000
+#define CONFIG_SYS_CS0_MASK		0x00FF0001
+#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#else
 #define CONFIG_SYS_CS0_BASE		0x00000000
 #define CONFIG_SYS_CS0_MASK		0x00FF0001
 #define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#endif
 
 #endif				/* _M52277EVB_H */